Static random access memory device with a power dissipation reduction function

A static random access memory device is comprised of a write mode detector (31) for detecting a signal state transition of a write enable signal changing to an active state; an input data transition detector (32) for detecting a transition of the input data supplied from exterior, during a continuation of the active state of the write enable signal, an address signal transition detector (33) for detecting a transition of an exter­nally applied address signal during an active state of the write enable signal, a power down timer (34) for generating a pulse signal with a predetermined pulse width in response to any of the detecting signals out­putted from the write mode detector (31), input data transition detector (32), and address signal transition detector (33); a gate circuit (G1) for permitting the output data from a row decoder (13) to be transferred to memory cells (MC1 to MCn) during a period that the power down timer (34) generates a pulse signal, and for inhi­biting that data transfer during a period that the power down timer (34) rests, and a write circuit control cir­cuit (35, 19) allowing a write circuit (17) to supply write data to the bit line pair (BL1, BL1) during a period that the power down timer (34) generates a pulse signal, and prohibiting that write data transfer during a period that the power timer (34) rests.