Electronic clock device and installation comprising a plurality of electronic clock devices.

p0001The invention relates to the correction of a local schedule information using a reference time information.

p0002In an installation involving a plurality of stations interconnected by means of computer communication, it is necessary to ensure good communication between all stations that they have identical time reference. This is the case for example for embedded equipment installation in an aircraft or in a mobile such as a ship, but it can also be the case for a land-based facility.

p0003Currently, the time setting of the different clocks of the stations is carried out by more or less efficient software. The correction accuracy then varies between tens to hundreds of milliseconds. This accuracy is however insufficient in some installations including embedded systems where real time problems are critical.

p0004The invention overcomes this disadvantage by significantly improving the timing accuracy of correction of different clocks compared to a reference clock.

p0005The invention thus relates to an electronic clock comprising: - A local frequency source, - A register-counter, able to contain a local time information maintained by division from said source and frequency - a set of correction of the local time information, characterized in that the set of correction includes: . and a first register . control means having a first state in which they are able to perform at a first time, a first loading of the first register by the contents of the counter-register and a second load to a second later time to the first, the counter-register a reference time information, valid at the first time, plus the difference between the current contents of the counter-register and the contents of the first register, whereby the counter-register contents equals a local corrected time information from said reference time information.

p0006Advantageously, the set of correction comprises first receiving means for receiving information defining a sequence of first instants and second receiving means for receiving said reference time information.

p0007The second time can be defined as the time of receipt of a said reference time information in the second receiving means; this second time can also be determined by a control signal indicating the validity of the reference time information received in the second receiving means.

p0008The set of correction advantageously comprises an intermediate member adapted to output the register-counter a clock signal having a frequency synchronous to that of the local frequency source.

p0009In one embodiment, the device comprises an own sampling means for storing a data pattern sampling local time. These sampling means advantageously comprise a second register whose content is equal to a local time information of the sampling result and sampling control means for comparing the current contents of the counter-register with the contents of the second register and adapted to perform a third loading, when the compared contents are equal, the second register by a separate local time information of the sampling result.

p0010Preferably the sampling means includes a sampling register containing a sampling period, said other local sampling information then being equal to that previously contained in the expanded second register of said sampling period.

p0011The device may also comprise further dating means adapted to store a local time information in response to a dating dating control signal. These dating means advantageously comprise a third register and dating control means able to load the current contents of the counter-register in the third register in response to said control signal dating.

p0012In another embodiment of the device according to the invention, the set of correction includes a correction register containing a predetermined correction and control means then have a second state in which they are able to load, at a third time, the register-counter increased by said reference time information from said predetermined correction.

p0013Preferably, the third moment is identical to the second moment.

p0014The entire correction may also include a configuration register containing at least two control means states and the control means may also be able to deliver a record-counter overflow signal.

p0015The invention also relates to an installation comprising a plurality of electronic devices clock characterized in that the electronic clock devices are interconnected by a communication means and in that at least one of the devices includes clock generating means for generating on the communication medium a master information defining at least a first time.

p0016Very advantageously, the first moment is defined as the time of receipt of said master information by all electronic clock devices.

p0017Preferably, one of the clock devices is a clean master device to transmit on the means of communication such information reference time, the reference time information being equal to the counter-register contents loaded into said first register to said first instant .

p0018The time information of the master device reference may be issued by an external time source.

p0019Other advantages and features of the invention will appear on examining the detailed description below and the appended drawings in which:<ul><li>- Figure 1 is a schematic block diagram of an electronic clock device according to the invention,</li><li>- Figures 1A-1E illustrate five particular modes of operation of the device of Figure 1, and,</li><li>- Figure 2 is a schematic block diagram of an installation according to the invention.</li></ul>

p0020The designs involving essentially of a certain character elements are part of the description. As such they can be used not only to better understand the detailed description below, but to serve, if appropriate, the definition of the invention.

p0021If one refers to Figure 1, we see that the DH electronic clock device comprises a local frequency source F fed through a CH intermediate member whose function will be explained below, a counter-register T 32 bits. This counter-register T is able to contain a local time information maintained by IHL division from said frequency source F.

p0022The DH clock device also includes a set of correction EC local time information IHL. This correction assembly includes a first 32-bit S register, whose input is connected to the output of the register-counter T by means of two successive switches TS0 and TS1 and whose output is connected to the input of the register -meter T via two IT2 and IT3 switches. The output of the counter-register T is also connected to its input via a switch and IT4 IT2 and IT3 switches.

p0023A IHR reference time information is likely to be connected to the input of the register counter-T via the switch IT3.

p0024It should be noted here that the various switches shown not to be interpreted as function of interruption or non-interruption of connections between the components of the device. Their effective implementation will of course depend on the technology used and their functions can be optionally obtained by software instructions.

p0025The whole correction EC also includes control means MC. These MC control means are suitable for delivering a logic control signal I1 controls the switch IT1, a logic control signal I2 commanding IT3 and IT4 switches. Both I1 and I2 control signals are respectively set to "true" to the first and second moments. For notation simplicity, a first time will also be designated by reference I1 and a second time will also be designated by the reference I2.

p0026In general, the various switches shown in Figure 1 are in the position they occupy when the control signal has the value "false". For example, the switch IT1, controlled by the logic control signal I1, shown in the open position, retains this position as the logic signal I1 has the value "false" that is to say as long as does not lie in the first moment.

p0027The MC control means have a first state and a second respectively differentiated by a logic signal MOD state. When the logic signal MOD is the "true" value the control means are in the first state and when the control signal MOD is the "false" value the control means are in the second state. The TS0 and TS2 switches are controlled by the control signal MOD.

p0028The electronic clock device further comprises a second P register 32 bit whose input is connected via a switch IT5 to the output of the counter-register IT5 T. This switch is controlled by a logic control signal SI emitted by control means MC. The latter also receive permanently the contents of the second register P and the content of the counter-register T.

p0029The second register P is associated with a sample register 16-bit B whose output is connected to the input of the second register P through the switch IT5. The function of this register B will be explained below.

p0030The second register P, the sampling register B, and the control means MC are part of sampling control means capable of memorizing a sequence of local time information sampling IHLE.

p0031The set of correction EC further comprises first receiving means adapted to receive a IFI1 information defining a sequence of first instants I1, and the second receiving means adapted to receive said reference time information IHR. These first and second receiving means are combined in this embodiment in unique receiving means MR that can be, for example latch memories commonly called in English "latch". These MR receiving means are controlled by the control means MC by means of a REC control signal for issuing towards the other constituents of the clock devices of the signals arriving at the input of the receiving means.

p0032The set of correction also includes ME transmission means controlled by a logic control signal SSW output from the control means MC. These ME transmission means may also be latches memories.

p0033MR receiving means receives an SCV control signal indicating the validity of the IHR reference time information received in the second receiving means MR. The SCV control signal is transmitted to the control means MC and its meaning will be explained below.

p0034The clock device further comprises a third register 32-bit D whose input is connected to the output of the register-counter T via a IT6 switch and whose output is connected to the input means of ME transmission via a IT7 switch. Both IT6 and IT7 switches are controlled by an ICD dating control signal received by the MR receiving means and transmitted to the control means MC.

p0035The third register D and the control means MC are part of dating control means capable of memorizing a IHLD dating local time information in response to the ICD dating control signal.

p0036The whole correction EC includes a correction register H2 16 bits containing a predetermined correction OFF. The output of the H2 register is connected via a switch IT8 controlled by the logic signal I2 of switch IT2 and IT3 switch to the input of counter-register T. This H2 correction register is used when the MC control means are in their second state. For this purpose, the set of correction EC also includes a 16-bit register of C configuration connected to the control means and containing the state of the control signal MOD for defining the number of control means state.

p0037The electronic clock device finally comprises an H1 access 16-bit register connected to control means MC and adapted to configure the DH clock device in view of the computer-related information received by the receiving means and computer nature of information transmitted by the transmitting means. This computer-related can be for example the direction of advance information of addresses in a dual-port 16-bit counter register-T or the S registers, D or P.

p0038It Reference is now made to Figure 2 which shows a computer installation comprising a plurality of clock devices, as described in Figure 1, connected by communication means MCOM such as a serial transmission bus. Figure 2 only shows two DH1 and DH2 clock devices with their MR receiving means and their transmission means ME. Each DH clock device is also associated with a host that may comprise several HOT IT equipment. The host is also connected directly to the MCOM media. It is convenient then to separate the MR receiving means and transmission means ME clock device respectively a first part MR1, ME1 reserved for communication with the host and a second part MR2, ME2 reserved for communication with MCOM the communication.

p0039One of the clock devices, here the DH1 clock device, is designated as a master clock device to time and which will resolve all other local times of other devices connected on the clock MCOM the communication.

p0040It is also assumed that the master device comprises DH1 not shown generating means in Figure 2 and adapted to generate on the communication means MCOM IFI1 the information defining the sequence of first moments I1 and that can be referred to under the name mistress of information. The generating means comprises in fact the control means and the means for emitting the DH1 clock device.

p0041The HOT1 host further comprises a SH reference time source of great stability greater than the stability of the local frequency source DH1 device and delivering this local frequency source of a reference time information IHR. This external time source can be for example an atomic clock.

p0042It is now particularly referred to Figures 1A to 1E illustrate the operation of an electronic timepiece apparatus of the invention. To facilitate understanding of this operation we place in the event that the clock device is part of a plant described in Figure 2 it being understood that the general operation described below is applicable to a clock device the invention alone.

p0043Each DH clock device maintains a local time information IHL communicated via transmission means ME1 to the corresponding host. This local information IHL schedule is maintained by division from the local frequency source F and the intermediate member CH SF controlled by a control signal from the control means MC. This CH intermediary body is actually shaping the clock signal emitted by the source F and outputs a clock signal to the counter-T register with a synchronous frequency than the local frequency source F. The organ CH allows intermediate to provide a wide range of maintenance periods of the local time information in the counter-register T. Indeed, CH intermediate member may include a first floor providing a division by a factor of 8, 1026 and a second stage providing a division by 1, 10, 100 or 1000.

p0044The control means are able to deliver an OVF overflow signal from the counter-register T. The operation of this OVF signal depends on the intended application. This can be especially resetting the counter-T register or capacity expansion. The value of this OVF signal is contained in the configuration register C.

p0045It is now referred to 1A and 1B illustrate a correction of the local time information with respect to a reference time IHR information received. 1A to 1E is identical to Figure 1 and is shown on these thick lines illustrating the connections between the various components in the described modes of operation.

p0046The control means MC are supposed to be in their first state characterized by the value "true" MOD signal.

p0047When IFI1 information defining a first time is received by the receiving means MR, MC control means loads the current contents of the register-counter T in the first register S (Figure 1A). The receipt of this information means that IFI1 reference time information will later be received by the receiving means MR. When this reference time information is received in the receiving means MR (Figure 1B) the control means MC-load the counter register with the IHR T reference time information received, plus the difference in the content of the course registre- T counter and the contents of the register S. the contents of the register counter-T after the second load so cortient local time information corrected in relation to the reference time information and taking into account the propagation time between the place of issue of this reference time information and the clock device that receives it.

p0048In this operation, the second moment is receiving the reference time information in the receiving means. However, it is envisaged that this second time is no longer directly that moment of receiving information in reference time receiving means but a moment defined by the validity control signal SCV meaning that the received reference time information is indeed valid. If this reference time information is valid correction of the local time information is performed and, if not, nothing is done.

p0049This first state control means is used when the propagation time between the point of reference of the time information transmission and the clock device that receives this information is not known a priori. By cons, if not, when it is certain a priori this propagation time, the control means MC can take their second state defined by the value "false" MOD signal. In this mode (Figure 1C) upon receipt of information indicating the first IFI1 Currently there are more loading the contents of the register-counter T in the first register S and when the reference time information IHR is received in the receiving means MR ago loading, the second time, in the counter-register T of the reference time information IHR plus the predetermined correction OFF contained in the correction register H2. Of course, again the concept of the second moment may depend on the validity signal SCV.

p0050The control means can then deliver the logic signal of the last OK hour meaning that a time-setting was performed. The value of the OK signal is also stored in the configuration register C.

p0051The thus corrected local time information will then be maintained until the next adjustment announced by Prime next. Generally the first moments are part of a predetermined sequence. Also receiving means they generally receive information defining the first moments after IFI1 and improperly recorded.

p0052The reference time information is derived from the master clock device which is supposed here also decide instants and correction of the local time information of the other clock devices. Also, when a correction procedure of the schedule information, the means for generating master devices generate said master information that is actually present on the communication means MCOM only after some time. When this master information is present on the means of communication it is received simultaneously by all clock devices including the master clock device. This reception time then constitutes said first moment.

p0053On receiving the IFI1 information, the master device control means loads the current contents of the register-counter T in the S register, the contents of this register while S defining IHR reference time information that is by issued following the MCOM communication.

p0054the master clock device was assumed above that emitted himself the master information therefore decided itself to correcting all the local time information. One can also consider a correction request is issued by a clock slave device. In this case the procedure is the same as described above, the slave clock device to contain the generating means of the master information.

p0055It is now made reference to Figure 1D to illustrate a particular mode of operation of the clock devices wherein the sampling means are adapted to store the result of local time information IHLE sampling and outputting outside clock devices IE sampling signal.

p0056At initialization of the clock device, the P register contains the time of the first information local sampling schedule. During operation, the MC control means compares the current contents of the counter-T-register with the contents of register P and when the compared contents are equal (logic signal IS) IE sampling signal is issued outside the clock device and parallel to this issue, the second register P is charged by the current contents of the register increased counter-T content of the register B to define the time of the local time information next sampling . In fact, the register B contains a constant PEC sampling period. Accordingly, the P register is capable of storing a result of local time information sampling regularly spaced in time.

p0057is shown here for the sake of simplicity the emission of a single sampling signal IE. Of course it is possible to consider the issue of two sampling signals on one communication means MCOM, the other to the host. An application of this particular operating mode can be the trigger to predetermined times of a particular equipment of the host.

p0058It is now made reference to Figure 1E illustrating another operating mode of the device according to the invention wherein the dating means are suitable for storing a IHLD dating local time information in response to an ICD dating control signal. When ICD dating control signal is received by the reception means and is transmitted to the control means, they load the contents of the register-counter T in the third register D so as to store the current local time information to build local time information dating. This local time information dating IHLD is then transferred to the transmitting means to an external grant. An application of this particular operating mode can be for example the precise dating of data transmitted by a particular equipment of the host.

p0059When one of the hosts an outdoor time source HS, a high stability, the host clock associated with this device is generally the master of time and in this case, before correcting the local time information other clock devices the time master device corrects its local time information by end reference time information of this external time source. The correction procedure is the same as described above remark was made that the communication between the external time source and master clock device is not made by the MCOM channel, but by a direct bond.

p0060The time correction accuracy obtained by the clock device of the invention depends on the technology used and may vary between a few tens and a few hundreds of microseconds.

p0061The invention may include variants, including the following: - The third register D may optionally be confused with the first register S in the case where it is ensured that there is no conflict of access, and the size of the different registers dependent upon the intended application.

p0062Of course some of the means described above may be omitted in variants where they are not used. The sampling means and / or timing may in particular not be implanted in the case where the corresponding particular operating modes are not used.