Quadrature receiver

p0001The invention relates to a quadrature receiver according to the preamble of claim 1. Such a receiver is known for example from DE-PS 26 45 950th

p0002In the known implementation of a reception signal in which Kophasal- and quadrature components, these components may be distorted due to non-ideal properties mixer.

p0003From "Philips Journal of Research", Vol.41, No.3, 1986 S.219-231, methods are known, especially to compensate for the zero-IF receivers, the distortions occurring due to DC drift at the outputs of the mixer. One of the methods is of opposite sign to superimpose equal DC voltages at the outputs. However, this is difficult because the DC drift changes permanently. In another method, the outputs of the mixers are connected by AC coupling with the subsequent stages. but this is lost the necessary for incoherent demodulation of an amplitude modulated received signal carrier. In a frequency-modulated signal reception signal components are suppressed in the vicinity of the conversion frequency.

p0004The invention has for its object to provide a quadrature receiver having a circuit which compensates by non-ideal properties, in particular the mixer, caused distortions of the quadrature signals.

p0005This object is accomplished by the means mentioned in the main claim. Advantageous further developments are contained in the dependent claims.

p0006The invention is illustrated below with reference to several embodiments. Show it<ul><li>FIG. 1 a first quadrature receiver,</li><li>Fig. 2 shows a part of a second quadrature receiver,</li><li>Fig. 3 shows a part of a quadrature receiver, which operates according to the Weaver method.</li></ul>

p0007The quadrature receiver according to Fig. 1 has three series-connected in a tree structure power divider LT, LT ', Lt, which split a receive signal E in four sub-signals. The power divider LT 'is a first and a third mixer M1, M3 and the power divider LT a second and a fourth mixer connected downstream. The first mixer M1 is followed by a first low-pass filter TP1 and this is a first amplifier V1. Accordingly, the second, third and fourth mixer M2, M3, M4, depending a low pass filter TP2, TP3, TP4 and amplifier V2, V3, V4 downstream. The output of the first amplifier V1 is connected to the first input and the output of the third amplifier V3 to the second input of a first circuit P ', an in-phase signal IP at its output. The output of the second amplifier V2 is connected to the first input and the output of the fourth amplifier V4 to the second input of a second circuit P which a quadrature signal at its output QU. The first and second circuit P ', P are identical.

p0008Each circuit P ', P includes an adder A', two subtractors S1, S2, a switch U and an integrator I '. The adder A 'adds the two input signals of the circuit, the first subtracter S1 is subtracted from the first input given input signal the signal present at the second input. The switch U turn by either the output of the adder A 'or the output of the first subtractor S1 to the integrator I' to the output of which is subtracted by the second subtractor S2 from the first input of the circuit P ', P applied input signal. The output of the second subtracter S2 is the output of the circuit P ', p.

p0009The quadrature receiver further includes an oscillator circuit O, which generates four oscillator signals O1, O2, O3, O4. The first oscillator signal O1 is supplied to the first mixer M1. The second oscillator signal O2 is opposite to the first phase shifted by 90 ° and supplied to the second mixer M2.

p0010The third oscillator signal O3 alternately has the same or opposite phase as the first and the third mixer M3 is supplied. The fourth oscillator signal O4 alternately has the same or opposite phase as the second and the fourth mixer M4 is supplied.

p0011The oscillator circuit includes an oscillator OS O, to which a HA circuit is connected downstream, which divides the signal of the oscillator OS into two by 180 ° from each other phase-shifted signals. The first oscillator signal O1 is directly on an output of the circuit HA tapped, the second oscillator signal O2 is generated from the first phase shift by means of a 90 ° N -Phasendrehgliedes. The oscillator circuit further includes a switch O U at the output of the third oscillator signal O3 occurs by connecting alternately one or the other output of the circuit HA with its output. The fourth oscillator signal O4 is generated from the third through phase rotation by a further 90 ° N -Phasendrehgliedes.

p0012The quadrature receiver also has a clock generator TG, which thus controls the switch U in the oscillator circuit O and the switch U in the circuits P ', P, that this switch synchronously. This switching is preferably carried out with a frequency of several kHz.

p0013The compensation of the DC drift at the outputs of mixers M1-M4 and the additional DC drift, which is caused by the mixers M1-M4 following amplifier V1-V4, with the aid of the circuits P ', P is made possible by the fact that the DC drift of the phase position of the oscillator signals O1-O4 independently, the converted received signal, however, is dependent on it. One thus obtains a change of sign, derived from a received signal component in the mixed product when the phase of the oscillator signals O3, O4 is switched between 0 ° and 180 °.

p0014Denoting the fraction of the DC drift in the (amplified) mixing product of the first (or second) mixer M1 (or M2) with G 'and the fraction of the DC drift in the (reinforced) blend product of the third (or fourth) mixer M3 (or M4) with G ˝, as occurs at the output of the first subtracter S1 in the illustrated in Fig. 1 position of the switch U, U, the size G 'G˝ on who is the integrator I' supplied. After switching occurs at the output of the adder A '+ G˝ that the integrator I' the size of G is supplied. About a switching cycle averaged therefore provides the integrator I 'at its output exactly the size G', which means the second subtractor S2 from the from the first (or second) mixer M1 (or M2) derived signal is subtracted, the by G of its DC drift 'is freed.

p0015Fig. 2 shows a part of a second quadrature receiver which differs from that of FIG. 1 in that it takes the circuits P ', P digital circuits D', D with controllers and instead of the clock generator TG clock control TS having. For reasons of clarity has been omitted in the presentation of the remaining part of the second quadrature receiver comprising the digital circuit with the first D 'identical, second digital circuit D.

p0016The digital circuit D 'has on each input a subtractor S' on, S˝, which a sample and hold element AH 'ah downstream. The switch U turn by either the output of one or the other sample-hold element AH 'ah an A / D converter AD to which an arithmetic unit RR and this two D / A converter DA downstream. Each D / A converter DA, a respective low-pass filter TP ', TP downstream, the output signals of the inverting inputs of subtracter S' are supplied, P. At the output of the first input downstream subtractor S 'is the output of the circuit D' can be tapped.

p0017As is apparent from the above description and from FIG. 2, includes the digital circuit D ', two control circuits. The control variables are the direct current drift G 'and G werden- calculated by the arithmetic unit RR and be controlled by a respective contained in the arithmetic unit RR is set to zero. The outputs of the controllers are connected to the D / A converters DA. The necessary arrangements for the reference variables are generated in the arithmetic unit RR. Regulators have PI action; because of the slow temporal change of the controlled variables is a D-behavior of the controller is not required.

p0018The timing TS not only controls the switch U in the oscillator circuit and the switch U in the digital circuits D ', D˝ but also the sample-hold circuits AH' ah and the arithmetic unit RR. A timing diagram is also shown in Fig. 2.

p0019By the sample-and-hold devices AH ', AH the input voltages are at the instants t₁, t₂, ... sampled and latched until the next sampling instant. By continuously switching the changeover switch U these samples are supplied to the arithmetic unit RR to analog / digital conversion. In timing diagram illustrates the case that read every time you switch any two samples into the arithmetic unit RR and averaged there.

p0020Compared to the circuits P D˝ ', p of the first embodiment shown in FIG. 1, containing no control, are at the digital circuits D' compensated by the regulator also linearity error of circuits and deviations in the gain from the ideal value 1 , The settling time of the control loops is 'both mixers smaller than if only a control circuit for compensating the DC drift G, G' is present in compensating the DC drift G. Other designs of the circuits P ', P with such a control loop additionally contain a the integrator I' downstream regulator, with the adder A 'and the first subtractor, the output signal of the second subtracter S2 is supplied in place of the first input signal applied S1.

p0021Fig. 3 shows a part of a third quadrature receiver, which operates according to the Weaver method and differs from that of FIG. 1 by the circuits W ', W, and as shown in FIG. 2 for reasons of clarity to the representation of the rest of the circuit W is dispensed with, which is the circuit W 'identical. In addition to the oscillator circuit, the third O quadrature receiver on an identical with this additional oscillator circuit, of which only a portion is also shown, and generates the four auxiliary signals H1-H4. The clock generator TG controls the switch U, U 'in the oscillator circuits such that they switch simultaneously, but in opposite phase.

p0022The circuit W 'has at its first input to a subtractor S and at its second input a further mixer M˝. The subtractor S is another mixer M 'whose output signal is the output signal of the circuit W'. The output signals of mixer M ', M are an adder A supplied by an amplifier V and that an additional mixer M are connected downstream. Said additional mixer M and the other mixer M 'is the first auxiliary signal H1 and the further mixer M. supplied to the third auxiliary signal H3, which alternately has the same or opposite phase comprising as the first. Said additional mixer M is an integrator I and a controller that R whose output signal is supplied to the inverting input of the subtractor S.