Multi-bus microcomputer system with bus arbitration.

0001The present invention relates to bus arbitration in a multi-bus microcomputer.

0002Background information respecting the 80386 microprocessor, its characteristics and its use in microcomputer systems including cache memory subsystems are described in Intel Corporation's publications "Introduction to the 80386", April 1986 and the 80386 Hardware Reference Manual (1986). The characteristics and operating performance of the 82385 cache controller are described in the Intel Corporation's publication "82385 High Performance 32-Bit Cache Controller" (1987).

0003Microcomputer systems including a cache subsystem are, architecturally, significantly different from microcomputer systems without cache subsystems. Microcomputer systems with a cache subsystem operate as dual bus devices. More particularly, in microcomputer systems with a cache subsystem, there is a first bus (referred to as the CPU local bus) which interconnects the CPU, cache memory and cache control. Other devices are coupled to a different bus (system bus). Such other devices include, for example, main memory, I/O devices and ancillary apparatus. In addition to the foregoing devices, the system bus may also be coupled to the cache control.

0004The cache subsystem typically relieves the system bus from a large proportion of memory accesses that would otherwise be carried by the system bus in the absence of the cache subsystem. That is, to the extent that the CPU can obtain information from the cache memory, then for that particular cycle the CPU does not require access to the system bus. Accordingly, other devices can, during the same period of time, use the system bus for other operations. This is expected to result in a significant reduction of the system bus cycles which are actually used by the CPU. Usually the cache control is coupled to both the system bus and the CPU local bus, and one of the functions of the cache control is to supervise the arbitration supervisor which, in the single bus systems, had been supervised by the CPU.

0005One available cache controller, the 82385, has the capability of operating in a master or a slave mode. When the 82385 is operated in the master mode, and supervises the arbitration supervisor, there is no longer any mechanism for the CPU to contend for the system bus resource.

0006Accordingly, it is an object of this invention to provide a mechanism whereby a CPU, in a multi-bus microcomputer system with a cache control element supervising the arbitration supervisor, may access the system bus resource distributed by the arbitration mechanism.

0007The arbitration supervisor responds to arbitration request signals which are coupled in common from a plurality of devices. When the arbitration supervisor recognizes that one or more devices has requested the common resource, it signals the beginning of an arbitration period by changing the condition of a conductor (the ARB/GRANT) which is accessible to all the contending devices. When the contending devices see the condition of this conductor changed so as to signal the beginning of an arbitration period, the devices generate signals corresponding to their priority levels and drive a plurality of arbitration conductors dedicated to this function with those signals. The connection between the plurality of devices and the arbitration conductors is arranged such that the conductors assume that priority value of the highest priority circuit driving the arbitration conductors. Each device can therefore recognize, by comparing the priority value on the arbitration conductors with its own priority value, whether there is any higher priority device contending for access to the bus. At the termination of a predetermined arbitration period, the ARB/GRANT/ conductor changes state. This begins the grant period, during which that contending device whose priority value was the priority value on the arbitration conductors assumes control of the common resource to initiate a bus cycle.

0008Furthermore there is still another conductor dedicated to a PREEMPT signal which can be generated to force a device having received access to the system resource, to terminate its access. Thus, a device which has received access to the system resource and is using that resource, on recognizing an asserted preempt, is required to initiate an orderly termination of its use of the system resource. When the device which is thus preempted terminates it use of the common resource, the arbitration supervisor begins a new arbitration period as described above.

0009In microcomputer systems with a cache subsystem, the CPU cycles accessing cache (and thus not requiring access to the system bus) are cycles of minimum duration or zero wait state cycles. When CPU cycles extend beyond this minimum, they signal CPU requirements for the system bus. Thus CPU cycles of longer than the minimum duration signal CPU need for the system bus, the common resource.

0010In accordance with the invention, the CPU is provided with the means to generate a PREEMPT signal which will cause any device having gained access to the bus through the arbitration mechanism to terminate that access as has already been described. As will be described, the CPU's generation of PREEMPT is controlled by detecting a CPU cycle of duration longer than one required for a cache address.

0011However, the CPU's use of the system resource is arranged to conserve as much time as possible. More particularly, when a device which had gained access to the bus via an arbitration recognizes a preempt and initiates an orderly termination of its bus access, it signals its termination of the use of the bus. The arbitration supervisor responds to this indication by generating a new arbitration period. If the CPU was the device which had generated the preempt to require release of the bus, it will respond differently to the beginning of the arbitration period than will any other device contending for bus access. At the beginning of the arbitration period, each of the other devices contending for access to the bus places its priority value on the arbitration conductors. The CPU does not enter into this process at all; with the beginning of the arbitration period, the CPU actually begins using the bus.

0012In an embodiment of the invention which has actually been constructed, the minimum arbitration period is 300 nanoseconds. However a zero wait state bus cycle is less than 300 nanoseconds. Accordingly, whenever the CPU preempts and thereby gains access to the system bus, it can actually complete a cycle simultaneous with the arbitration process.

0013According to the invention, there is provided a multi-bus microcomputer system comprising a processor and a cache subsystem connected together by a CPU local bus, a random access memory, an arbitration supervisor and a plurality of other functional units connected together by a system bus, means coupling said CPU local bus and said system bus, both said CPU local bus and said system bus including a plurality of conductors dedicated to arbitrating access to said system bus by at least some of said plurality of other functional units, one of said plurality of said conductors providing a preempt signal, and a preempt signal source with inputs responsive to a CPU local bus cycle extending beyond a minimum duration, said preempt signal source having an output coupled to said CPU local bus for asserting a preempt signal effective at any functional unit with access to said system bus for limiting a duration of said access in response to receipt of said preempt signal. An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: <ul id="ul0001" list-style="none"><li>Fig. 1 is an overall view of a typical microcomputer system which may employ the present invention;</li><li>Fig. 2 is a detailed block diagram of a majority of the components of a typical microcomputer system which may employ the present invention;</li><li>Fig. 3 illustrates how the arbitration supervisor and CPU are connected in accordance with a single bus microcomputer system;</li><li>Fig. 4 illustrates how the arbitration supervisor, CPU and cache control are interconnected in accordance with the present invention;</li><li>Fig. 5 illustrates the apparatus associated with the CPU to generate a PREEMPT signal;</li><li>Fig. 6 illustrates the logic associated with the CPU for generating a signal CPUREQ which is used in generation of a PREEMPT signal by the CPU;</li><li>Fig. 7 is a timing diagram illustrating several arbitration and grant cycles, one of which provides access to the system bus by a generic device and another of which provides access to the system bus to the CPU via a PREEMPT signal;</li><li>Fig. 8 shows the relationship between the central arbitration supervisor 335 and arbitors 336 associated with other devices;</li><li>Figs. 9 and 10 taken together are a block diagram of an arbitration supervisor 335; and</li><li>Fig. 11 is a timing diagram for explaining the operation of Fig. 8.</li></ul>

0014Fig. 1 shows a typical microcomputer system in which the present invention can be employed. As shown, the microcomputer system 10 comprises a number of components which are interconnected together. More particularly, a system unit 30 is coupled to and drives a monitor 20 (such as a conventional video display). The system unit 30 is also coupled to input devices such as a keyboard 40 and a mouse 50. An output device such as a printer 60 can also be connected to the system unit 30. Finally, the system unit 30 may include one or more disk drives, such as the disk drive 70. As will be described below, the system unit 30 responds to input devices such as the keyboard 40 and the mouse 50, and input/output devices such as the disk drive 70 for providing signals to drive output devices such as the monitor 20 and the printer 60. Of course, those skilled in the art are aware that other and conventional components can also be connected to the system unit 30 for interaction therewith. In accordance with the present invention, the microcomputer system 10 includes (as will be more particularly described below) a cache memory subsystem such that there is a CPU local bus interconnecting a processor, a cache control and a cache memory which itself is coupled via a buffer to a system bus. The system bus is interconnected to and interacts with the I/O devices such as the keyboard 40, mouse 50, disk drive 70, monitor 20 and printer 60. Furthermore, in accordance with the present invention, the system unit 30 may also include a third bus comprising a Micro Channel (TM) architecture for interconnection between the system bus and other input/output devices.

0015Fig. 2 is a high level block diagram illustrating the various components of a dual bus microcomputer system. A CPU local bus 230 (comprising data, address and control components) provides for the connection of a microprocessor 225 (such as an 80386), a cache control 260 (which may include an 82385 cache controller) and a random access cache memory 255. Also coupled on the CPU local bus 230 is a buffer 240. The buffer 240 is itself connected to the system bus 250, also comprising address, data and control components. The system bus 250 extends between the buffer 240 and a further buffer 253.

0016The system bus 250 is also connected to a bus control and timing element 265 and a DMA controller 325. An arbitration control bus 340 couples the bus control and timing element 265 and arbitration supervisor 335. The main memory is also connected to the system bus 250. The main memory includes a memory control element 351, an address multiplexer 352 and a data buffer 353. These elements are interconnected with memory elements 360 through 364, as shown in Fig. 2.

0017A further buffer 267 is coupled between the system bus 250 and a planar bus 270. The planar bus 270 includes address data and control components, respectively. Coupled along the planar bus 270 are a variety of I/O adaptors and other components such as the display adaptor 275 (which is used to drive the monitor 20), a clock 280, additional random access memory 285, an RS 232 adaptor 290 (used for serial I/O operations), a printer adaptor 295 (which can be used to drive the printer 60), a timer 300, a diskette adaptor 305 (which cooperates with the disk drive 70), an interrupt controller 310 and read only memory 315. The buffer 253 provides an interface between system bus 250 and an optional feature bus such as the Micro-Channel (TM) bus 320 represented by the Micro-Channel (TM) sockets. Devices such as memory 331 may be coupled to the bus 320.

0018Figs. 8-11 are useful in explaining the arbitration mechanism. Referring now to Fig. 8, the relationship between the arbitration supervisor 335 and a local arbiter unit 336, representative of all local arbiter units, will be described. In general, when a device wants access to the system bus 250 to transfer data, a local arbiter unit 336 will receive a request signal from the particular device to which the arbiter unit is related. The request signal is converted to a /PREEMPT signal which is generated by the local arbiter and transmitted to the arbitration supervisor 335 and each of the local arbiters over the /PREEMPT line of the arbitration bus. It should be noted in the specific embodiment of this invention that the /PREEMPT lines are OR'ed together and thus it is irrelevant to the arbitration supervisor 335 which particular device generates the request. The arbitration supervisor 335 generates the ARB/GRANT/ signal at an appropriate time as determined by the HLDA and +REFRESH memory signal from a refresh controller (not shown) well known to those skilled in the art, in response to a /PREEMPT signal from one or more of the local arbiters 336. HLDA is one signal of the pair HLDA and HRQ (or HOLD) which in a single bus system was exchanged between the arbitration supervisor 335 and the CPU. In dual bus systems these signals are between the arbitration supervisor and the cache controller, shown at 260 in Figure 2.

0019Thus when any one of the devices desires to contend for use of the system bus 250, it generates a request signal to its corresponding local arbiter 336 which then generates a /PREEMPT signal over the /PREEMPT line of the arbitration bus. Then at the appropriate time when the bus becomes available, as determined by the HOLD and the +REFRESH signal from the refresh controller, the arbitration supervisor 336 generates the +ARB state of the ARB/GRANT/ signal over the arbitration bus to each one of the local arbiters 336. In response to the +ARB state, each of the local arbiters 336 which desires access to the system bus 250 drives its priority level onto respective lines ARB0-ARB3 of the arbitration bus. Then each of the local arbiters desiring access to the system bus 250 compares its designated priority level with the priority level on the arbitration bus and takes itself out of contention for the bus in the event its priority level is lower than that being driven onto the arbitration bus. Thus at the end of the arbitration cycle, only that one of the local arbiters having the highest priority level during that arbitration cycle remains in contention for the bus and thus gains control of the bus when the GRANT/ state is received from the arbitration supervisor 336 over the ARB/GRANT/ line.

0020Referring now to Figs. 9 and 10, a more detailed circuit description of the arbitration supervisor 336 is illustrated. The arbitration supervisor 336 comprises a modified Johnson ring timing chain including counters 31 to 34 and OR gate 35, OR gate 36, NAND gate 37, inverter 38 and OR gate 39. Assuming the bus begins in an idle condition with the CPU 225 "owning" the bus, but not using it, the circuit operation will be described hereinafter in conjunction with the timing chart of Fig. 11. In the aforesaid condition, ARB/GRANT/ is then active low, and the arbitration priority levels ARB0 to ARB3 all have a value of one. The modified Johnson ring timing chain is held reset by the +HLDA signal through the OR gate 36 and the NAND gate 37. When a device needs access to the bus, the /PREEMPT signal is activated. As shown in Fig. 10, the /PREEMPT signal going active results in the output of the gate going positive, representing a PROCESSOR HOLD REQUEST (+PROC HRQ) signal. The +ARB0 through +ARB3 signal and a +GRANT signal are also input to the OR gate of Fig. 10 to insure that the CPU 225 will not interfere with bus transfers by other devices. The +PROC HRQ signal results in deactivating +HLDA which results in the reset signal (output from OR gate 36) being removed from counters 30 to 33. It should be understood that inputs -S0, -S1, -CMD and -BURST must be inactive in order for +HLDA to remove the reset signals from the aforesaid counters 31 to 34, as illustrated in Fig. 11. The -S0 signal represents the WRITE cycle, and the -S1 signal represents the READ cycle. The -CMD signal is generated by the current bus master a specified time period after -S0 or -S1. During READ cycles the -CMD instructs the slave device to place READ data onto the bus and during WRITE cycles -CMD is activated for validation of WRITE data.

0021On the next (20 MHz) clock pulse, after +HLDA is deactivated, the counter 31 output is set causing the output of OR gate 39 to go high (+ARB) indicating an arbitration timing period. The OR gate 39 output remains high until the output of counter 33 goes low sometime after the output of counter 34 has gone high. This establishes a 300 nanosecond timing pulse for the ARB/GRANT/ signal. The output from counter 34 remains set until the device begins a bus cycle by either activating -S0 or -S1. The output is then reset, and the counters 31 through 34 are ready to begin timing again at the end of the current bus cycle. If no devices are requesting bus service, the bus returns to the idle condition and control is returned to the processor. HLDA is reactivated and the bus is now available for processor operations.

0022Fig. 3 shows the interconnection between an 80386 CPU, such as the microprocessor 225, and the arbitration supervisor 335 in a single bus microcomputer system. The output signal ARB/GRANT/ from the supervisor is the signal defining whether the arbitration mechanism is in the arbitration state (during which devices contending for access to the system resource place their priority level on the arbitration conductors) or in a grant phase (wherein the device obtaining access to the common resource can employ that resource to the exclusion of other devices which may have been contending for access). Another input signal to the arbitration supervisor 335 is the PREEMPT signal which has already been described. Finally, the input to the 335 arbitration supervisor represented by ARB[0-3] is the arbitration conductors which, during the arbitration phase, are driven by devices contending for access with their own priority levels. The input/output connections on the left side of the arbitration supervisor 335 show its interconnection with the 80386, in a typical single bus microcomputer system. The signals HLDA and HRQ (sometimes referred to as HOLD) are handshaking mechanisms whereby the arbitration supervisor 335 can request access to the system resource to the exclusion of the 80386 (HRQ). When the 80386 acknowledges (HLDA) then the arbitration supervisor 335 can distribute access to the resource. In single bus microcomputer systems, the CPU cannot preempt on its own behalf. This raises the undesirable potential for the CPU to be locked out of the common resource by an device which is allowed to burst.

0023Fig. 4 is a block diagram showing selected interconnections in a dual bus microcomputer system which employs the 80386 CPU and an 82385 cache controller. The input/output connections on the right side of the arbitration supervisor 335 of Fig. 4 are identical to those in Fig. 3 and will not be described again. The important point illustrated in Fig. 4 is that the supervision of the arbitration supervisor 335 is now implemented by the 82385 cache controller, since it is that element to which the HRQ and HLDA signals are connected. Absent some other arrangement, then, the 80386 CPU could be frozen out of use of the common resource. The present invention provides that other mechanism and does so, to a large extent, without impacting other devices accessed to the common resource.

0024Figs. 5 and 6, taken together, illustrate how the signal CPREEMPT, and its antecedent CPUREQ, are generated.

0025Referring first to Fig. 6, the logic there can be considered part of the cache control 260. The logic is provided to generate the signal CPUREQ which can be considered a control signal input to the control portion of the buffer 240. The control signal CPUREQ is developed from the inputs shown at the left including /BUSYCYC 386, READYI, CLK, RESET and /(/M/IO &amp; A31). The latter signal is the decoded address to the coprocessor. The signals BUSYCYC 386, READYI and /(/M/IO &amp; A31) are active low signals such that for example when the flip-flop 601 becomes set (through a high input at its D input), its output is high and the CPUREQ signal is low (active). In addition to the flip-flop 601, the logic of Fig. 6 includes an OR gate 602, three AND gates 603-605 and inverters 606-608.

0026Essentially the inputs to AND gate 603 detect an 80386 cycle which extends beyond the zero wait state and which is not at the same time a cycle dedicated to the coprocessor. Once the condition is detected, the flip-flop 601 becomes set, and can only be reset at a clock time CLK2 when the condition has terminated. Gates 604 and 605 are provided to reset flip-flop 601 when CLK is high and READYI is (active) low. This condition occurs when a CPU bus cycle is completed.

0027A CPU local bus cycle extending beyond the zero wait state (and which is also not a coprocessor dedicated cycle) is a cycle which requires access to the system bus. Accordingly the CPUREQ under those circumstances becomes active, that is, goes low. The effect of this signal is shown in Fig. 5.

0028Fig. 5 shows logic which is associated with the system bus 250. As shown in Fig. 5 the control element of the buffer 240 has an output CPUREQ (which is driven by the same signal shown in Fig. 6). The CPUREQ is one input to a gate 501 whose output /CPREEMPT is, in effect, a preempt signal generated by the 80386. As see in Fig. 5 the signal /CPREEMPT is coupled to the PREEMPT conductor which is one of the inputs to the arbitration supervisor 335 (see Fig. 3 or 4). The signal /CPREEMPT is generated by the logic shown in Fig. 5 including the gates 501- 503. A second input to the gate 501 is the output of gate 503, one of whose inputs is the ARB/GRANT/ signal (identical to the output of the arbitration supervisor 335). The other input is ENCPUPREEMPT. The latter is an output of the 80386. When inactive, this signal will inhibit /CPREEMPT from ever becoming active. Thus when ENCPUPREEMPT is inactive, the 80386 cannot preempt. ENCPUPREEMPT may be controlled by a user-settable switch or a software switch, depending on the requirements of other system devices and/or software. Under normal circumstances, ENCPUPREEMPT will be active, thus enabling the 80386 to preempt. When the ARB/GRANT/ indicates the arbitration process is in the grant phase (and ENCPUPREEMPT is active) then the output of gate 503 will be active. An active output of the gate 503 along with an active CPUREQ will enable production of an active /CPREEMPT. The gate 503 will prevent generation of an active /CPREEMPT during the arbitration phase, and only allow an active /CPREEMPT during the grant phase of the arbitration process. The gate 502 is used to monitor the state of the arbitration conductors and will prevent generation of an active /CPREEMPT if all conductors are (active) high, indicating that other devices are not arbitrating for the bus, i.e. the CPU owns the common resource.

0029Accordingly, by the logic shown in Figs. 5 and 6, for cycles on the CPU local bus which are not dedicated to the coprocessor, and which extend beyond a minimum duration (zero wait state), the CPU may preempt, and will preempt, if the arbitration mechanism is in its grant phase. The effect of this preemption will now be described in connection with Figs. 7A-7E.

0030Figs. 7A-7E illustrate: <ul id="ul0002" list-style="none"><li>1) use of the system bus by a burst device (a-d),</li><li>2) preemption of that device by a typical device through use of the PREEMPT signal (b-h)</li><li>3) acquisition of the bus by the CPU via use of the /CPREEMPT signal (k-o), and </li><li>4) simultaneous with use of the bus by the CPU, arbitration for use of the bus by another device (m).</li></ul>

0031More particularly, for purpose of illustration assume that a Burst mode device has gained control of the system bus as illustrated (a) in Fig. 7D. When another device along the system bus asserts PREEMPT (b), the Burst device presently in control completes its current transfer as illustrated (c) - Fig. 7C. On completion of the current transfer, the Burst device that is relinquishing control of the system bus removes its Burst signal from the Burst line as shown at (d) - Fig. 7D. This Burst device will not participate in the next arbitration cycle. The arbitration supervisor 335 then places the ARB/GRANT/ into the ARB state (e) - Fig. 7A. The same transition represents the beginning of another arbitration cycle and arbitration for the system bus begins at (f) - Fig. 7B. After the ARB/GRANT/ signal goes low, control of the system bus is granted to the new device as illustrated at (g) - Fig. 7A. The new device which has gained control of the system bus then removes its PREEMPT signal in response to the GRANT signal as shown at (h) - Fig. 7E.

0032Sometime later, in the example of Figs. 7A-7E and based on conditions reflected on the CPU local bus 230, the CPU asserts /CPREEMPT which is reflected in PREEMPT (k) - Fig. 7E. As has already been explained, this will result in a new arbitration cycle beginning as illustrated (l) - Fig. 7A. The arbitration cycle, as shown in Fig. 7A, extends from (l-o). During this arbitration cycle, the CPU actually employs the system bus, and at the beginning of that cycle the CPU de-asserts its PREEMPT signal (n) - Fig. 7E. During the CPU's use of the system bus, other devices which may contend for access to the system bus arbitrate for that resource beginning at (m) - Fig. 7B. At the end of the CPU cycle, when it has completed use of the system bus (o), a new arbitration has been completed so that immediately thereafter some further device (if any were contending for access to the system bus) can employ that resource in the duration beginning at (o) - Fig. 7A.

0033The /CPREEMPT signal is only active when a CPU bus cycle extends beyond a predetermined duration (beyond a zero wait state, for example). During the arbitration phase (ARB/GRANT/ high), the CPU cache control 260 is released from the hold state by the supervisor 335 dropping HRQ and is allowed to run one or more cycles.

0034The completion of a CPU cycle, allowed to use the system bus by use of the preempt mechanism, is detected by READYI active with CLK high. By virtue of the logic of Fig. 6, under these conditions the flip-flop 601 is reset and CPUREQ goes inactive.

0035The logic equations which have been referenced above are reproduced immediately below. In this material the symbols have the following meanings associated with them: <tables id="tabl0001" num="0001"><table frame="all"><tgroup cols="2" colsep="1" rowsep="0"><colspec colnum="1" colname="col1" colwidth="78.75mm" /><colspec colnum="2" colname="col2" colwidth="78.75mm" /><thead valign="top"><row rowsep="1"><entry namest="col1" nameend="col1" align="center">Symbol</entry><entry namest="col2" nameend="col2" align="center">Definition</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="right">/</entry><entry namest="col2" nameend="col2" align="left">Negation</entry></row><row><entry namest="col1" nameend="col1" align="right">:=</entry><entry namest="col2" nameend="col2" align="left">A registered term, equal to</entry></row><row><entry namest="col1" nameend="col1" align="right">=</entry><entry namest="col2" nameend="col2" align="left">A combinatorial term, equal to</entry></row><row><entry namest="col1" nameend="col1" align="right">&amp;</entry><entry namest="col2" nameend="col2" align="left">Logical AND</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="right">+</entry><entry namest="col2" nameend="col2" align="left">Logical OR</entry></row></tbody></tgroup></table></tables><tables id="tabl0002" num="0002"><table frame="all"><tgroup cols="2" colsep="1" rowsep="0"><colspec colnum="1" colname="col1" colwidth="78.75mm" /><colspec colnum="2" colname="col2" colwidth="78.75mm" /><thead valign="top"><row><entry namest="col1" nameend="col2" align="center"><u style="single">Logic Signals</u></entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">ARB[0-3]</entry><entry namest="col2" nameend="col2" align="left">Arbitration Requests</entry></row><row><entry namest="col1" nameend="col1" align="left">ARB/GRANT</entry><entry namest="col2" nameend="col2" align="left">Arbitration Grant</entry></row><row><entry namest="col1" nameend="col1" align="left">/(/M/IO &amp; A31)</entry><entry namest="col2" nameend="col2" align="left">Decoded math coprocessor address</entry></row><row><entry namest="col1" nameend="col1" align="left">/CPREEMPT</entry><entry namest="col2" nameend="col2" align="left">See Fig. 5</entry></row><row><entry namest="col1" nameend="col1" align="left">/CPUREQ</entry><entry namest="col2" nameend="col2" align="left">See Fig. 6</entry></row><row><entry namest="col1" nameend="col1" align="left">ENCPUPREEMPT</entry><entry namest="col2" nameend="col2" align="left">Programmable bit to enable or disable ability of the CPU to generate /CPREEMPT</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">PREEMPT</entry><entry namest="col2" nameend="col2" align="left">Defined in the copending applications, modified in this application to the extent it may be generated by /CPREEMPT</entry></row></tbody></tgroup></table></tables>

Logic Equations

0036/BREADY385=/BUSCYC385 &amp; /BREADY &amp; MISS1      (1) /BT2:=BUSCYC385 &amp; PIPECYC385 &amp; /BADS &amp; CLK &amp; BT2 + BUSCYC385 &amp; /PIPECYC385 &amp; BADS &amp; CLK &amp; NACACHE &amp; BT2 + MISS1 &amp; /BUSCYC385 &amp; /BADS &amp; /(BW/R) &amp; CLK &amp; NCA &amp; /BREADY + /MISS1 &amp; /BREADY &amp; /BUSCYC385 &amp; CLK + /BT2 &amp; BREADY &amp; NACACHE + /CLK &amp; /BT2      (2) /BUFWREND:=WBS &amp; /BUSCYC385 &amp; /BREADY &amp; CLK      (3) /BUSCYC385:=BUSCYC385 &amp; /BADS &amp; CLK + BUSCYC385 &amp; /PIPECYC385 &amp; CLK + BUSCYC385 &amp; /BT2 &amp; CLK + /BUSCYC385 &amp; BREADY + /BUSCYC385 &amp; /CLK      (4) /BUSCYC386:=BUSCYC386 &amp; /ADS &amp; CLK &amp; /RESET + BUSCYC386 &amp; /PIPECYC386 &amp; CLK &amp; /RESET + /BUSCYC386 &amp; CPUREADY &amp; /RESET + /BUSCYC386 &amp; /CLK &amp; /RESET      (5) /CPUNA:=/MISS1 &amp; CLK &amp; CPUNA &amp; /NACACHE + /MISS1 &amp; CLK &amp; CPUNA &amp; /BREADY &amp; /BUSCYC385 + /CPUNA &amp; /CLK + /CPUNA &amp; /MISS1 &amp; CLK + /CPUNA &amp; CLK &amp; BREADY + /CPUNA &amp; BUSCYC385 &amp; NACACHE &amp; CLK      (6) LEAB:=/LEAB &amp; /BUSCYC386 &amp; /CPUREADY &amp; (W/R) &amp; CLK &amp; ADS + LEAB &amp; BUFWREND &amp; /CLK + LEAB &amp; WBS &amp; CLK      (7) /MISS1:=MISS1 &amp; BUSCYC385 &amp; CPUNA &amp; /BADS &amp; /(BW/R) &amp; CLK &amp; NCA + MISS1 &amp; BUSCYC385 &amp; /BADS &amp; /(BW/R) &amp; CLK &amp; NCA &amp; /BREADY + /MISS1 &amp; /CLK + /MISS1 &amp; BREADY      (8) /PIPECYC385:=PIPECYC385 &amp; /BADS &amp; /BUSCYC385 &amp; CLK &amp; /BREADY + PIPECYC385 &amp; /MISS1 &amp; BT2 &amp; /BUSCYC385 &amp; CLK &amp; /BREADY + /PIPECYC385 &amp; /CLK      (9) /PIPECYC386:= PIPECYC386 &amp; /ADS &amp; CLK &amp; /CPUREADY &amp; /RESET &amp; /BUSCYC386 + /PIPECYC386 &amp; /CLK &amp; /RESET      (10) /CPUREADY=/READYO &amp; /(W/R) + /BRDYEN &amp; /BREADY &amp; MISS1 &amp; /BUSCYC385 + /READYO387 + /BREADY385 &amp; (W/R) &amp; /LEAB + /READYO &amp; (W/R) &amp; NCA + /RDY387PAL      (11)

0037In the foregoing logic equations the following signals are described or referred to in the cited Intel publications: <tables id="tabl0003" num="0003"><table frame="all"><tgroup cols="2" colsep="1" rowsep="0"><colspec colnum="1" colname="col1" colwidth="78.75mm" /><colspec colnum="2" colname="col2" colwidth="78.75mm" /><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">ADS</entry><entry namest="col2" nameend="col2" /></row><row><entry namest="col1" nameend="col1" align="left">BADS</entry><entry namest="col2" nameend="col2" /></row><row><entry namest="col1" nameend="col1" align="left">BRDYEN</entry><entry namest="col2" nameend="col2" /></row><row><entry namest="col1" nameend="col1" align="left">BREADY</entry><entry namest="col2" nameend="col2" /></row><row><entry namest="col1" nameend="col1" align="left">(BW/R)</entry><entry namest="col2" nameend="col2" align="left">actually referred to as BW/R, the parenthesis are used to indicate that the entire term is one signal</entry></row><row><entry namest="col1" nameend="col1" align="left">CLK</entry><entry namest="col2" nameend="col2" /></row><row><entry namest="col1" nameend="col1" align="left">READYO</entry><entry namest="col2" nameend="col2" /></row><row><entry namest="col1" nameend="col1" align="left">RESET</entry><entry namest="col2" nameend="col2" /></row><row><entry namest="col1" nameend="col1" align="left">WBS</entry><entry namest="col2" nameend="col2" /></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">(W/R)</entry><entry namest="col2" nameend="col2" align="left">actually referred to as W/R, the parenthesis are used to indicate the entire term is a single signal</entry></row></tbody></tgroup></table></tables>

0038ADS, when active indicates a valid address on the CPU local bus 230. BADS, when active indicates a valid address on the system bus 250. BRDYEN is an output of the 82385 which is a antecedent of the READY signals. BREADY is a ready signal from the system bus 250 to the CPU local bus 230. BW/R defines a system bus 250 Write or Read. CLK is a processor clocking signal which is in phase with the processor 225. READYO is another output of the 82385 in the line of ready signals. RESET should be apparent. WBS indicates the condition of the Write Buffer. (W/R) is the conventional Write or Read signal for the CPU local bus 230.

0039Equations (1)-(11) define: BREADY385 BT2 BUFWREND BUSCYC385 BUSCYC386 CPUNA LEAB MISS1 PIPECYC385 PIPECYC386 CPUREADY in terms of the defined signals, the signals described or referred to in the cited Intel publications and NCA, NACACHE, READYO387 and RDY387PAL.

0040BREADY385 is a signal like BREADY which in an embodiment actually constructed was modified to accommodate a 64K cache. In the case of a 32K cache (as recommended by the manufacturer) BREADY can be used in lieu of BREADY385.

0041BT2 reflects the state of the system bus 250. The state BT2 is a state defined in the cited Intel publications.

0042BUFWREND represents the end of a buffered write cycle.

0043BUSCYC385 also reflects the state of the system bus 250. It is high for bus states BTI, BT1, BT1P and low for bus states BT2, BT2P and BT2I (again these are bus states referenced in the cited Intel publications).

0044BUSCYC386 is high during CPU local bus 230 states TI, T1, T1P, T2I and low during T2. It is also low for T2P unless T2I occurs first.

0045CPUNA is a signal to the 80386 allowing pipelined operation.

0046LEAB is the latch enable (into buffer 240) for posted writes.

0047MISS1 is active defining the first cycle in a double cycle for handling 64 bit reads to cacheable devices.

0048PIPECYC385 is active during BT1P (which is a bus state referred to in the cited Intel publications.

0049PIPECYC386 is low during state T1P of the CPU local bus 230.

0050CPUREADY is the ready input to the 80386.

0051NCA is a signal created by decoding the address component on the CPU local bus 230 to reflect, when active, a non-cacheable access. Cacheability is determined by a tag component (A31 to A17) and programmable information defining what tags (if any) refer to cacheable as opposed to non-cacheable addresses.

0052NACACHE is a signal similar to the BNA signal. BNA is a system generated signal requesting a next address from the CPU local bus 230, and is referenced in the cited Intel publications. NACACHE differs from BNA only in respect of the fact that BNA is created for 32K cache while NACACHE is created for a 64K cache. So long as the cache memory is 32K, as cited in the Intel publications the NACACHE signal referred to here could be replaced by the BNA signal.

0053READYO387 is the ready output of the 80387 math coprocessor.

0054RDY387PAL is an output of external logic used in the event a 80387 math coprocessor is not installed to prevent the absence of the math coprocessor from interfering in system operations.

0055Thus it should be apparent that by use of the invention, in dual bus microcomputer system employing an 80386 processor and 82385 cache controller, the processor is conditionally allowed to preempt for use of the system bus under specified circumstances. More particularly, for local bus cycles extending beyond a predetermined duration, the processor can assert /CPREEMPT on the condition that there are other users contending for access to the resource and the preempt option has been enabled (ENCPUPREEMPT). However, when the preempt becomes effective (as signalled to the processor by the arbitration supervisor), then two events occur simultaneously. The first event is that the processor accesses the system bus. This access will not interfere with any other potential bus users since during the period of the processor's access, other contending users are in an arbitration phase. Thus simultaneous with the access to the system bus by the processor, other users may arbitrate for access to the grant phase following the processor's use of the bus. Accordingly, by use of the invention, the processor is enabled to use the system bus even if other user devices are contending, simultaneously, for access to the bus. By overlapping the processor's use of the bus with the arbitration phase (entered into by other devices), bus utilization and efficiency are increased.