Multi-processing system and cache apparatus for use in the same

A main memory (5) is subdivided into a shared region (60, 63) to undergo a write access from a plu­rality of processors (1, 2) and an input/output device (6) and a plurality of private regions (61, 62) to undergo a write access only from the associated proces­sor (1, 2). Each of the cache devices (3, 4) includes a region discriminating circuit (20, 52) for determining whether an address generated from the processor (1, 2) is to be employed for an access the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices (3, 4) operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices (3, 4) operates according to the copy-back method. When the processor (2) or the input/output device (6) rewrites data in the shared region of the main memory (5), the stored data of the shared region in the cache device (3) of the processor (1) is invalidated.