Clock signal switching device of an IC card.

BACKGROUND OF THE INVENTION

Field of the Invention

0001The present invention relates to a clock signal switching device of an IC card. More particularly, the present invention relates to a clock signal switching device of an IC card for switching from an internal clock signal to an external clock signal supplied from a terminal unit, whereby an IC card operable in response to the internal clock signal can operate by the external clock signal in place of the internal clock signal when the IC card is attached to the terminal unit.

Description of the Background Art

0002IC cards provided with displays are utilized in various fields these days. Such an IC card is operable not only as a single body of a card but also in the form attached to a terminal unit. For those purposes, an IC card contains a battery, an internal clock signal generating circuit for generating an internal clock signal, and a processing circuit and, in the form of the single body of the card, the processing circuit operates in response to the internal clock signal.

0003When such a card is attached to a terminal unit, an external power is supplied from the terminal unit to the IC card and an external clock signal is also supplied thereto. The processing circuit in the IC card operates in response to the external clock signal. Thus, switching between the clock signals is required to apply the internal clock signal when the IC card is to operate in the form of a single body and to apply the external clock signal when an IC card is attached to the terminal unit. For those purposes, it is necessary to determine whether the IC card is operated as a single body or it is connected to a terminal unit. Methods for such determination include a method of detecting a mechanical contact of an external terminal provided in the IC card, and a method of detecting a difference between the voltage of the battery contained in the IC card and that of the internal power supplied when the card is attached to the terminal unit.

0004However, in view of the structure of an IC card in general, it is difficult to attach a detector to its external terminal for the purpose of detecting the above mentioned mechanical contact. The method of detecting the difference of the voltages cannot be always utilized, for example, in cases in which there is only a small difference between the voltage of the battery contained in the IC card and the voltage of the external power supply, and when a noise is mixed in the case of using the IC card as a single body, it is often erroneously determined that the card is attached to a terminal unit, causing errors in operation.

0005If an IC card is forcedly ejected from the terminal unit during communication of data between the card and the terminal unit, switching from the external clock signal to the internal clock signal occurs abruptly, causing a disorder in the program contained in the IC card.

SUMMARY OF THE INVENTION

0006Therefore, a principal object of the present invention is to provide a clock signal switching device of an IC card, which can be operated stably irrespective of whether the IC card is utilized as a single body or it is attached to a terminal unit.

0007Briefly stated, according to the present invention, in an IC card which contains containing a battery and a clock signal generating circuit for generating an internal clock signal and operates in response to the internal clock signal and to which electric power and an external clock signal are supplied from a terminal unit when it is attached to the terminal unit, pulses of the external clock signal supplied from the terminal unit are counted and in response to the count of a predetermined number of pulses of the external clock signal, the external clock signal is selected and outputted in place of the internal clock signal.

0008Therefore, according to the present invention, it can be correctly determined whether the IC card is operated as a single body or it is attached to a terminal unit.

0009In a preferred embodiment of the present invention, an internal clock signal is outputted in place of the external clock signal after an elapse of a predetermined period in response to detection of no input of the external clock signal and input of the internal clock signal.

0010Consequently, according to the preferred embodiment of the invention, the internal clock signal is selected after the elapse of the predetermined period after the external clock signal is not inputted, and accordingly an abrupt change from the external clock signal to the internal clock signal does not occur and there is no fear of disorder in the program contained in the IC card.

0011The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0012<ul id="ul0001" list-style="none"><li>Figs. 1A and 1B are block diagrams showing an entire construction of an embodiment of the present invention.</li><li>Figs. 2A and 2B are specific electric diagrams of the embodiment of the present invention.</li><li>Figs. 3, 4 and 5 are timing charts for explaining operation of the embodiment of the present invention.</li></ul>

DESCRIPTION OF THE PREFERRED EMBODIMENTS

0013Figs. 1A and 1B are block diagrams showing an entire construction of an embodiment of the present invention.

0014Referring first to Figs. 1A and 1B, the construction of the embodiment of the invention will be described. An IC card 1 has an external terminal set 2. This external terminal set is used to electrically connect the IC card 1 to a terminal unit 30 when the card 1 is attached thereto. An external power, an external clock signal and an external reset signal are applied from the terminal unit 30 through respective terminals 2a, 2b and 2c of the external terminal set 2. Those external power, the external clock signal and the external reset signal are applied to a clock switching circuit 3. An internal oscillation circuit 4 is provided to generate an internal clock signal. The clock switching circuit 3 switches between an internal clock signal generated from the internal oscillation circuit 4 and the external clock signal inputted through the external terminal set 2 and applies the signal selected by the switching to an internal circuit 5. When the IC card 1 is not attached to the terminal unit 30, electric power is supplied from a battery 28 to the clock switching circuit 3, the internal oscillation circuit 4 and the internal circuit 5.

0015Figs. 2A and 2B are specific definite electric circuit diagrams of the embodiment of the invention.

0016Referring first to Fig. 2A, a counter 17 is provided to output signals Qφ4 and Qφ5 for outputting a signal <o ostyle="single">φp</o> of a low (L) level from a NAND gate 18 and a signal φp of a high (H) level from an inverter 19 in response to the count of a predetermined number of pulses of an external clock signal f_out. A switching circuit 20 is used to switch between an internal clock signal f_in and the external clock signal f_out in response to the signal φp, so that either clock signal is outputted as a system clock φ to the internal circuit 5 shown in Fig. 1 and to a counter 21. The counter 21 is provided to output signals F1 to F4 for forming timing signals ACLR and <o ostyle="single">ACL′</o> by means of gates 22 and 23 and a latch circuit 24.

0017Referring to Fig. 2B, a counter circuit 7 is reset by an external clock signal <o ostyle="single">f_out</o>, counts pulses of the internal clock signal f_in and generates timing signals ARQ0 to ARQ2 for forming a signal AR. A latch circuit 12 is latched by an external reset signal and it is reset by a signal ACLR which attains H level after several cycles from the switching from the internal clock signal f_in to the external clock signal f_out. A synchronizing circuit 13 is provided to generate a signal ACL1 which synchronizes the output of the latch circuit 12 with clock signals φ3 and φ4 generated from the system clock φ.

0018Figs. 3, 4 and 5 are timing charts for explaining a definite operation of this embodiment.

0019Referring to Figs. 2A to 5, the definite operation of the embodiment will be described. First, in the case of operating the IC card 1 singly without being attached to the terminal unit 30, a power supply switch (not shown) provided in the IC card 1 is operated and then a power-on reset signal POR is applied to a reset input terminal of the counter 17 through an OR gate 16 shown in Fig. 2A, whereby the counter 17 is reset. The power-on reset signal POR is also applied to the counter 21 through an OR gate 25, whereby the counter 21 is reset. In consequence, the outputs Qφ4 and Qφ5 of the counter 17 are lowered to L level and the respective outputs are supplied to the NAND gate 18. The signal <o ostyle="single">φp</o> outputted from the NAND gate 18 rises to H level and it is applied to one input terminal of the NAND gate 15. In consequence, this NAND gate 15 is opened. Further, the signal <o ostyle="single">φp</o> is inverted by the inverter 19 to the signal φp of L level, which is applied to the switching circuit 20. In response to this signal φp, the switching circuit 20 selects the internal clock signal f_in and outputs this signal as the system clock pulse φ to the internal circuit 5 shown in Fig. 1. Then, in response to the system clock pulse φ, the internal circuit 5 carries out predetermined operation.

0020Next, operation in the case of attaching the IC card 1 to the terminal unit 30 will be described. When the IC card 1 is attached to the terminal unit 30, the external power, the external clock signal f_out and the external reset signal are applied from the terminal unit 30 to the external terminal set 2 of the card 1. The external reset signal of L level is inverted by the inverter 10 as shown in Fig. 2B and it is supplied as the signal ACL of H level to the OR circuit 11 as shown in (c) of Fig. 3. The OR circuit 11 outputs a signal ACLx of H level and in response to this signal, the latch circuit 12 is latched. The output of the latch circuit 12 is supplied to the synchronizing circuit 13 and the synchronizing circuit 13 synchronizes the clock pulses φ3 and φ4 with the output of the latch circuit 12 and outputs the signal ACL1 as shown in (j) of Fig. 3. This signal ACL1 is applied to one input terminal of the NAND gate 14. As a result, the NAND gate 14 is opened. The external clock signal f_out as shown in Fig. (b) of Fig. 3 is applied to the other input terminal of the NAND gate 14. The external clock signal f_out is applied to the NAND gate 15 through the NAND gate 14.

0021At this time, the counter 17 is reset by the application of the signal ACLx outputted from the OR circuit 11 shown in Fig. 2B through the OR circuit 16 and, as shown in (f) and (g) of Fig. 3, the outputs Qφ4 and Qφ5 are respectively at L level. In consequence, the signal <o ostyle="single">φp</o> outputted from the NAND gate 18 rises to H level as shown in (h) of Fig. 3, so that the NAND gate 15 is opened. As a result, the external clock signal f_out is applied to the counter 17 through the NAND gate 15. The counter 17 starts counting pulses of the external clock signal f_out. When a predetermined number of pulses of the external clock signal f_out are counted, that is, when the outputs Qφ4 and Qφ5 of the counter 17 rise to H level, the signal <o ostyle="single">φp</o> outputted from the NAND gate 18 falls to L level, whereby the NAND gate 15 is closed. As a result, the external clock signal f_out is not applied to the counter 17. Thus, the counter 17 stops counting pulses of the external clock signal f_out.

0022On the other hand, the signal <o ostyle="single">φp</o> of L level is inverted by the inverter 19 to H level and the signal of H level is applied to the switching circuit 20. In response to the signal <o ostyle="single">φp</o>, the switching circuit 20 outputs the external clock signal f_out as the system clock φ to the internal circuit 5. At the same time, the system clock φ is applied to the counter 21, so that the counter 21 outputs the timing signals F1 to F3 as shown in (c), (d) and (e) of Fig. 5. When all of the timing signals F1 to F3 attain H level, the AND gate 22 outputs the signal ACLR of H level as shown in (k) of Fig. 3 and (f) of Fig. 5 and the latch circuit 12 shown in Fig. 2B is reset by the signal ACLR. When the latch circuit 12 is reset, the synchronizing circuit 13 outputs the signal ACL1 falling to L level as shown in (j) of Fig. 3. The NAND gate 14 is closed by the signal ACL1 and the external clock signal f_out is not applied to the NAND 15.

0023The signal ACL1 is used to enable the internal circuit 5. More specifically, the internal circuit 5 is initialized in a period of H level of the signal ACL1 and after the signal ACL1 falls to L level, the internal circuit 5 operates. Thus, as shown in (j) of Fig. 3, since the signal ACL1 falls to L level after several cycles from the switching from the internal clock signal f_in to the external clock signal f_out, the internal circuit 5 operates stably and erroneous operation can be prevented.

0024Referring now to the timing chart of Fig. 4, description will be made of the case in which the IC card 1 is forcedly removed from the terminal unit 30. When the IC card 1 is removed from the terminal unit 30, the external clock signal f_out is no longer applied. On this occasion, the input terminal for the external clock signal f_out is pulled up by a resistor 26 as shown in Fig. 2B and accordingly it is raised to H level. The signal of H level at this terminal is inverted by the inverter 27 and it is applied to the reset input terminal of the counter 7, whereby the counter starts counting pulses of the internal clock signal f_in shown in (a) of Fig. 4. When the signals ARQ0 and ARQ2 of the counter 7 both rise to H level and the signal φp rises to H level as shown in (b) and (d) of Fig. 4, the latch circuit 9 is latched and the signal AR outputted from the latch circuit 9 rises to H level as shown in (e) of Fig. 4. This signal AR is inputted to the OR circuit 11 and the signal ACLx outputted from the OR circuit 11 rises to H level as shown in (g) of Fig. 4, whereby the latch circuit 12 is latched.

0025When the signal ACLx rises to H level, the counters 17 and 21 shown in Fig. 2A are reset and the NAND gate 18 outputs the signal <o ostyle="single">φp</o> of H level, while the inverter 19 outputs the signal φp of L level as shown in (h) of Fig. 4. In consequence, the switching circuit 20 selects the internal clock signal f_in and outputs it to the internal circuit 5. Thus, when the IC card 1 is forcedly ejected from the terminal unit 30, switching occurs from the external clock signal f_out to the internal clock signal f_in and thereafter the signal ACL1 falls to L level, whereby the internal circuit 5 starts operation.

0026As described in the foregoing, according to the embodiment of the present invention, when the IC card is attached to a terminal unit, pulses of the external clock signal supplied from the terminal unit are counted and, in response to counting of a predetermined number of pulses of the external clock signal, the external clock signal is selected and outputted in place of the internal clock signal. Accordingly, it can be correctly determined whether the IC card is operated in the form of a single body or in the form attached to any terminal unit.

0027Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.