Semiconductor integrated circuit device having improved input/output interface circuit
Abstract
A semiconductor integrated circuit device includes an external terminal (17, 140), an internal logic circuit (110), and an input/output interface circuit (120, 130). The input/output interface circuit includes an input circuit (7), a selection circuit (10) and an output circuit (8). The input circuit (7) receives an input signal and supplies the internal logic circuit (110) with the same. The selection circuit (10) selects either the input signal supplied from the input circuit (7) or an output signal supplied from the internal logic circuit (110). The output circuit (8) outputs the selected one of the input signal and output signal to the external terminal. A loop circuit is formed by the input circuit (7), selection circuit (10) and output circuit (8). The loop circuit logically includes an odd number of inverters.

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Projected expiry passed 7 April 2009, 17.5 years ago.
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1 sheet
Sheet 1
Every citation, both ways
| Document | Relation | Office | Category | Cited during |
|---|---|---|---|---|
| US4691161A | Cites | United States of America | A | Search report |
| US4703484A | Cites | United States of America | Y | Search report |
| IBM TECHNICAL DISCLOSURE BULLETIN, vol. 26, no. 9, February 1984, pages 4708-4709, New York, US; K.S. DAGHIR et al.: "Bypass circuit for receiver and driver delay measurement" | Non-patent | – | – | Search report |
| PATENT ABSTRACTS OF JAPAN. vol. 10, no. 48 (P-431), 25th February 1986; & JP-A-60 192 276 (TOSHIBA K.K.) 30-09-1985 | Non-patent | – | – | Search report |
| IBM TECHNICAL DISCLOSURE BULLETIN, vol. 19, no. 11, April 1977, pages 4331-4333, New York, US; D.A. HEUER et al.: "Internal oscillator ring" | Non-patent | – | – | Search report |
| IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, vol. CAS-28, no. 11, November 1981, pages 1070-1078, IEEE, New York, US; E.J. McCLUSKEY et al.: "Design for autonomous test" | Non-patent | – | – | Search report |
| "Intel microprocessor and peripheral handbook, vol. II, Peripheral", 1988, ISBN 1-55512-073-3, Intel, Santa Clara, US | Non-patent | – | – | Search report |
9 members in 5 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 8687188 | Japan | – | |
| 8687188 | Japan | A |
Members9
| Document | Office | Kind | |
|---|---|---|---|
| EP0336444A2 | European Patent Office (EPO) | A2 | |
| JPH01259274A | Japan | A | |
| KR890016391A | Republic of Korea | A | |
| US4970410A | United States of America | A | |
| EP0336444A3This record | European Patent Office (EPO) | A3 | |
| KR930000894B1 | Republic of Korea | B1 | |
| EP0336444B1 | European Patent Office (EPO) | B1 | |
| DE68921086D1 | Germany | D1 | |
| DE68921086T2 | Germany | T2 |
19 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | |
| Annual fee paid to national office [announced via postgrant information from national office to epo]GrantedPGFP | PGFP | |
| No opposition filedOpposition26N | 26N | |
| Gb: european patent ceased through non-payment of renewal feeCeasedGBPC | GBPC | |
| No opposition filed within time limitOppositionORIGINAL CODE: 0009261PLBE | PLBE | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: NO OPPOSITION FILED WITHIN TIME LIMITSTAA | STAA | |
| Fr: translation not filedEN | EN | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | |
| Corresponds to:REF | REF | |
| Designated contracting statesAK | AK | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | |
| (expected) grantORIGINAL CODE: 0009210GRAA | GRAA | |
| First examination report despatched17Q | 17Q | |
| Request for examination filed17P | 17P | |
| Main classification (correction)RHK1 | RHK1 | |
| Designated contracting statesAK | AK | |
| Search report despatchedORIGINAL CODE: 0009013PUAL | PUAL | |
| Designated contracting statesAK | AK | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI |
Numbers
- Publication
- 0336444
- Application
- 891062101
Titles3
- German
- Integrierte Halbleiterschaltkreisanordnung mit verbesserter Eingangs-/ Ausgangsschnittstellenschaltung
- English
- Semiconductor integrated circuit device having improved input/output interface circuit
- French
- Dispositif de circuit intégré à semi-conducteur comportant un circuit d'interface entrée/sortie amélioré
Classification
- CPC, 1
- G01R31/318522
- IPC, 3
- G01R31 26
- G01R31 28
- G01R31 3185
Designated states3
- Contracting states, 3
- Germany
- France
- United Kingdom