Node for a fast packet-switching network in optical-electrical technology.

The present invention relates to packet-switching telecommunications systems, and more particularly it concerns a node for a fast packet-switching network in optical-electrical technology.

Fast packet-switching, known also as label addressed switching or asynchronous time-division switching, is a digital information switching technique wherein information blocks, which are associated with a label characterizing the information and which arrive at random instant at the switching devices, are switched solely on the base of the label contents. This technique allows considerably improved performance in comparison with conventional packet switching, particularly as far as protocol simplicity, information processing speed and flexibility are concerned. For these reasons it seems the most promising switching technique for implementing a broadband integrated service network where the bandwidth requirements of the individual communications are met while respecting their time constraints, and the information is switched independently of the service type.

When implementing a broadband network, the use of optical technology appears an obvious solution, and it would be desirable to use such technology not only for transmission between network nodes, but also for switching in the nodes. Thus all optical-to-electrical conversions and vice versa could be dispensed with.

A totally optical fast packet-switching network requires optical switching matrices and optical processing means to carry out the operations relevant to node management, and more particularly signalling handling and routing.

Optical switching matrices to be used in time-division or space-division circuit-switching systems are largely described in the literature. For instance, the paper "Photonic switching using directional couplers" by H. S. Hinton, IEEE Communications Magazine, Vol. 25, No. 5, May 1987, pages 16 to 25, describes optical switching matrices based on switching elements with two inputs and two outputs; said elements can be used also for implementing self-routing switching matrices, e.g. with Omega or Delta topology, better suited to fast packet switching, as described in the paper "Access and Alignment of Data in an Array Processor" by D.H. Lawrie, IEEE Transactions on Computers, Vol. C-25, December 1975, pages 1145 and ff.

On the contrary, optical processing means having the processing capacity necessary for managing the nodes of a network of the type considered do not yet exist, even though at least relatively simple processing means, capable of controlling the routing through the optical switching matrix, might be available in the future. Therefore nowadays the most realistic solution to the problem of introducing the optical technology into a fast packet-switching network seems the use of optical-fibre connections between the nodes and of electrically-controlled optical switching matrices within the nodes.

Fast packet-switching networks combining optical switching and electrical control are not yet known in the art and it is the aim of the invention to provide a node for a network of this type.

The node according to the invention comprises: - an optical switching matrix, comprising a plurality of stages, each comprising a plurality of switching elements, for switching information packets transmitted as optical signals; - an electrical switching matrix, which is used for searching a routing through the node by exploiting information contained in the headers of the information packets and converted into electrical form, the configuration taken by the electrical switching matrix being reproduced in the optical switching matrix: - a first group of processing devices, associated with the inputs of the electrical switching matrix, for the electrical processing of the headers of the information packets, necessary to search a connection path between an input and an output of the electrical switching matrix, and for updating the headers in the optical information packets; - a second group of electrical processing devices, associated with the outputs of the electrical switching matrix, for detecting the setup of a connection between an input and an output of the electrical switching matrix and forwarding an acknowledgment packet of such a setup to the processing devices in the first group; - a centralized node controller, for the electrical processing of signalling packets.

The invention will be better understood with reference to the annexed drawings, wherein: <ul id="ul0001" list-style="none"><li>- Fig. 1 shows the general structure of a fast packet-switching network;</li><li>- Fig. 2 is a block diagram of a node according to the invention;</li><li>- Fig. 3 is a schematic diagram of the node operating phases.</li></ul>

As shown in Fig. 1, a fast packet-switching network can be considered as formed by a number of transit nodes NT1...NTn, associated each with a number of local nodes connected thereto by optical-fibre connections. For drawing simplicity only two local nodes NL1i and NLnj, connected to NT1 and NTn, respectively, are represented. The terminals generating packetized information, transmitted as optical signals, are connected to the local nodes through multiplexing/demultiplexing systems. Always for drawing simplicity, only multiplexing/demultiplexing systems MD1, MDn associated with nodes NL1i and NLnj, respectively, and only terminals T1x, Tny connected to MD1 and Mdn, respectively, are represented. Connections between terminals and multiplexing/demultiplexing systems are connections at relatively low speed, while connections among nodes and between the nodes and blocks MD are high-speed connections. In the structure proposed, relatively low speeds can be speeds up to one hundred of Mbit/s, while the high speeds can be speeds ranging from some hundred Mbit/s to some Gbit/s.

Each packet comprises, in addition to the actual information content, a header containing, i. a.: an indication of packet beginning; an indication of the type of packet (signalling, information,...) ; a protection field for the header; a label (geographic label) characterizing the communication and updated at each node; the so called "routing tag" for the routing inside the node.

Information and signalling packets can be transmitted at different wavelengths and possibly at different speeds. Some input/output lines in a node might carry only information packets, others only signalling packets, still others both packet types.

As indicated for node NL1i and as will be seen in more details hereinafter, the nodes comprise an optical switching part OS and an electrical control part EC. The optical switching part OS switches only information packets. The electrical control part processes the signalling packets and the information packet headers: more particularly, it updates the label and builds up the routing tag.

Signalling processing in a node is effected in a centralized way, while information packet headers are processed in a distributed way, in an independent manner for each switching matrix input. Besides, as to the routing through the node, a solution has been adopted wherein such routing is searched for through an electrical switching matrix, which preferably has the same topology as the optical matrix: the configuration taken by the electrical matrix is then reproduced identical in the optical matrix.

It is still to be noted that the optical switching part can operate either synchronously or asynchronously. In the first case there are cycles with constant duration, during which first the electrical switching matrix (and hence the optical one) is set, and then all packets for which a path through the node has been found are transmitted at the same time. The packets which could not be forwarded are queued in node input buffers. Obviously suitable strategies will be adopted to prevent a packet from being delayed indefinitely. In the second case the individual elements of the switching network will be associated with buffers where the packets which cannot reach the desired output of the element itself will be queued, as well as processing means for managing said buffers. The difficulty of implementing a switching network with distributed memories and optical processing capacity, has induced us to choose the synchronous operation for the present invention.

Fig. 2 shows the node structure in the most general case in which the input lines convey both signalling packets transmitted at a wavelength W1 and information packets transmitted at a wavelength W2. The different packet types are transmitted at different speeds. For drawing simplicity a single input line 1 and a single output line 17 have been shown. Double lines indicate optical signal paths, while single lines indicate electrical signal paths.

Each input line 1 of a node arrives at a respective wavelength demultiplexer WD which separates signalling packets from information packets and forwards the former on line 5 and the latter on line 2.

Signalling packets on line 5 are converted into electrical signals by an optical-to-electrical converter COE1 and hence are sent to signalling processing devices in electrical control equipment EC. Information packets on line 2 arrive at a beam splitter SEP which shares the power associated with the optical signals between line 3, leading to optical switching devices OS, and line 4, leading to an optical-to-electrical converter COE2 and hence to devices for processing information packet headers in electrical control equipment EC. At the node output, a wavelength multiplexer WM recombines into a single optical packet flow, on line 17, packets outgoing from OS as well as packets arriving from EC, converted again into optical form by an electrical-to-optical converter CEO.

Optical switching devices OS comprise the actual switching matrix MOT and an optical buffer BOT for each input of switching matrix MOT; the buffers are to temporarily store information packets to be switched through MOT.

The electrical control equipment EC comprises two groups of devices, processing the signalling packets and the information packet headers, respectively.

The first group of devices, inserted between COE1 and CEO, comprises: - a synchronization device SIN1, which extracts from the arriving signalling packet flow timing signals CKE1 for signalling packet acquisition by the node, and recognizes the beginning of each such packet, generating signal IN1; - a buffer BEIS temporarily storing the signalling packets, emitted by SIN1 on connection 6; - a node controller CEL, for the electrical processing of the signalling packets present on line 9 outgoing from BEIS; - an output buffer BEOS storing signalling packets emitted by CEL on output 10, before the packets are forwarded onto line 11 towards CEO, WM and line 17.

The devices processing information packet headers comprise: - a synchronization and decoding device SIN2, identical to SIN1; SIN2 emits timing signals CKE2, IN2 which have for the information packets the same functions as CKE1, IN1. - a buffer BEL, temporarily storing the headers of the information packets present on line 7, outgoing from SIN2; - a first processing unit PEE (input processor), performing the processings of information packet headers required for packet switching in the node, on the basis of the information supplied by CEL through connection 12; - an electrical switching matrix MEL, topologically identical to MOT, which is used in the routing search; - a memory MPM, storing the configuration taken at each network cycle by MEL and controlling accordingly the setting of MOT; - a second processing device PUE (output processor), recognizing that a connection has been set up between an input and an output of MEL and forwarding a packet acknowledging the occurred connection to input processor PEE associated to that input.

Controller CEL is unique for the whole switching node: supposing that z input/output lines, k of which carry both information and signalling packets, are connected to the node, reference numerals 9a ..9k, 10a...10k denote the connections of CEL with the k branches comprising each devices COE1, SIN1, BEIS and respectively BEOS, CEO, handling signalling packets; references 12a...12z denote the connections with the z branches comprising each devices SEP, COE2, SIN2, BEL, PEE, PUE, BOT handling the information packets.

Also matrices MOT, MEL, and memory MPM are unique; the matrices have z inputs/outputs indicated in the Figure by 13a...13z, 14a...14z (for MEL) and 15a...15z, 16a...16z (for MOT).

The node also comprises a time base BT extracting from a main clock signal CKM (node clock) the local signals necessary to time the various operations in the node. At the output from BT the whole of the local signals is shown at CKL. At the inputs to the various blocks there are explicitly indicated signals CKL1, CKL2, CKL3, RC, T, R used respectively for: timing reading in BEIS and writing/reading in BEOS ; timing reading in BOT; timing reading in BEL; reproducing into MOT, through MPM, the configuration of MEL; starting optical packet transmission through matrix MOT; starting the setting of electrical matrix MEL.

Signals CKE1, CKE2, which are directly extracted from packet flows on lines 5, 2 by devices SIN1, SIN2, by exploiting synchronization packets or synchronization information contained in signalling/information packet headers, are used as synchronization signals for writing into input buffers BEIS and respectively BOT, BEL.

CKL1 and CKL2 are signals at the same rate as CKE1 and respectively CKE2. CKL3 is a slower signal, as will be seen hereinafter.

The optical switching matrix MOT is made of 2-input and 2-output switching elements, which are capable of switching packets having a length e. g. of the order of one thousand bits and are connected so as to form a self-routing network suitable for a fast packet-switching system with Delta or Omega topologies.

Optical buffer BOT loads the bits of an information packet starting from the instant of recognition of the packet beginning (signal IN2) and with the timing established by CKE2. After the header has been updated by PEE, the information stored in BOT is read with the timing established by CKL2. Taking into account that writing into BOT can start after recognition in SIN2 of the packet beginning, a delay line is conveniently inserted along line 3, leading to BOT optical packets to be memorized. The delay line is schematized by loop 3a and is made for instance by a winding of the same fibre which forms line 3. Memory BOT can be made of a group of bistable lasers and directional couplers, driven by input processor PEE. The use of bistable lasers as memory elements and their command by electrical signals is described e.g. in the paper "An experiment on high speed optical time-division switching" by S. Suzuki et al., Journal of Lightwave Technology, Vol. LT-4, No. 7, July 1986, pages 894 to 899.

Electrical buffers BEIS and BEOS are wholly conventional and have each a capacity which is multiple of the signalling packet length (of the order of 100 - 300 bits). The electrical buffer BEL, this too conventional, has a capacity which is multiple of the length of the packet header (e. g. 32 bits).

Input processor PEE has the typical tasks of similar devices in already proposed fast packet-switching networks: more particularly PEE updates the label in the optical packet stored in BOT and builds the routing tag in the electrical "header packet", on the basis of the information supplied by CEL. The tasks of PEE are described in greater details e. g. in the paper "Fast packet-switching technique in first generation ISDN", presented by C. Demichelis, G. Giandonato, S. Giorcelli and R. Melen at the International Switching Symposium ISS '87, Phoenix (USA), 15 - 20 March 1987.

Matrix MEL is based on topologies proposed for fast packet-­switching networks and preferably it is topologically identical to MOT. It will consist of switching elements of considerably smaller capacity than that required for the elements of MOT, since they are to switch only the packet headers. Therefore MEL can operate at a much lower speed than MOT and it is timed by signal CKL3, and not by signal CKL2 representing the line speed. E. g., if the optical transmission takes place at a speed of the order of some hundred Mbit/s, the speed required in MEL can be of some tens Mbit/s. The routing path for each packet is built through MEL, as in a conventional network, and is then reproduced in MOT.

Memory MPM comprises a position for each switching element in MEL and, as the various elements in MEL become set, such a position will store the bit indicating the configuration taken by the corresponding element of MEL. Block MPM comprises also the drivers necessary to transform the logic signals stored therein into signals having the power necessary to drive the elements of MOT.

The output processor PUE can consist of a read only memory, whose reading command is associated with the "header packet" arrival at the output of MEL associated therewith.

All other node blocks carry out functions well known in the art, and hence further information is unnecessary.

Fig. 3 shows the subdivision of an operating cycle of the node in the case disclosed of distributed routing control and of synchronous operation. As shown, basically three time phases can be recognized: - in the first phase, which lasts from instant t0 of cycle beginning until an instant t1, the operations necessary to set MEL and to update the packet header in BOT take place: the phase duration is Te.(Lh + S), where Te is the duration of an electrical bit, Lh is the length of the packet header, expressed as number of bits, and S is the number of stages in MEL; - the second phase, t1 to t2, is devoted to transmission from PUE to PEE of the acknowledgment packet: the duration of the second phase is Te.(La + S), where La is the length in bits of the acknowledgment packet, and Te, S have the meaning said above; in this second phase also the setting of MOT will be effected; - the third phase, from t2 to the cycle end t3, is devoted to the transmission of packets stored in memories BOT through the matrix; this phase will have a duration To.Lp, where To is the duration of an optical bit and Lp is the length in bits of the packets to be switched.

It is to be noted that while a packet is being transmitted, the acquisition of the following packet present on the same node input and the label processing can start: network cycles can then overlap. Besides, suitable guard times between the various phases will be provided.

The node operation will be now described, with reference to the diagram of Fig. 3.

A packet arriving on line 1 (Fig. 2) can be a signalling or an information packet. It has been assumed that the packet is modulated in the first case at wavelength W1 and in the second case at a wavelength W2 different from W1. The wavelength demultiplexer WD placed at the node input forwards the packet on line 5, if it is a signalling packet, or on line 2, if it is an information packet.

Considering first the signalling packets, these packets, after conversion into electrical signals in COE1, are temporarily stored in memory BEIS (enabled by signal IN1 emitted by SIN1) to be subsequently processed by CEL. As mentioned above, the storage in BEIS is timed by CKE1 while the transfer to CEL is timed by CKL1. Signalling processing, which does not differ from the processing in any electrical fast packet-switching network, results in the generation of new signalling packets or in the transmission of the received packet to another network node. In any case the signalling packet(s) outgoing from CEL is (are) stored in memory BEOS (with the timing established by CKL1) and then they are extracted therefrom, converted by CEO into optical signals at wavelength W1 and wavelength multiplexed with the optical information packets at wavelength W2 coming from line 16.

Signalling processing is not concerned by the present invention and hence it will not be described further.

When an information packet arrives, it is forwarded by WD onto line 2 and duplicated by SEP: the packet on line 3 is stored into the optical buffer BOT, while the packet on line 4 is converted into electrical signals and transferred to SIN2; SIN2 recognizes the packet beginning and enables storage into BOT and BEL. More particularly, only the packet header is to be loaded into BEL. The packet is loaded into BOT and BEL with timing CKE2 extracted from arriving information packet. Since BEL is to store only the header, while loading into BOT is being completed, the packet header is already available to PEE, which can then start its operations.

PEE receives from CEL, through connection 12, the information relevant to the communication to which the packet refers and on the basis of such information it replaces the input label by the output label in the optical packet stored in BOT and builds the routing tag in the electrical "header packet" read from BEL with the timing established by CKL3 and supplied to PEE through line 8. The modified electrical "header packet" is sent through self-routing network MEL (operation started by signal R) and, as the individual elements of MEL become set in the manner indicated by the routing tag bits, the configuration of the individual elements (crossed, straight) is stored into MPM.

The same operations are carried out in parallel for all other node inputs.

Whatever the result of the search for a routing path, at instant t1 (Fig. 3), the operations related to the setting of MEL (Fig. 2) are over and reading command RC for MPM can be emitted in order to set MOT.

Supposing that a routing path has been found for the "header packet" considered, at instant t1 such a packet is present on an output of MEL and enables output processor PUE to start backwards transmission of the acknowledgment packet via the same path followed by the "header packet". When PEE has received such a packet (instant t2), the reading of the whole information packet stored in BOT can be enabled (signal T), and the packet is transferred towards line 17 through MOT and WM. At the same time all other optical packets for which a routing path through MEL has been set up, are read. While an optical packet is transmitted through network MOT, the operations concerning acquisition of the following packet can begin.

It is worth noting that the packets arrive at the various node inputs at random instants. In a cycle, only the packets whose headers have been completely loaded into buffers BEL and have been processed within the proper time phase will be transmitted through MOT; the others will be read in the subsequent cycles.

It is clear that what described has been given only by way of non limiting example and that variations and modifications are possible without going out of the scope of the invention. Thus, even if it has been implicitly supposed that devices PEE, PUE are associated with each input/output of MEL, it is evident that their number can be lower than that of the inputs/outputs of MEL, since a same device PEE or PUE can serve a group of inputs or respectively outputs of MEL. Besides, it is evident that the lines which carry only information packets will be directly connected to devices SEP, while the lines which carry only signalling packets are directly connected to converter COE1: in both cases device WD is unnecessary, as device WM is unnecessary on output lines conveying an only type of packet. Further, even though in the example described an electrical matrix MEL topologically identical to MOT has been considered, matrices with different topologies can be used: e.g. matrix MEL can have greater dimensions, but a topology allowing a faster setup.