Time variant drive for use in integrated circuits

A circuit is provided which modifies a digital drive signal to produce a time variant drive signal for appli­cation to a gate of a bus driver transistor. The circuit's purpose is to reduce the amplitude of ringing on a bus, due to rapid discharging of current from the bus, in order to prevent unintentional triggering of devices connected to the bus. A P-channel MOS transistor (60) and N-channel MOS transistor (50) are connected so that the digital drive signal (VG) is simultaneously applied to the source of the P-channel MOS transistor (60) and to the drain of the N-channel MOS transistor (50). The gate of the driver transistor (10) is connected to the drain of the P-channel MOS transistor (60) and the source of the N-channel transistor (50). The width-to-length ratio of the channels of the P-channel (60) and N-channel MOS (50) transistors, and the gate voltages, are chosen so that application of a drive signal to the circuit causes the N-channel MOS transistor (50) to rapidly apply a limited drive signal to the gate of the driver transistor (10) and causes the P-channel MOS transistor (60) to apply a gradually increasing drive signal voltage to the gate of the driver transistor (10). By choosing the proper width-to-length ratios and gate voltages, the time variant drive signal applied to the gate of the driver transistor (10) will not produce objectionable ringing on the bus when the bus is intended to be at a low level.