Method of manufacturing a thin film transistor.

0001This invention relates to the manufacture of thin film transistors (TFTs) by the deposition of polysilicon.

0002Figure 1 of the accompanying drawings illustrates the first steps in a well-known process for the formation of a polysilicon TFT. Firstly, a layer (Figure 1(a)) of silicon dioxide is deposited on a glass substrate 2. A layer 3 of polysilicon is then formed over a region of the silicon dioxide layer. A further area 4 (Figure 1 (b)) of silicon dioxide is formed on the layer 3, and a gate region 5 of polysilicon is formed in alignment with the area 4. The gate region 5 and regions 6 and 7 of the layer 3 projecting beyond the gate region are then doped (Figure 1 (c)) by ion implantation to form gate, source and drain regions respectively, of n⁺ polysilicon. Contact layers (not shown) are subsequently formed over the regions. During the ion implantation process, the gate region 5 acts as a mask, which should prevent doping of the central region 8 of the layer 3. However, unless very careful control over the ion implantation process is maintained, the doped regions 6 and 7 will extend underneath the gate region 5, forming parasitic capacitances between the gate and the source and between the gate and the drain. The capacitances will reduce the speed of the operation of the device.

0003Furthermore, the ion implantation process accounts for a major part of the cost of forming the device. Moreover, ion implantation is not suitable for the production of TFTs over a large area.

0004In an alternative known process, (not shown), the lower silicon dioxide layer is covered with a mask having apertures through which doped source and drain regions similar to the regions 6 and 7 are deposited. A layer of polysiliocn is formed over those regions, followed by a silicon dioxide layer. A gate region similar to the region 5 is then formed centrally on the silicon dioxide layer. There is a considerable likelihood that the gate region will overlap the edges of the source and drain regions, and parasitic capacitances such as mentioned above will result.

0005It is an object of the present invention to provide a process for manufacturing polysilicon TFTs which does not involve the use of ion implantation to produce the conductive regions, and in which the production of the above-mentioned parasitic capacitances is avoided.

0006According to the invention there is provided a process for manufacturing a thin film transistor, including the steps of forming a first polysilicon layer on a substrate; forming a silicon dioxide layer on a region of the first polysilicon layer leaving exposed regions of said first polysilicon layer; forming a second polysilicon layer on the silicon dioxide layer and aligned therewith; and depositing on the second polysilicon layer and on the exposed regions of the first polysilicon layer, regions of a selectively-grown electrically-conductive film, which film will not grow on the edges of the silicon dioxide layer but will grow on the exposed polysilicon.

0007Preferably the electrically-conductive film is formed of tungsten.

0008An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which <ul id="ul0001" list-style="none"><li>Figure 1 illustrates steps in a known TFT manufacturing process as described hereinbefore, and</li><li>Figure 2 illustrates corresponding steps in a process in accordance with the invention.</li></ul>

0009Referring to Figure 2(a), a layer 9 of polysilicon is formed on a substrate 10. A layer 11 (Figure 2(b)) of silicon dioxide is formed over a region of the layer 9, and a layer 12 of polysilicon is formed over the layer 11 and in alignment therewith. The device is then heated in a chemical vapour deposition chamber so that a substrate temperature of around 350°-450°C is achieved. Tungsten hexafluoride is introduced into the chamber. A conductive layer 13 (Figure 2(C)) of tungsten is thereby selectively-grown on the layer 12 and on the exposed regions 14 and 15 of the layer 9. It is found, however, that the film 13 does not grow on the edges 16, 17 of the silicon dioxide film, which therefore remain uncoated.

0010The film therefore forms a conductive gate electrode 18 and conductive source and drain electrodes 19, 20 which are isolated from each other and the edges of which would be exactly aligned with each other if it were not for the portion of the layer 13 on the vertical edges of the layer 12. However, that layer is extremely thin, so that there is no appreciable overlapping of the regions to constitute the above-mentioned parasitic capacitances.

0011The device can be subsequently heated to cause the tungsten to diffuse into the upper surfaces of the polysilicon layers 9 and 12, as show in Figure 2(d).

0012Although deposition of tungsten by a chemical vapour deposition technique is described above, any conductive material may be deposited by any method in which the material will grow on the polysilicon but not on the edges of the silicon dioxide layer. For example, selective silicon epitaxy, phosphorus-doped, may be used.

0013It will be apparant that the expensive conventional ion implantation process is not required in the process of the present invention.