Switching network and controller for a switching system.

p0001The invention relates to a switching network and a switching network control for a switching system according to the preamble of claims 1 and 2. FIG.

p0002In communication networks, the proportion of data traffic to be transmitted is constantly increasing. To cope with the traffic switching systems were constructed separately for data and voice traffic. Since the data rate of the transmitted data signals can assume a plurality of different values, it is difficult to combine data and telephone exchange in a network node.

p0003As part of the development of future integrated broadband networks will be discussed, according to which method the digital or analog information - to be transferred to digital networks - partly with high bandwidth requirements. Known a long time is the packet switching (packet switching), in which the (digital) news flow is divided into individual packages. In each packet Additional information is in addition to the payload included, inter alia, information about the destination (address). This message can be direct to a partner involved in the connection, which only requires transmission capacity, when in fact there is a message to be transmitted by virtue of their packet addresses.

p0004Furthermore, has long been the circuit switching (circuit switching) known which transmission capacity for the entire duration of the connection requires, regardless of whether just messages are received or not. In particular, the telephone network bi-directional transmission paths are provided, although generally speaking, only one of the two telephone subscriber.

p0005So far, the application of the packet switch led to the traffic throughput rates in the order of 1000 packets per second and above. For future services using the method of packet switching, for example, in the image communication, is expected already with a thousand times the amount. To achieve such throughput rates, the time-consuming treatment of the logs from the actual through-connection process is the "Fast Packet Switching" separated and the packages are distributed according to their destination addresses to the transmission paths. To speed up the circuit switching operation in the switching networks are highly simplified protocols which can be evaluated very quickly. At the entrance of the switching node, the incoming data packets are locally processed by this condition according to their destination internal address information, switched via the central switching network and are then passed to the output without the internal address information.

p0006Embodiments of the "Fast Packet Switching" are "Asynchronous Time Division" and "Frame Relaying". With regard to the transmission method (Transfer Mode) differentiates "Synchronous Transfer Mode" and "Asynchronous Transfer Mode" and a mixed form "Hybrid Configurations". When "Synchronous Transfer Mode" a particular transmission channel is identified solely by its time interval of a sync word. The "Asynchronous Transfer Mode", the respective channel by the address (header) of its packets (blocks) gekennzeich net, in particular the beginning of the blocks can be recognized, so that can evaluate the headers. For this purpose flags or a coded synchronous structure can be used, which requires a constant block length. An example is "Asynchronous Time Division", in which repeatedly sync words are displayed as "empty blocks" in the bit stream.

p0007Practical significance should first obtain hybrid configurations with combination of "Synchronous Transfer Mode" and "Asynchronous Transfer Mode", because the network operator due to the high investment costs will continue to use the existing, according to the "Synchronous Transfer Mode" structured networks as long as possible.

p0008In European Patent Application Publication No. 0183592, a broadband switching system was proposed, in which the message into blocks (cells) divided and transmitted through wideband transmission links according to an asynchronous time-division multiplex method. The blocks (cells) may have the same or different length. The blocks comprise useful as well as address information, the address information is housed in a so-called block header (header). The number of bits of one block is referred to as the length thereof, being provided in the standardization proposals therefor between 120 to 256 bits for the payload and 32 or 16 bits for the header. The time intervals in which blocks are transmitted are called a frame (frames). Here, a frame containing a valid block or be empty. Between two subscribers of the broadband switching system a "virtual circuit" (virtual connection), which is maintained by the fact that the abgesand th of the subscriber equipment blocks are provided with unique header identifiers which allow the switching node the correct routing of the blocks. The arriving in the switching node blocks from an incoming line to be transferred under implementation of the header to an outgoing line. Since during a frame two or more blocks may arrive for the same output line, so-called queue buffers must be provided in the switching node. In the waiting buffer one or more of these blocks are long cached until for this is a free framework.

p0009With regard to the waiting buffer arrangement, the switching node zentralgepufferte systems (such as from the European Patent Application Publication No. 0,183,592 known) or locally buffered systems. In centrally buffered systems there is only one buffer in which each incoming line stores its incoming blocks and reads intended for them blocks back from each outgoing line. Systems with decentralized buffering are to the effect discriminated whether buffering of blocks exclusively on the input side (is an embodiment of this example, in the German patent application with the official file reference P 37 14 385.9 described) is carried out or whether the buffer only before the outgoing lines ( . see, for example, IEEE, B 10.2.1, 1987, "The knockout Switch: A Simple, Modular Architecture for high-performance Packet switching of JS Yeh et al) are arranged or whether it concerns systems with input and output buffering here. one also speaks of Koppelfeldpufferung when each crosspoint of a switching matrix is ​​associated with a buffer.

p0010As the above shows, requires the design of the switching network for a switching node of a broadband switching system lengthy investigations and special considerations to take into account the variety of dependencies and their mutual influences. In addition, it should be noted that the circuit technology is for the considered switching networks at the boundaries of the current semiconductor switching times. In particular, performance bottlenecks can occur when multiple blocks are simultaneously sent through the switching network of a switching system. The blocks can influence each other when fewer lines are in the switching network as necessary paths. Two types of interference are of particular importance: the conflict and the obstruction.

p0011Two blocks (or she emitting circuits) conflict with each other when the same circuit components are to be used for transmission. Usually one of the blocks relative to the other is then prioritized and the other block must either wait or lost.

p0012When disability is a block must V wait for the operation of a block U, at the same time but U is not operated because of a conflict between block U and a third block W occurs. Thus, a normal wait situation is in a waiting buffer no hindrance as long as the first block is transferred to the buffer in each frame cycle. Only when this occurs in a conflict and is not operated by the same time, no other block can be transmitted in this queue buffer, there occurs a disability.

p0013The concept of disability is for performance valuation of such systems important. Because if a non-empty queue buffers during a reference period can not be processed, so you can imagine that instead an additional "virtual" block is processed. The sum of the virtual and real load then gives the overall load on the system. The virtual load, in some switching networks almost as large as the real load. This is especially true for switching networks that use input buffering.

p0014In Fig. 1 a switching matrix is ​​shown having input, which is described in the German patent application with the official file reference P 37 14 385.9. In the description of this German patent application is incorporated herein by reference.

p0015From the busbar system with feeder lines Z and trunk lines A a switching network is constructed in the manner of a space-division switching network. For each crosspoint CP own evaluation logic is provided for the information contained in the block header. The on the feeder line Z supplied blocks are incorporated within the matrix input side in the input buffer B. The frame received by the subscriber or the previous switching node are right-justified in the input buffer B. By means of each crosspoint CP associated comparator C is stored in the memory SCA address the columns arranged trunk lines A compared to the routing information contained in the block header. Each of the trunk lines A is associated with a decision circuit CA, which determines the order of to be through, line by line arranged feeder lines Z in the case of equal Weglenkungs information. The order is determined by the spatial arrangement on the feeder lines Z, each decision circuit CA polls all assigned comparators C cyclically.

p0016To the input of buffer B to the number of trunk lines is A corresponding number of shift registers SR is connected, in which the routing information is stored. Each shift register SR is connected on one side to the coupling point CP and the other hand to the comparator C. The activation input of the associated cross point is connected to the decision circuit CA to the comparator C. The decision circuit CA controls by an output from a logic circuit L signal to include a new routing information in the shift register SR. The signal is triggered by one of the logic circuit L supplied enable signal ALE.

p0017The buffer B connected to the input logic circuit L comprises a first AND gate U1 and a first OR gate O1. Each of the first input of the first AND gate U1 and the first OR gate O1 of the logic circuit L is connected to the decision circuit CA. The second input of the first OR gate O1, the output of which is connected to a reset input R of a bistable flip-flop RS, a signal generated in the switching node start signal I is supplied. The second input of the first AND gate U1, the output of which is connected to the first input of a second OR gate O2, a current generated in the switching node clock data DC is supplied. The inverting output of the bistable flip-flop RS is connected to a first input of a second AND gate U2, at whose second input a current generated in the switching node frame clock HC bears. The output of the second AND gate U2 is connected to the second output of the second OR gate whose output is connected both to the input buffer B and with the shift register SR. On the set input S of the bistable flip-flop RS is a in the switching node derived from the frame clock HC blocking signal DNH.

p0018If the bistable flip-flop RS at the inverting output emits a switching signal and on the second input of the second AND gate U2 abuts the frame clock HC, the block header of the first frame is read in the input buffer B in the shift register SR. The comparator C compares the contained in the block header routing information with the included memory address of SCA arranged in columns serving lines A.

p0019In the case of compliance CA are given a signal from the comparator C to decision circuit and the decision circuit CA shall use the received signals to specify the order of to be through, line by line arranged feeder lines Z. The decision circuit CA sets this to the input buffer B, the enable signal ALE and turns through the selected crosspoint CP. With the help of the data clock DC data D via the coupling point CP are connected to the trunk line A.

p0020In the event that no routing information is contained in the block header, stored in the shift register SR routing information is not sent to the trunk line A.

p0021In the P 37 14 385.9 Thus, a switching device is described according to the principle of the asynchronous time-division multiplex technique, which is constructed in the manner of a space division switching matrix. Each crosspoint CP is equipped with a comparator C which compares the address of the arranged in columns A trunk line with the way steering information. In case of a multiple match in a column one of the trunk line A associated decision circuit CA determines the order in which to switch the crosspoints (Fig. 1).

p0022Here, an input buffer B is connected to each feeder line Z, in which the blocks are cached until they reach one of the trunk lines A.

p0023As shown by extensive research, it is possible that this high loads lead to buffer overflows. This will be explained in more detail below, being additionally made to Fig. 2a. We consider the case of an access conflict of a number n feeder lines Z on a trunk line A_i, The decision circuit CA controls the order in which each of the first blocks of the n affected input buffer B to the trunk line A_i reach. There is an input buffer B_k (Feeder line Zk) with the longest waiting time: Here the first block P must_1k in the input buffer B_k wait (n-1) block transmission times until he A on the line_i arrives. The second block P_2k This input buffer B_k must wait n block transfer times to get to his desired output line A_jto get. This waiting time is in particular even if the output line A_j was free during the duration of n frame transmission times. This example shows that free channel capacity remain unused, what then is clearly noticeable at high loads.

p0024The invention is based on the object, a switching network and a switching network control for a switching system to provide such a way that the occurrence of performance bottlenecks is within the matrix largely avoided.

p0025This object is achieved by a switching network having the features of claim 1.

p0026The switching network according to claim 1 has the advantage that no major delays in the through-connection of the blocks occur in the switching network and the emergence of conflicts is largely avoided.

p0027The switching network control according to patent claim 2 avoids the disadvantages largely by each crosspoint an input buffer is allocated. In reference to Fig. 2b described situation the input buffers B_ik and B_jk both the blocks P_1k and P_2k, The line for the A_j certain block P_2k must - regardless of the type of access conflict on the line A_i - Just a block transfer time to wait for this to the free line A_j can pass.

p0028The invention will in the following with reference to the drawing shown in embodiments described in more detail and explained. Show it:<ul><li>FIG. 1 shows an embodiment for a switching network having input,</li><li>Fig. 2a and 2b in juxtaposition assigning input buffer and switching network according to FIG. 1 and Fig. 3,</li><li>Fig. 3 shows an embodiment for a switching network with Koppelfeldpufferung,</li><li>Fig. 4 shows another embodiment for a switching network with Koppelfeldpufferung and</li><li>Fig. 5 shows another embodiment for a switching matrix having input when used as a concentrator.</li></ul>

p0029The embodiments of switching networks with expansion stage (Dekonzentrator) according to FIG. 1 and 2a were already explained in detail. These switching networks can be built up from identical units BE, whereby the switching network is "columns" dismantled. Preferably, the data of the feeder lines Z all units BE offered in parallel with a bus-type wiring (see Fig. 3). The implementation of the feeder line Z to the bus-type wiring is made of interface circuits IM.

p0030Each interface circuit IM contains functions for serial-parallel conversion of the data a buffer circuit P, all incoming data is synchronized to a block start with. The interface circuit IM and BE units are preferably designed as plug-in cards for a backplane wiring, with the said bus type cabling is to be realized particularly advantageous.

p0031In Fig. 4 there is shown a switching network control for a switch fabric with Koppelfeldpufferung (with input buffering unit), the function of the circuit parts used was already explained in detail with reference to FIG. 1. In the constructed like a space-division switching network busbar system is connected to each feeder line Z each one of the number of trunk lines (A) is connected to appropriate number of input buffers B, in which the supplied blocks are cached. On the output side bus of an input buffer B a the crosspoint associated comparator C is connected, which compares the address stored in the memory SCA arranged in columns trunk lines A with the routing information. In case of multiple match the order in which to be through, line by line arranged feeder lines Z is defines by the affiliated both to the comparators C related as well as the coupling points CP decision circuit CA.

p0032Each comparator C is connected to a flip-flop FF, at its inverting output crosspoints CP and to whose non-inverting output the decision circuit CA is connected.

p0033After evaluating the way steering information by the comparator three cases must be distinguished:<ul><li>1. The block P_1k is for the trunk line A_l thought and will receive from the decision circuit CA, the trunk line A_l allocated. In this case, the crosspoint CP, and the block P on_lk is read from the input buffer B (activating the Line ALE).</li><li>2. The block P_1kis intended for the trunk line and the line Al A_l has not been allocated by the decision circuit CA. This is a waiting state until the trunk line A_l is assigned (see FIG. 1).</li><li>3. The block P_1k is not for the trunk line A_l thought. There is no signal from the decision circuit CA. The line ALE is activated via the inverting output of the flip-flop FF. The block P_1k is read, but does not pass through the switching point CP to the trunk line A_l,</li></ul>

p0034. The decision circuits of Figures 3 and 4 define in non-empty buffers a falling priority feeder lines 1, 2, ... This does not incur any unfair decision algorithm is implemented, this prioritization should be different for each unit BE, as in the following manner: <tables id="tabl0001" num="0001"><table frame="topbot"><tgroup cols="2" colsep="1" rowsep="0"><colspec colnum="1" colname="col1" colwidth="78.75mm" /><colspec colnum="2" colname="col2" colwidth="78.75mm" /><thead valign="top"><row><entry namest="col1" nameend="col1" align="left">trunk line</entry><entry namest="col2" nameend="col2" align="center">Falling priority feeder lines</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="right">1</entry><entry namest="col2" nameend="col2" align="right">1 2 3 ...</entry></row><row><entry namest="col1" nameend="col1" align="right">2</entry><entry namest="col2" nameend="col2" align="right">2 3 4 ...</entry></row><row><entry namest="col1" nameend="col1" align="right">3</entry><entry namest="col2" nameend="col2" align="right">3 4 5 ...</entry></row></tbody></tgroup></table></tables>

p0035A unit BE can be advantageously used for concentrator applications: then causes a concentration of data streams from m lines on a line. however, an additional component is needed for the reverse direction then, as illustrated in Fig. 5. It permits to convey the data coming from a feeder line Z according to their way steering information to n trunk lines A: This is also a demultiplexer function.

p0036Since no access conflict may occur, the decision circuit CA is omitted. . The component of Figure 3 can also act as a statistical multiplexer: In this case, the comparator C must show that even a block on the corresponding feeder line Z is present.