Serial memory, picture memory device and reproduction apparatus comprising one or more serial memories.

Background of the invention.

The invention relates to a serial memory, comprising a series of memory cells, data input means, data output means, control signal input means, clock signal input means and serial address input means sharing a particular terminal with said control signal input means.

A memory of this kind is known from U.S. Patent No. 4,159,541.

The memory described therein has only four terminals; this appears to be an absolute minimum, but such a small number reduces the flexibility; for example, all input and output data, in addition to address signals and mode-control signals, must pass through a single terminal. Furthermore, the known memory uses CCD-technology which is energy-inefficient.

Summary of the invention.

It is an object of t!' invention to provide a serial memory comprising a clock-incremented address counter and having low dissipation as well as easy accessibility.

To achieve this, the serial memory in accordance with the invention is characterized in that the memory is suitable for the non-shifting storage of information and furthermore comprises at least one address counter suitable for accepting, under the control of an activation signal received on said control signal input means, a preset address received on said serial address input means, said at least one address counter receiving address incrementation signals from said clock signal input means.

Further aspects of the invention.

A first embodiment of the serial memoy is constructed so that it comprises a read address counter as well as a write address counter, each counter being selectively loadable by connection to respective associated serial address input means. This offers greater flexibility.

In a further embodiment, the serial memory is constructed so that a reset input is used as the serial address input means. This offers the advantage of easy implementation.

In another embodiment the serial memory is constructed so that it comprises recognition elements for header information which precedes the preset address and is receivable on the serial address input means, which header information uniquely identifies the beginning of a subsequent preset address, and/or for termination information which succeeds the preset address and which can be received on the serial address input means, which termination information uniquely identifies the end of a preceding preset address. This facilitates the detection of the preset address.

A further embodiment of the serial memory is constructed so that said recognition elements comprise an output via which, after detection of a given pattern in said header information, a signal is supplied which ensures that the normal function of said input means, used as the serial address input means and also usable for another signal, is cancelled until the inspection of said preset address has been completed. This simplifies the input of the preset address.

The invention also relates to a picture memory device comprising one or more of the described embodiments of serial memories, and a reproduction apparatus comprising a reproduction element and a picture memory device, of the kind set forth.

The facility for supplying a preset address can be used in video signal processing, for example for "picture in picture" and "zoom".

Brief description of the Figures.

The invention will be described in detail hereinafter with reference to some Figures. <ul id="ul0001" list-style="none"><li>Fig. 1 shows the interface of a known serial memory module for 256Kx4 bits,</li><li>Fig. 2 shows a circuit diagram of the preset mechanism,</li><li>Fig. 3 shows a timing diagram for a preferred embodiment with a header and a termination information pattern,</li><li>Fig. 4 shows a diagram of hardware suitable for the preset mechanism,</li><li>Fig. 5 is a breadboard representation of the reset mechanism, and</li><li>Fig. 6 shows a reproduction apparatus comprising a picture memory device.</li></ul>

Description of a preferred embodiment.

Fig. 1 shows the interface of a memory module comprising separate connections for read and write operations.

There are provided 4 inputs for data (DinO-Din3); 4 outputs for data (DoutO-Dout3); 2 connections for power supply (VDD, VSS); a write enable pin and a read enable pin (WE, RE) for (de-) activating write and read operations, respectively; a serial write clock connection and a serial read clock connection (SWCK, SRCK) for synchronization; a write reset pin and a read reset pin (RSTW, RSTR) for resetting the write address and the read address to zero, respectively, so 16 pins in total.

In the present embodiment the reset inputs for reading and writing are used as the serial address input means for inputting the preset address with the header information and termination information.

Fig. 2 shows the circuit diagram of the preset mechanism. Via the serial address input means (in this case one of the reset inputs) the preset address enters the associated address counter S or L which addresses, in combination with a decoder, a given memory cell MC and which subsequently counts further as from the preset address. The terms used are the same as those used in Fig. 1.

Fig. 3A shows a timing diagram for a normal reset operation. Resetting is asynchronous in this case: in response to the transition from 0 to 1 of the reset signal RS, the address counter AC (for reading or writing) is reset to the address 0. The address counter counts further in the rhythm of the clock signal CK (for reading or writing) The increment of the address counter is chosen to be 1 in the present case, but may also have any other arbitrary value (also a negative value) which is not equal to 0. It will be apparent also that resetting need not necessarily take place to the address 0, and that any other fixed address is also feasible.

Fig. 3B shows a timing diagram for a reset instruction in a preferred embodiment in which the reset input is used as the serial address input means for the input of a preset address with preceding header information and subsequent termination information. The reset signal RS is synchronised with the clock signal CK. The preset address A consists of 18 bits; the header information and the termination information consist of 3 bits each. Evidently other numbers are also possible. The address counter value becomes 0 each time when a 1 bit succeeds a 0 bit between the beginning of the header information and the end of the termination information. After the preset address with the header information and the termination information has been written into a shift register (see Fig. 4), recognition elements compare this header information and termination information with a given fixed pattern, for example 101 and 001; when correspondence is detected the preset address A between the header information and the termination information is input into the address counter: the address counter value becomes A.

Between two successive reset instructions to a preset address the reset signal must remain stable for some clock signals (depending on the header and termination patterns chosen) in order to prevent interference.

The normal reset function where the address counter is reset to the starting address of the memory can be maintained.

Other versions where only header information or only termination information is used operate analogously.

Another embodiment utilizes header information and/or termination information which ensures, after recognition by recognition elements, that a signal, is supplied which ensures that the normal reset function of the reset input is cancelled for the number of clock signals corresponding to the length of the preset address. After this time interval, the preset address is introduced into the address counter and the normal reset function of the reset input is restored.

It will be apparent that instead of the reset input an other signal input can be used as the serial address input means, for example an enable input or a data input.

Fig. 4 shows a diagram of hardware which is suitable for the preset mechanism: a shift register SR for writing the preset address V with the header information and termination information, II and Al, respectively, and recognition elements C1 and C2 for the header information and the termination information. When correspondence with a fixed pattern is detected, the remainder of the contents of the shift register, being the preset address V, is stored in the memory element ME of the address counter.

Fig. 5 is a breadboard representation of the reset mechanism. The blocks U001, U002 and U003 (Signetics 74164; see Philips Data Handbook Electronic Components and Materials, Integrated Circuits Book IC09N, 1986, TTL Logic Series Signetics) form the shift register in which the preset address with the header and termination information is stored. The blocks U004 and U005 are recognition elements which compare the termination information and the header information with a given pattern. When correspondence is detected, the memories U007 to U011 (Signetics 74161) are loaded with the preset address. The blocks U006a and U006b are inverters.

U001, U002, U003 and U007-U011 are connected to a clock signal. The input CLR' of U007-U011 and the input B of U001 are connected to a reset signal. The input CLR of U001-U003 is always high; input A is not used. In the case of a reset instruction, the preset address with the header information and the termination information is input in U001-U003 via the input B and the output QH.

The recognition element U004 checks the correspondence (input No. 3 is'high; Nos. 2 and 4 are low) of the termination information (QC, QB and QA in U001) with pattern "001" (BO, B1, B2 = B3). Output No. 6 is connected to input No. 3 of U005. This recognition element performs the same operation on the header information. If this information alsa corresponds to the predetermined pattern (in this case "101" in B0, B1, B2 = B3), the inputs LD of U007-U011 receive a signal and the preset address (the central 18 outputs of U001-U003, numbered 0-17) is loaded via the inputs A, B, C, D of 0007-U010 and C, D of U011.

Inputs ENT and ENP of U007 are high, output RCO of U007 is connected to ENT of U008 and ENP of U008-U011, RCO of U008 is connected to ENT of U009, and so on for the other memory elements. The 18 outputs QA, QB, QC, QD of U007-U010 and QC, QD of U011, containing the preset address, are connected to an internal memory address bus.

Fig. 6A shows the circuit diagram of an embodiment of a reproduction apparatus comprising a picture memory device. Input data line 601 is connected to serial memory 605 and to synchronization signal separator 607. The latter is connected to control unit 609 and the reproduction element 603. The control unit controls the serial memory, and the user control unit 611 feeds the control unit. The coupling and matching means are not described for the sake of simplicity.

Fig. 68 shows an application of preset addresses in the case of "picture in picture". Without preset addresses, the picture memory is each time completely addressed. Thanks to the improved accessibility offered by the use of preset addresses, part of the picture memory can be separately addressed without influencing the other contents. The whole operation is realized without additional connections.