Method for determining the control voltage of a voltage-controlled oscillator in a phase-locked loop.

In digital communication networks are clock signals - referred to as network clock signals - either separately or in the flow of information included in the individual network components, such as switching equipment, transmitted.. In the switching devices, such. As private branch exchanges, the received network clock signals are usually not used directly for clock control of the individual components of the switching device in case of loss of power clock signals the switching devices controlled would not or would occupy an undefined operating state. For this reason, the received network clock signals are fed to a phase locked loop is formed in the internal clock signals and transmitted to the individual components of a subscriber station.

In such a phase-locked loop following functions must be implemented:<ul><li>Generating internal clock pulses in an internal voltage controlled oscillator - referred to below as VCO-oscillator,</li><li>Adjusting the frequency of the network clock signals at the frequency of the internal clock signals, and</li><li>Controlling the internal oscillator VCO such that the phases of the network clock signals and internal clock signals coincide to <ul><li>1. be able to process the information transmitted by the communication network directly into the switching equipment and</li><li>2. To avoid a phase shift in one of the internal clock signals when mains clock signals.</li></ul></li></ul>

In addition to integrated circuits microprocessors are used with suitable peripherals in phase locked loops increasingly. A phase-locked loop, the one part comprising the above-described features and the other hand is equipped with a microprocessor system, is known from the publication "Proceedings of 1979 ISCAS", pages 804-805, known. This phase-locked loop consists of a digital phase comparator, a digitally controlled oscillator, control means and two divider means. In the first dividing the frequency of the supplied network clock signals is reduced. This changed in frequency network clock signals are then transmitted to a digital phase comparator. The phase comparison device is provided with a phase comparator and a counter. To the phase comparing means are additionally guided via the second dividing the internal, generated in a digitally controlled oscillator clock pulses. The divider means are so dimensioned that the frequency of the applied to the phase comparator network clock signals with the internal clock signals coincide approximately. In the phase comparator, the two clock signals are compared in terms of their phase position; the comparison result is supplied to the counter. In addition, the internal clock signals are transmitted to the counting input of the counter. Switches the phases of the two clock signals differ, internal clock signals are read and counted in the numerator. The counting result is passed to a realized by a microprocessor controller. In this control device, the phase deviations representing counts are determined, filtered, - low-pass filter - and passed as digital voltage values ​​to an externally disposed D / A converter. The output by the D / A converter analog output voltages control a VCO oscillator such that the generated by the VCO oscillator internal clock signals comply with network clock signals with respect to their phase position. VCO oscillator and D / A converter together form the digital controlled oscillator.

From said publication it appears that the individual system components of the control circuit, such as phase comparator, counter, the oscillator and the D / A converter, are not integrated in the control device. The document also contains no indication of how the individual hardware components, in particular the phase comparator can be realized. Furthermore, the phase locked loop can be adjusted only by changing or swapping of hardware components to different Netztakt- and VCO clock signal frequencies.

From a further document DE-A-27 35 053 a phase locked loop with a digital filter stage is known. The digital filter stage includes two counter stages in which in dependence on the pulse duration of formed in a phase detector the phase difference signals, the clock signals formed in a separate Zähltaktoszillator be paid. The stored counter readings of the first counting stage set here represents the controlled variable for the phase locked loop and a downstream digital / analog converter are supplied.

is based on the use of a microprocessor system in a phase locked loop, the object of the invention, this phase-locked loop in such a way that a simple adaptation to different Netztakt- and VCO clock signal frequencies is made possible and, if possible, all system components and their functions in the microprocessor system can be realized.

The object of the invention is achieved on the basis of the defined in the preamble of claim 1. The method by the characterizing features of claim 1.

The series circuit of the counter, the register and arithmetic means causes a very simple adaptation to different frequencies of the two clock signals because the components of the PLL are so dimensioned -eg counter and register Lange - that a phase difference between the two clock signals representative of different clock signal frequencies information can be determined and formed a drive voltage signal for the voltage controlled oscillator.

Another advantage of the series circuit of the counter, the register and the arithmetic means is in its very simple realizability in a microprocessor system - to see - counting, storing, simple arithmetic. This means that the phase locked loop can be implemented largely in a microprocessor system, since - as already discussed - the integration of low pass filter and PI filter functions per program is known in a microprocessor system.

The control accuracy of the PLL is essentially dependent on the frequency of the clock signals, the duration of the evaluation intervals and by the coordinated time constants or control speeds of the downstream filter and integrator from. A higher frequency of clock signals causes a higher resolution in determining the phase deviations. The higher the resolution - that is, the more accurate the determined phase deviation per evaluation period -, the more accurately the driving voltage are determined. It must be noted that the time constant of the low-pass filter in particular must be kept as small as possible. This is done such that the Auswerteintervalldauer and the time constants or control rates of the filters and integrators successive Tiered in function of the frequency of the clock signals are IMMT - see claim 2nd

According to an advantageous development of the embodiment of the invention as claimed in claim 2, the components of the PLL are controllable by a central control and monitored. This is especially true for such an implementation of the inventive method in a microprocessor system, in which all parts of the program advantageously coordinated by a central control, monitoring, and commission.

Particularly noteworthy are the various error detection and error reporting and display options that are possible due to the implementation of the programs. For example, the presence of the reference and clock signals can be monitored - see claim 4 cases coming from the oscillator clock signals, this failure may be reported or displayed. Further, for example, the creation of reference clock signals, their frequency of the phase locked loop is not synchronized, are detected and reported or displayed - see claim 5. Since the switching devices are usually connected via a plurality of the reference clock transmitting lines to the digital communication network, can after failure one of the reference clock signals are usually switched to redundant supplied reference clock signals.

The mentioned in claim 1 condition - the frequency of the time interval clock signals is lower than the frequency of clock signals - is advantageously such satisfied that the interval clock signals are obtained by means of a variable in their division ratio divider from the reference clock signals - see claim 6. This divider can be implemented as a hardware device either via the program in the microprocessor system, which contains the phase-locked loop, or. The type of implementation is essentially dependent on the frequency of the reference clock signals. At high frequencies, ie, higher than the maximum processing speed of the microprocessor system, a hardware implementation of the divider is required. If the frequency is below the maximum Verarbeitungsgeschwindkeit of the microprocessor system, as a hardware or software implementation is possible. However, the software version is preferable because a simple adaptation to different operating conditions of the PLL is to be made by changing the programs and they will integrate the set task, as many components of the phase-locked loop in a microprocessor system more effectively.

Varying the division ratio of the divider is particularly advantageous to carry out both a hardware and a software version from the central controller - that is, via the program input -, since a setting of the dividing ratio can be avoided by externally arranged mechanical switching means - see claim 4. a hardware implementation of the divider, for. example, as a frequency divider chain variable division factor can be adjusted via additional control connections between microprocessor system and frequency divider chain, the division factor and thus the division ratio.

A particularly advantageous implementation with respect to the divider is automatically detecting and adjusting the division ratio of the divider Here, the frequency of the phase locked loop supplied reference clock signals is detected and determines the division ratio by means of the central control device and the divider set accordingly -. See claim 8. The frequency the reference clock signals is measured by means of a likewise realized by frequency measuring program. The division ratio can hereby be determined so that each time interval clock signals of equal duration are present at the output of the divider. It may be determined by the division ratio also different time interval clock signals, but the Auswerteintervalldauer and the time constants or control speeds of the following low-pass and PI filters are then adjusted as necessary.

Due to the conception of the method and the thus achieved high adaptability to different clock signal frequencies, the insertion of additional components or functions of the phase control circuit used between the already existing is possible. Particularly advantageous this phase-locked loop can be used to form a Frequenzvervielfacheinrichtung or a high constant voltage controlled oscillator - see claim 9 - are used. Other means may be formed with a corresponding adjustment of the phase locked loop, for example, by inserting delay elements, additional analog components or additional filter functions.

As explained above, all components of the phase-locked loop with the exception of the voltage controlled oscillator in a microprocessor system can be realized - see claim 10th

The realization associated per program - see claim 11 - increases the adaptability of the PLL to the most diverse conditions. By this is meant, for example, an adaptation to different clock frequencies - even during operation on failure of the reference clock signals and switching to the reference clock signals of other frequency - to understand. Further, an adaptation to different oscillator control speeds -., For example, depending on the quality of the clock signals - and to different oscillators - as regards the Ansteuerspannungsbedingungen - possible. The adjustment can automatically during operation - this are additional detectors, such as a frequency measuring insert, - or manually -. For example, by loading a program - carried out by appropriate program changes.

According to a further advantageous embodiment of the invention according to claim 12 the microprocessor system can be realized by a one-chip microprocessor with built-in D / A converter. This is with regard to space requirement and cost, a particularly advantageous embodiment of the invention, since for forming the phase-locked loop the 1-chip microprocessor only the voltage controlled oscillator and optionally - if the reference clock or the oscillator clock signal frequency is much higher than the processing speed of the microprocessor - a in its division ratio variable divider must be assigned to the 1-chip microprocessor.

According to an advantageous embodiment of the invention as claimed in claim 13, the components of the PLL associated functions are mainly realized in a customer-specified integrated circuit. For this purpose, especially the integrated circuits are in ASIC (Application Specified Integrated Circuit) technology. These circuits contain a 1-chip microprocessor system and an area that can be occupied by specified by the client hardware. This circuit provides at high frequencies of the clock signals, the most advantageous realization of the invention, as those components of the phase-locked loop that process the clock signals in hardware, and those components of the phase-locked loop, to make the calculation of the phase deviation and the drive signals of the oscillator implemented in software are.

In the following implementation options and embodiments of the method and the inventive arrangement are explained with reference to block diagrams and a flow diagram.

They show:<dl id="dl0001"><dt>Fig. 1</dt><dd>a block diagram of a phase locked loop,</dd><dt>FIG. 2</dt><dd>a flow chart for explaining the block diagram of FIG. 1,</dd><dt>Fig. 3</dt><dd>a Frequenzvervielfacheinrichtung, or highly stable voltage controlled oscillator which are formed with the phase locked loop according to the invention.</dd></dl>

Fig. 1 shows the necessary components for explaining a phase locked loop. Assume that the phase-locked loop by a voltage controlled oscillator VCO - referred to below as oscillator -, a divider DIV and a 1-chip microprocessor MP is formed. The oscillator VCO for example, consists of an integrated crystal oscillator circuit and a pull-up circuit with which the oscillator frequency can be regulated within predetermined limits. Since the pull-up circuit is usually implemented by capacitance diodes, a frequency change is achieved by varying a voltage applied to a voltage input of the oscillator VCO SE DC voltage. This DC voltage is referred to below as drive voltage. The divider DIV comprises a group formed of integrated circuits divider chain at whose setting inputs EE the division factor or the division ratio is set. At an input E of the divider DIV network clock signals nts out. These network clock signals nts are derived for example from about transmitted a communication network clock information by suitable means.

In the 1-chip microprocessor MP, a counter Z, a register R, arithmetic means AE, a low-pass filter TP, a PI filter and PIF a D / A converter is connected in series. In terms of start-up, the control and monitoring of the components of the 1-chip microprocessor MP contains a central controller ZST. With this central control device ZST is the Einstellausgänge EA, which are connected to the setting inputs of the divider DIV EE, the division factor of the realized in the divider DIV divider chain - set - for example, by editing. An output A of the divider DIV is connected via a corresponding connection with a transfer input UE of the register R. An output A of the D / A converter D / A is performed on the voltage input SE of the oscillator VCO. At the output of the oscillator VCO are digital clocks are available, which are guided on the one hand as an internal clock signals its continued processing facilities and the other part is reached by a correspondingly arranged to connect to a counting input ZE of the counter Z. All facilities at the 1-chip microprocessor MP are through programs - adapted to the respective 1-chip microprocessor MP - realized. It is particularly advantageous to use a 1-chip microprocessor MP with integrated D / A converter D / A. This allows the user programming and development expenses are reduced.

In the following with the aid of the shown in Fig. 2 flowchart explains the individual functions of the components of the PLL and their interaction. After switching the phase locked loop - ie the supply voltage - is commissioning by using the central controller ZST of the phase locked loop. To this end, the central control device ZST controls all components of the PLL - in particular, the components in 1-chip microprocessor MP - in a defined initial state, such as register R to reset and enter arithmetic operation parameters, etc ...

After the recognition of each output from the oscillator VCO and guided to the counting input of the counter Z ZE its internal clock signal in the counter Z, the count of the counter Z is increased by one. This process, recognizing the internal clock signal its and increasing the count is repeated until the transfer input UE of the register R, an information exchange is established. Such information exchange is, for example, the transition from TTL Highzu TTL low voltage level. If now an information exchange of the time interval clock signals zts detected, the current in the counter Z present count is transferred to the R register and stored there. Subsequently, the detection of the internal clock signals ITS and the respective increase of the counter reading is continued by one. Simultaneously, the stored count to the arithmetic means AE is forwarded. In the arithmetic means AE following calculations are performed in the following order:<ul><li>Determining the evaluation interval, when the duration of time interval clock signal zts does not match the duration of the evaluation interval,</li><li>Determining the difference of the current count to the count of the previous evaluation interval,</li><li>Determine the current phase deviation by subtracting a set value from the determined meter reading difference (the setpoint represents the drive signal as the oscillator VCO at the rated frequency)</li><li>Summing all determined each evaluation interval phase deviations.</li></ul>

The Phasenabweichinformationen determined in the arithmetic means AE are performed in terms of rectifying a digital low pass filter TP and in terms of a voltage type and control speed adjustment via a digital PI filter PIF. The now present digital drive signals ds for the oscillator VCO are reacted in a D / A converter into analog control signals as and passed over a corresponding output of the 1-chip microprocessor MP system to the voltage input SE of the oscillator VCO.

Fig. 3 shows a device which can be used both as a frequency as well as high constant voltage-controlled oscillator. This device is equipped with a realized according to Fig. 1 and Fig. 2 phase-locked loop. Here, meet the arrangements and meet the functions realized in the 1-chip microprocessor system MP components or those described in FIG. 1 and FIG. 2. The time interval clock signals zts Fig. 1 are correspondingly by means of a divider DIV nts derived from the network clock signals and routed to the transfer input UE of the register R. Similarly, the oscillator VCO to the 1-chip microprocessor according to Fig. 1 connected MP and controlled by the latter. The main difference from Fig. 1 consists in inserting a frequency multiplier FV between the output of the oscillator VCO and the counter input ZE of the counter Z. The frequency FV is by a series connection of an additional phase comparator PVG, a low pass filter F and an additional voltage-controlled oscillator ZVO educated. Here is the output of the additional voltage-controlled and a higher frequency having oscillator ZVCO to the input ZE of the counter Z, the output A of the oscillator VCO to an input of the phase comparator PVG and the remaining input of the phase comparator PVG with the previously unused output A of the Z counter connected. This device is now to be used both as Frequenzvervielfacheinrichtung as a highly constant, voltage-controlled oscillator. When used as Frequenzvervielfacheinrichtung the clock signals are tsh higher or multiplied frequency at the output of the additional oscillator ZVCO available and can be performed, for example, as a clock signal to further processing means of a switching device. By increasing the frequency of the oscillator clock signals its - as already explained - the control accuracy of the phase locked loop is increased. This causes the oscillator VCO is controlled accurately and precisely. an already highly stable per se oscillator VCO is now additionally used, it is in terms of its frequency is also very precisely controlled, whereby the device as a highly accurate voltage controlled oscillator is used. Another, but not illustrated measure to increase the control accuracy of the PLL is to insert a term means in place of the frequency multiplier. Here, it can be determined at time intervals which are smaller than a time interval of a clock pulse ITS, the occurrence of a polarity change of time interval clock signals and reference clock signals zti. This additionally obtained information is also included in the calculation of the phase deviation. However, a prerequisite for applying this measure are low-noise power clock signals nts, which are present, for example, if these are transmitted by a first phase locked loop to a second phase locked loop, which is intended to replace loop.