Coding and decoding method and device for transmitting pictures via a network with a variable data flow.

p0001The present invention relates generally to the transmission of images, especially moving images such as television images. More particularly, the invention relates to a method for encoding rate reduction images and decoding images to increase rate, for transmitting a digital signal of moving images through a digital network variable rate such as an asynchronous digital network.

p0002In the article "The digital image and coding" published in "The echo of research", No. 126, fourth quarter of 1986, pages 21-36, J. Guichard and D. NASSE describe the state of the art in the field of processing the digital image to its rate reduction in transmission. The various existing encoding and decoding devices are designed to transmit images through constant rate transmission routes such, whether through an integrated digital network (ISDN). Generally, adequate capacity buffer memory is provided at the output of the encoding device to adapt the flow rate of the encoded image constant rate of the transmission channel allocated to the network. This buffer introduces a delay time in the transmission of frames between transmission and receiving equipment located at different ends of the array and respectively including an encoding device and a decoding device. This time delay in the transmission of images is particularly troublesome in the case of interactive image services, for example, such as video telephony at very low speed (64 kbit / s). The advantage of a variable speed network is that by offering the possibility of transmitting a variable data rate, it reduces the capacity of the buffer, or eliminate it, and so reduce the delay time transmission between the encoding device and the decoding device. However, the variable-speed networks such as asynchronous networks, have their flow traffic capacity calculated based on statistics. The fact that all subscribers do not use the same time the maximum flow allocated to them, is taken into account and the network is designed to sell a determined average total throughput statistically. This means that a subscriber can be temporarily denied a rate increase if the network is overloaded and where the requested rate exceeds a minimum guaranteed rate. The additional information resulting from the increase requested flow is in this case not routed to its final destination. For the transmission of encoded images, the non-delivery of the requested additional information is particularly disastrous because the algorithms of encoding and decoding are recursive. It is imperative that the information being processed by the coding device arrive at their destination in the decoding device.

p0003The invention aims to provide a coding and decoding method for the transmission of rate reduction images, without loss of information through a digital network with variable displacement.

p0004To this end, a method for encoding and decoding digital image signal according to the invention is as defined by claim 1.

p0005According to a first preferred embodiment, a coding device implementing the method according to the invention is as defined by claim 3.

p0006According to a second preferred embodiment, a decoding device implementing the method according to the invention is as defined by claim 11.

p0007The invention will be better understood on reading the following description of several preferred embodiments of the coding and decoding devices according to the invention with reference to the corresponding accompanying drawings in which:<ul><li>- Fig. 1 shows in the form of functional block diagram of a coding and decoding system comprising a coding device and a decoding device according to the invention connected via a digital transmission network variable rate;</li><li>- Fig. 2 is a detailed block diagram of a first preferred rélisation of a coding device according to the invention;</li><li>- Fig. 3 is a detailed block diagram of a second preferred embodiment of an encoding device according to the invention.</li></ul>

p0008In the following paragraphs of the description of coding and decoding devices of the invention, it is appealed to the state of the art in the field of digital encoding. Reference is useful to the cited article by J. Guichard and D. NASSE for additional information concerning in particular the technique of motion compensation and the use of transformed in the field of transmission of digital images to flow reduction .

p0009Referring to Fig. 1, a coding device 1 and a decoding device 2 according to the invention are connected through a digital transmission network with variable flow 3 as an asynchronous digital packet transmission network.

p0010The coding device 1 comprises a main encoder 11 performing an encoding function PC, a decoder 12 performing a decoding function CP⁻¹ reverse to the encoding function PC, a subtractor 13, and an auxiliary encoder 14 performing an encoding function IT.

p0011The main encoder 11 is preferably a known type encoder prediction loop. Input encoder 11 receives a digital video signal X consists of digital sample words resulting sampling a luminance signal or chrominance constant frequency. Output, the encoder 11 outputs a digital error signal quantized and coded e transmitted to the decoding apparatus 2 through a first transmission path with variable flow 31 of the network 3. The error signal e is the difference between the signal X and a product P prediction signal in the encoder 11 as a function of preceding values ​​of the signal X. the error signal e is inputted to the decoder 12 which outputs a digital video signal Y. the evaluated evaluated signal Y is applied to an inverse input "-" of the subtracter 13. a direct input "+" of the subtracter 13 receives the signal X. the subtracter 13 outputs a digital signal z error representing the difference between the signals X and Y. the signal z is input auxiliary encoder 14 which quantifies and code into a digital error signal quantized and encoded corresponding e_at. The signal e_at is transmitted to the decoding device 2 through a second path of variable rate transmission 32 of the network 3.

p0012The auxiliary encoder 14 is preferably a complementary structure to the main encoder 11, while achieving coding function of the same family as the primary encoder 11. The encoder 14 may be without an encoder prediction loop, unlike the main coder 11, and carries such a type of coding function PCM or DPCM (differential PCM) as the primary encoder performs encoding function for example of the discrete cosine transform DCT, or vice versa.

p0013When the network 3 is able to flow through the path 31, all of the information rate that can provide the main encoder 11, the encoder 11 operates in a full resolution mode, and the evaluated signal Y and representing a evaluation of the information contained in the video signal X actually transmitted by the coded signal e through the track 31, is little different from the signal X. the error signal z = X - Y is then close to zero. The auxiliary encoder 14 is inactive and no image information is flowed through the channel 32. When the network 3 is not able to flow through the path 31, the entire flow of information that could be provided the primary encoder 11, for example for reasons of congestion of the network 3, the encoder 11 is located in an operating mode to reduced resolution, for example by increasing the quantization intervals of the signal X and thus reducing the number of levels of quantization of the signal X, and the evaluated signal Y becomes substantially different from the signal X. the error signal z = X - Y whereas a non-zero value representing a precision supplement on the X signal and not transmitted through the channel 31 . the auxiliary encoder delivers 14 is active and the path 32 a signal e_at nonzero. Through the channel 32 is thus transmitted an additional information concerning the X signal to the decoding device 2 is able to recover the signal X with the required precision. In practice it is noted that a buffer circuit included in the main encoder 99 receives a signaling SIG brand home exchange network in the central 3 to accurate flow rate that can be passed in the way 31.

p0014The decoding device 2 includes a main decoder 21 performing the inverse decoding function to CP⁻¹ CP coding function performed by the encoder 11, and an adder 23.

p0015The decoders 21 and 22 respectively receive as input signals e and e_at transmitted in the channels 31 and 32. The decoders 21 and 22 respectively reconstitute the signals Y_at and z_at from e and e signals_at received. The signals Y_at and z_at are respectively applied to first and second inputs of adder 23. The adder 23 outputs a recovered digital video signal X_at corresponding to the signal X.

p0016The coding device of the block diagram according to the invention described with reference to Fig. 1 is a basic block diagram in which the main encoder 11 and decoder 12 are shown as separate functional elements. In fact, in the known encoders of predictive type, the decoder is included in the encoder prediction loop such that the Y signal can be taken directly in a particular connection point of the main encoder 11. The complexity of a device encoding according to the invention is substantially reduced because of this characteristic.

p0017Referring to Fig. 2, a first preferred embodiment of the encoding device 1 of the invention comprises a main encoder 11a having a prediction loop constituting a decoder 12a, a subtractor 13a, and an auxiliary encoder 14a.

p0018The main encoder 11a is a type of encoder transformed loop prediction and motion compensation. It comprises a 111a subtractor, a circuit for computing transform 112a, a quantizer adjustable quantization levels 113a, a coding circuit 114 a variable flow rate, a 115 a buffer circuit, a predicting loop / decoder 12a, and a circuit motion compensation 116a.

p0019The subtracter 111a receives a direct input "+" the incoming digital video signal X and an inverse input "-" P a digital signal resulting from a prediction of the value of the signal X, and provides a digital error signal E = XP. The signal E is applied at input of 112a transform computation circuit which performs on the signal E a reversible transformation, for example a discrete cosine transformation DCT, to represent the signal E into a space other than the space of representation X signal, ensuring better decorrelation between the different image points. The E signal after processing, is provided to quantizer 113a which produces a digital error signal transformed and quantized signal E. el corresponding to quantization levels in the quantizer 113a are adjusted by a QC control signal supplied by the circuit buffer 115a to a levels adjustment input of quantizer 113a. The signal el is inputted to the variable rate coding circuit 114a and the input of a dequantizer 121a included in the prediction loop / decoder 12a. The rate coding circuit 114a code each digital sample of the el variable signal into a corresponding digital word having a number of bits dependent on the sample value. The 114 circuit performs a rate reduction by optimizing to a minimum the number of bits needed to represent each sample. The 114 circuit provides digital error signal quantized and coded e. The signal e is applied to a first input 115a of the buffer circuit. A second input buffer circuit 115a receives a VD digital signal carrying digital words representative of image block motion vectors. The samples and digital words e and VD signals are loaded into the buffer memory circuit 115a and transmitted in the 31 way of the variable speed network 3 (Fig. 1) in chronological order of arrival. The circuit 115a buffer comprises a buffer memory, which is similar to a buffer included in a conventional encoder for constant bit rate transmission network, but has a much smaller capacity. The system 115a is operable to perform a rate adaptation between the flow rate of the signal e and the instantaneous flow of the channel 31 indicated by the central home exchange, these flows corresponding to the write and read of the buffer memory clocks . The buffer memory 115a controls the adjustment of the quantization levels in the quantizer 113a in function of its filling level, via the CQ command siganl. The number of quantization levels in the quantizer 113a is smaller when the number of occupied cells 115a in the buffer is large, that is to say the instantaneous flow rate in the channel 32 is less than the flow signal e.

p0020The predicting loop / decoder 12a includes, besides the dequantizer 121a, 122a of a computing inverse transform circuit, an adder 123a, a circuit 124a image memory, and a digital filter 125a.

p0021The dequantizer 121a and 122a inverse transform calculating circuit are cascaded in order to reconstruct from the error signal el transformed and quantized, a corresponding digital error signal Ea shown in the same space as the signal X and having a rate equal to that of the signal X. the signal Ea is applied to a first input of the adder 123a. A second input of summer 123a receives the prediction signal P. An output of adder 123 produces the digital video signal evaluated Y = P + Ea. The Y signal is applied to a 1241a input of the circuit to process image 124a and an inverse input "-" of the subtracter 13a receiving a direct input "+" the input signal X. The image memory circuit 124a includes an image memory which stores the previous value of the signal Y to a same image point value which is processed by the motion compensation circuit 116a and engages in the prediction of the value of the signal X for said point picture. The prediction signal P has a rate equal to that of the signal X and is applied by an output 1242a 124a picture memorizing circuit 125a through the filter, to the second input of the adder 123a and the inverting input of the subtractor 111a.

p0022116a the motion compensation circuit comprises a central processing unit, consisting for example of a microprocessor, processing in accordance with a firmware the different values ​​of the evaluated signal Y stored in the image memory 124a of the circuit and the different values the signal X in order to calculate the block motion vectors respectively for a plurality of predetermined image blocks. Each vector represents the motion of a corresponding block of an incoming image carried by the signal X with respect to the position of the same block in the previous image. Such interframe prediction can be optionally combined with a infraimage prediction between blocks of the same image. 116a the motion compensation circuit receives the incoming video signal X to a 1161A entry and the stored values ​​of the Y signal read from the image memory to an input 1162A. The digital words representative VD motion vectors are delivered by a 1163a output 116a of the circuit. Based on the calculated motion vectors, the motion 116a compensation circuit optionally modifies the values ​​of the signal Y stored in the buffer circuit 124a in order to refine the prediction of the signal X. A 1164A connection between the motion compensation circuit 116a and the image memory circuit 124a is provided to write the changed values ​​of the Y signal in the image memory.

p0023The auxiliary encoder 14a does not include a prediction loop. It comprises a calculating circuit 141a transform, a quantizer 142a, and a coding circuit 143a variable flow. The 141a circuit, the quantizer 142a and 143a circuit are connected in cascade to produce from the digital error signal z = XY provides the subtractor 13a, the digital error signal e_at transmitted in the channel 32. The transform 141a computing circuit receives as input the signal z; the coding circuit 143a variable speed outputs the signal e_at; the quantizer 142a is placed between the circuit 141a and 143a. The circuits 141a and 143a are similar circuits to circuits 112a and 114a of the main coder 11a. The quantizer 142a is fixed quantization levels 113a quantifier unlike the main encoder 11a. The coding circuit 143a provides a variable flow of information flow that varies without exceeding a guaranteed minimum flow in the channel 32 by the variable speed network 3.

p0024The detailed structure of the decoding device 2 adapted to the coding apparatus described with reference to Fig. 2 can easily be deduced by the skilled person from the above description of the coding device and the general structure of the decoding device 2 described with reference to Fig. 1. The main decoder includes a buffer memory circuit followed by a decoding circuit that complements the variable rate coding circuit 114a shown in FIG. 2 and a prediction loop such as the predicting loop / decoder 12a, shown in Fig.2. A motion compensation circuit receiving the digital words VD collected in the buffer of the main decoder and processing the stored values ​​and read from the image memory of the prediction loop based on the received VD words must also be provided in the decoder main. The auxiliary decoder comprises a decoding circuit that complements the encoding circuit 143a variable flow shown in Fig. 2 followed by a de-quantizer and an inverse transform calculation circuit.

p0025Referring to Fig. 3, a second preferred embodiment in a simplified structure of a coding device 1 according to the invention comprises a circuit for computing transform 10 placed at the input of a main encoder 11b which is of type transform and prediction loop and which includes a prediction loop / decoder 12b, 13b and 14b subtracting auxiliary encoder.

p0026The main encoder 11b and the encoder 14b auxiliary have simpler structures than the encoders 11a and 14a shown in Fig. 2 that the encoder 11b does not perform motion compensation.

p0027The main encoder 11b comprises, in addition to the prediction loop / decoder 12b, a subtractor 111b, a quantizer 113b, a coding circuit 114b variable flow, and a circuit 115b buffer. The prediction / 12b decoder loop comprises a dequantizer 121b, 123b and a summing circuit to circuit 124b image.

p0028Unlike the encoder 11a shown in Fig. 2, wherein the transform 112a computation circuit is placed at the output of the subtractor 111, the transform computation circuit 10 is connected to the direct input "+" of the subtracter 111b and receives as input the incoming digital video signal X to produce outputting a digital transformed video signal Xb. The subtracter 111b receives the transformed signal Xb to the direct input "+" and a digital prediction signal Pb to the inverse input "-". Pb signal results from a prediction of the transformed signal Xb. The subtracter 111b applies to the input of quantizer 113b a digital error signal transformed Eb = Xb-Pb. The quantizer 113b is fixed quantization levels; it outputs the digital error signal transformed and quantized el corresponding to the signal Eb. The signal el is inputted from the encoding circuit 114b and the variable flow dequantizer 121b included in the prediction loop / decoder 12b. 114b the circuit is similar to variable rate coding circuit 114a shown in FIG. 2; it outputs the digital error signal e corresponding to el signal and transmitted in the first channel 31 of the network 3 through the buffer memory circuit 115b.

p0029In predicting loop / decoder 12b, the dequantizer 121b into receiving el signal outputs a digital error signal Eab reconstructed transformed from el signal. Adder 123b receives the first and second inputs the signals Eab and Pb, respectively, outputs a digital video signal evaluated Yb = Pb + Eab. The Yb signal is input from the image 124b memory circuit and inverse input "-" of the subtracter 13b whose direct input "+" receives the signal Xb. The image memory circuit 124b outputs the prediction signal Pb.

p003014b auxiliary encoder 142b includes a quantizer and a coding circuit 143b similar to the variable flow circuits 142a and 143a shown in Fig. 2. The quantizer 142b receives as input a digital signal converted error z_b= Xb-Yb produced by the subtracter 13b. The quantizer 142b is followed by the coding circuit 143b variable rate which delivers the digital error signal e_at transmitted in the second path 32 of the network 3.

p0031The detailed structure of the decoding device 2 adapted to the coding apparatus shown in FIG. 3, as for the coding apparatus shown in FIG. 2, can easily be deduced by the skilled person. The main decoder includes a buffer memory circuit followed by a decoding circuit that complements the encoding circuit 114b to variable flow shown in Fig. 3 and a prediction loop such as the predicting loop / decoder 12b shown in Fig. 3. The auxiliary decoder comprises a decoding circuit that complements the encoding circuit 143b to variable flow shown in Fig. 3 followed by a dequantizer. An inverse transform calculation circuit is provided at the output of adder 23 (Fig. 1) in the decoding device 2.