Antenna selection control circuit.

Background Art

Radio receivers that make use of antenna selection diversity are known in the art. In general, such a receiver makes use of a default antenna, and only makes use of the alternate antenna when the signal being received by the default antenna diminishes below an acceptable threshold (the threshold may either be a preselected constant or a value that fluctuates somewhat and represents, for example, an average value of the default antenna received signal). The criteria for measuring antenna performance may be, for example, a received signal strength indicator (RSSI).

Time division multiplexed (TDM) RF communications systems are also known in the art. Such systems divide information to be broadcast into packets, which packets are then broadcast in predetermined time slots. A typical TDM system establishes a short time frame (for example, a few milliseconds) made up of two or more time slots, wherein the basic time frame format repeats continuously. A typical receiver will monitor, decode, and process further as appropriate information contained in time slots of interest, and receive but ignore information contained in other time slots.

A need exists to accommodate antenna selection diversity in a TDM RF receiver.

Summary of the Invention

This invention includes circuitry for developing signals related to received signal quality, such as signal strength, for at least two antennas associated with at least one of the antennas during a TDM time slot not of interest. The circuit then compares these developed signals to identify which of the antennas receives the stronger signal, and causes the receiver to use that identified antenna.

In one embodiment, all of the antennas associated with the receiver are sampled during a time slot not of interest, such that the antenna selection occurs prior to receipt of a time slot of interest.

In another embodiment, the circuitry continues to monitor received signal strength for the selected antenna during the time slot of interest, such that if the received signal strength diminishes unacceptably, the receiver can be caused to utilize an alternative antenna during the time slot of interest.

Brief Description of the Drawings

<ul id="ul0001" list-style="none"><li>Fig. 1 comprises a schematic diagram of a first embodiment of the invention;</li><li>Fig. 2 comprises a timing diagram associated with the first embodiment;</li><li>Fig. 3 comprises a schematic diagram of a second embodiment of the invention;</li><li>Fig. 4 comprises a timing diagram associated with the second embodiment; and</li><li>Fig. 5 comprises a schematic diagram of additional circuitry that can be utilized with either embodiment.</li></ul>

Best Mode For Carrying Out the Invention

Referring now to Fig. 1, the first embodiment can be seen as depicted generally by the numeral 10. This first embodiment includes generally a sample and hold circuit (11), a comparator (12), and an antenna switch control circuit (13).

The sample and hold circuit (11) includes a sample and hold device (14) such as an AD585. The sample and hold control port connects to receive an appropriate sample and hold control signal (S/not H) as described in more detail below. The signal input port connects to receive an RSSI signal. The output ports connect to the comparator (12) as described below.

The comparator (12) can be comprised of a device such as the MC3302 (16). The non-inverting input to this device connects to receive the output of the sample and hold device (14). The inverting input connects to receive an RSSI signal. The output of the device (16) connects to a 1K ohm pull-up resistor (17) and also to one input of a first exclusive OR gate (18) that constitutes one input to the antenna switch control circuit (13).

The output of the first exclusive OR gate (18) connects to the data port of a flip-flop (19). The not Q output of the flip-flop (19) connects to the remaining input of the first exclusive OR gate (18). The Q output of the flip-flop (19) connects to one input of a second exclusive OR gate (21), the remaining input of which connects to the output of a third exclusive OR gate (22). One input of the latter connects to a positive 5 volt source and the remaining input connects to receive the S/not H signal, which produces an inverted S/not H signal, which signal also connects to the clock port of the flip-flop (19). The output of the second exclusive OR gate (21) constitutes the antenna switch output of the antenna switch control circuit (13).

Referring to Fig. 2a, a series of TDM time slots A and B can be seen, wherein slot A contains information of interest and slot B contains information not of interest to the receiver in question. Fig. 2b depicts the S/not H signal that would correspond to this arrangement. In particular, the S/not H signal as used in the first embodiment depicted in Fig. 1 would cause the sample and hold circuit (11) to sample RSSI for an antenna during a time slot containing information of interest. A comparison could then be carried out during time slots having information not of interest with respect to the antenna actually being used. A determination could then be made as to which antenna should be used for subsequent time slots containing information of interest.

Referring now to Fig. 3, an alternative embodiment can be seen as depicted generally by the numeral 30. This embodiment includes a sample and hold circuit (11) and a comparator (12) essentially as described above. Therefore, these particular sections will not be described again.

The second embodiment (30) also includes a MC14013 flip-flop (31) having its data port connected to receive a CS2 signal as described below in more detail. The clock port connects to receive an appropriate clock signal as well understood in the art. The clock rate should of course be chosen to accommodate the time slot and frame length durations of the TDM system in question. The Q output of the flip-flop (31), which provides a delayed version of the CS2 signal, connects to the S/not H port of the sample and hold circuit (11). The not Q output of the flip-flop (31) connects to the antenna switch control circuit (32) as described below in more detail.

The antenna switch control circuit (32) includes a first exclusive OR gate (33) having one input connected to receive the output of the comparator (12) and another connected to receive the not Q output of a data type flip-flop (34) associated therewith. The flip-flop (34) has its data port connected to receive the output of the first exclusive OR gate (33). The clock port of this flip-flop (34) connects to receive a CS1 signal as described below in more detail. This CS1 signal is also provided to one input of a second exclusive OR gate (36), the remaining input of which connects to a positive 5 volt source. The output of this exclusive OR gate (36) connects to one input of an AND gate (37), the remaining input of which connects to the not Q output of the first flip-flop (31) referred to above. The output of this AND gate (37) and the Q output of the second flip-flop (34) connect to both inputs of a third exclusive OR gate (38), the output of which connects to an appropriate antenna switch as well understood in the art.

Referring now to Fig. 4a, a series of TDM time slots A and B can again be seen. An appropriate CS1 and CS2 control signal to be used in the second embodiment (30) are depicted in Figs. 4b and c. An S/not H control signal that results through provision of these control signals, in conjunction with an appropriate clock signal, is depicted in Fig. 4d.

By controlling the timing of the second embodiment (30) as depicted in Fig. 4, the second embodiment (30) will function to sample and compare RSSI values for both antennas during time slots that are not of interest, such that the decision regarding antenna selection can be made prior to receipt of a time slot of interest. With this approach, an improvement can be realized in a Rayleigh fading field with higher Doppler frequency where the time between antenna samples and the desired information slot is short.

Referring now to Fig. 5, an additional circuit which can be used in combination with either embodiment (10 or 30) can be seen as depicted generally by the numeral 50. This circuit (50) functions to allow the antenna in use during a time slot of interest to be monitored and compared against a historically determined value of antenna performance. If instantaneous antenna performance degrades sufficiently, this circuit (50) causes the receiver to switch antennas.

The circuit (50) depicted includes a reference signal unit (51), a comparator (52), and an antenna switch control circuit (53).

The reference signal circuit (51) receives an RSSI signal for the antenna in use and, through use of the operational amplifiers (54 and 55) and the <u style="single">10K ohm</u> resistors and capacitor depicted, develops an average value for the RSSI signal with respect to time. The variable resistor (50) connects to an appropriate 5 volt source, and serves to set the level below mean at which the circuit forces a switch to the alternative antenna. The output of this reference signal unit (51) connects to the noninverting input of a comparator (52), the inverting input of which connects to receive an instantaneous value representative of RSSI. The output of the comparator then connects to a 1K ohm pull-up resistor (56) and to one input of an AND gate (57) that constitutes the input to the antenna switch control circuit (53). The remaining input to the AND gate (57) connects to receive a window trigger signal, which essentially comprises the S/not H signal wherein the leading edge is delayed by 0.5 milliseconds to accommodate transients and to allow the circuitry to reach steady state conditions (when using the embodiment depicted in Fig. 3, the window trigger signal can be comprised of the CS1 signal to achieve substantially the same effect). The output of the AND gate (57) connects to the set port of a flip-flop (58), the Q output of which connects to one input of an exclusive OR gate (59), the remaining input of which connects to the antenna switch output of the antenna switch control circuit in either embodiment (13 or 32). The output of this exclusive OR gate (59) functions to provide a signal that can cause an appropriate antenna switch to switch antennas.

The reset port of the flip-flop (58) referred to above also connects to an appropriate reset circuit that includes a transistor (61) having a base connected through an 18K ohm resistor (62) to receive the window trigger signal referred to above. The emitter of this transistor connects to ground and the collector connects both to the reset port of the flip-flop (58) and through a 4.7K ohm resistor (63) to a positive 5 volt source. The reset signal forces the antenna switch to be controlled by the antenna switch control circuit (13 or 32) when the system receives a slot not of interest. When receiving the slot of interest, the antenna can be forced to switch to the alternative antenna by the flip-flop (58) based on the comparator (52).