Removing resist layers.

0001The present invention relates to a method of fabricating a semiconductor device and is particularly concerned with the removal of a resist layer which has a high dose of ions implanted therein, formed on a substrate in the course of fabrication of a semiconductor device.

0002Generally, in an ion implantation process used in the course of fabrication of a semiconductor device on a substrate, a resist layer made of resin such as novolak resin is used as a mask for masking designated portions of the substrate which are not to be ion-­implanted, and the resist layer must be removed after the ion implantation process is finished, for proceeding to a next semiconductor device fabrication step. For removing the resist layer, an oxygen plasma etching method performed with no sputtering action, a downstream ashing method carried out in a reactive gas of hydrogen, or a wet stripping method have been used. However, when high doses of ions, for example more than 1 x 10¹⁴/cm², are implanted, high doses of ions are also implanted into the resist layer, so that designated regions of the upper surface of the resist layer become physically and chemically rigid. This phenomenon is called "carbonization" and the designated region is called a "carbonized region". This carbonization of the resist layer is discussed in a paper entitled "Study on Ashing Process for Removal of Ion Implanted Resist Layer" by five authors including Shuzo Fujimura and Junichi Konno who are inventors of the present invention, in proceedings of the "DRY PROCESS" symposium, published by Electronics and Dielectrics and Insulation Divisions of The Electrochemical Society, in 1987.

0003Because the resist layer is carbonized, it is difficult to remove by the methods mentioned above without damaging the substrate under the resist layer. That is, if a reactive etching method such as an oxygen plasma etching method is used for removing the resist layer with a strong sputtering action, for example, by using a parallel plate plasma etching appratus, the resist layer can be ashed even though the resist layer has been carbonized. However, when such a strong sputtering is performed on the resist layer, the following problems occur:- one problem is that a surface of the substrate which was beneath the resist layer is contaminated by residues such as phosphorus pentaoxide (P₂O₅) and heavy metal compounds produced from the resist layer during the strong sputtering; another problem is that lattice defects are generated in a surface region of the substrate by the strong sputtering. Therefore, after removing the resist layer, residues remaining on the substrate must be selectively etched and the etched substrate must be annealed for reforming (removing) the lattice defects. Moreover, there is a further problem in that a designated portion, such as a gate oxide layer of an MOS transistor, previously fabricated in a surface region of the substrate under the resist layer, can be broken or damaged because of stored charge produced on the surface of the substrate during the plasma sputtering. If this occurs, there is no way to rectify the damage.

0004Thus, when high doses of ions were implanted, removal of the resist layer involves the performance of many extra processes and sometimes a previously fabricated portion of the substrate under the resist layer is damaged. The consequences are:- increased semiconductor device cost; decreased semiconductor device yield rate; decreased reliability; and restricted freedom for designing a semiconductor device.

0005According to the present invention there is provided a method of removing a resist layer formed on a substrate, the resist layer including an ion-­implanted region, extending into the resist layer from an upper surface of the resist layer, into which a high dose of ions has been implanted, the method comprising:- removing a first region of the resist layer, including the said ion-implanted region, by a first plasma etching process, using hydrogen at a reactive gas, leaving a second region of the resist layer in place; and removing the second region by a second etching process performed without using a plasma.

0006An embodiment of the present invention can provide for the removal of a resist layer, into which a high dose of ions has been implanted, formed on a substrate being processed to form a semiconductor device, with simple removal processes.

0007An embodiment of the present invention can provide for removal of the resist layer without damage to the substrate.

0008Use of an embodiment of the present invention can lead to a decrease in the cost of a semiconductor device fabricated using processes involving implanting high doses of ions.

0009Use of an embodiment of the present invention can provide increased reliability of semiconductor devices fabricated using processes involving implanting high doses of ions.

0010Use of an embodiment of the present invention can provide for increased yield rate of products using semiconductor devices fabricated using processes involving implanting high doses of ions.

0011In an embodiment of the present invention, a resist layer is removed in the following two steps, the resist layer being divided into two regions with an upper region including a carbonized region and a lower region attached to a substrate: a step for removing the upper region by a plasma etching method carried out with a mixing gas of nitrogen and an active gas of hydrogen and a step for removing the lower region by using a previously proposed method such as a downstream sputtering method or wet stripping method.

0012In other embodiments other inert gases may be used as mixing gases.

0013Applying the plasma etching method to the upper region with the mixing gas, bonds tightly bounding the implant with carbon in the carbonized region, for example, phosphorus-carbon (P-C) bonds can be broken and an implant hydride produced, and the implant hydride is volatilized at room temperature. In the above steps, the volatilization is important for providing that almost no residue remains on the substrate after removal of the resist layer, and furthermore, the fact that the volatilization can be performed at room temperature is effective to make simple the processes involved in removal and arising after removal of the resist. Applying an embodiment of the present invention, semiconductor device cost can be decreased, yield rate can be increased, reliability of the products of the semiconductor device can be increased, and a semiconductor device can be designed without considering the problems linked with high-dose ion implantation.

0014Reference is made, by way of example, to the accompanying drawings, in which:- <ul id="ul0001" list-style="none"><li>Fig. 1(a) is a partial cross-sectional view of a silicon substrate having oxide films formed in a surface region thereof, on which a resist layer is coated, illustrating a selective phosphorus ion implantation;</li><li>Fig. 1(b) is a partial cross-sectional view of the silicon substrate coated with the resist layer, illustrating a carbonized region formed in a surface region of the resist layer due to high-dose implantation of phosphorus ions into the resist layer;</li><li>Fig. 1(c) is a partial cross-sectional view of the silicon subsrate illustrating etching of an upper region, including the carbonized region, of the resist layer by a plasma etching method;</li><li>Fig. 1(d) is a partial cross-sectional view of the silicon substrate illustrating removal of a lower region of the resist layer by a downstream ashing method; and</li><li>Fig. 2 is a schematic diagram of an etching apparatus used in an ashing process, embodying the present invention, for the resist layer.</li></ul>

0015An embodiment of the present invention will be described with reference to Figs. 1(a) to 1(d) in which the cross-sectional views of a semi-processed semiconductor device illustrate successive steps in a method embodying the present invention.

0016In Fig. 1(a), photoresist (for example, HPR 204; FUJI-HUNT) mainly made of novolak resin, is coated on a substrate 1 by a spinner so as to form a resist layer 2 of 2 µm thickness, and the resist layer is patterned by photolithography for forming an opening 6 for implantation of a high dose of ions into a silicon substrate 5. In this embodiment, the substrate 1 consists of a silicon substrate 5 and oxide layers 3 formed in surface regions of the silicon substrate 5.

0017In Fig. 1(b), high doses, 1 x 10¹⁶ cm⁻² for instance, of phosphorus ions are implanted into the silicon substrate 5 at an energy of 70 keV (kilo electron volts), to form phosphorus implanted region 4 in the silicon substrate 5 at the opening 6 in the resist layer 2. Only one opening 6 is shown in Figs. 1(a) to 1(d) and only the implanted region 4 is indicated in Figs. 1(b) to 1(d), at the opening 6. Of course, in practice, there may be a plurality of openings and implanted regions. When high-dose phosphorus ions are thus implanted into the silicon substrate 5, high-dose phosphorus ions are also implanted into the resist layer 2, which results in the production of a carbonized region 2a in the layer, leaving an uncarbonized region 2b, as shown in Fig. 1(b). In this case, the thickness of the carbonized region 2a is from 0.2 µm to 0.3 µm. This carbonized region 2a is responsible for problems as mentioned above.

0018Next, the resist layer 2 is removed, and in this embodiment of the present invention, this removal is performed in two steps respectively for removing the carbonized region 2a and the uncarbonized region 2b, using a resist ashing apparatus 50. Fig. 2 is a schematic illustration of the resist ashing apparatus 50. As shown in Fig. 2, the resist ashing apparatus 50 consists of a cathode-coupled parallel plate plasma ashing chamber 11, which will be called simply a "plasma ashing chamber 11" hereinafter, for removing the carbonized region 2a, a downstream ashing chamber 21 for removing the uncarbonized region 2b, and load locks or blocks 30, 31 and 32. The load lock 30 is for introducing a wafer to the plasma ashing chamber 11 from outside the resist ashing apparatus 50, the load lock 32 is for transferring the wafer from the plasma ashing chamber 11 to the downstream ashing chamber 21, and the load lock 31 is for outputting the wafer from the downstream ashing chamber 21 to the outside. Here, a wafer is a member such as a silicon wafer divided into a plurality of semi-processed devices on each of which a resist layer is formed.

0019In the plasma ashing chamber 11, plasma is confined between a power electrode 15 and a table 14 on which a wafer 100 is placed; wherein, on the wafer 100, a plurality of semi-processed devices as seen in Fig. 1(b) are provided. The temperature of the wafer 100 can be controlled by a heater and a cooler, not shown in Fig. 2, attached to the table 14. RF (radio frequency) power at 13.56 MHz is delivered to the plasma from a power source 16. The temperature of the wafer 100 should be maintained lower than a softening point (about 120°C) of the resist layer 2. If the temperature were to exceed the softening point (for a prolonged period), the uncarbonized region 2b would be softened during the etching of the carbonized region 2a, so that the carbonized region 2a could suffer cracking and be torn or divided into many pieces, with some pieces sunk into the softened uncarbonized region 2b. As a result, residues obtained from plasma etching of the carbonized region 2a would be left at the bottom of the uncarbonized region 2b adhering to the upper surface of the substrate 1, unless the residues are etched off by the plasma. If plasma etching were applied to the uncarbonized region 2b, the same problems as have previously occurred would arise.

0020A mixed gas composed of 97% nitrogen and 3% hydrogen in volume is used in the plasma ashing chamber 11 as a reactive gas, with, for instance, a pressure of 0.5 Torr. The mixed gas is introduced into the plasma ashing chamber 11 through an inlet 12 and exhausted from the plasma ashing chamber 11 through an outlet 13, using an evacuating system Vac. 1 not shown in Fig. 2.

0021When plasma etching is performed on resist layer 2 formed on (the semi-processed devices on) the wafer 100, in other words, formed on substrate 1, with the gas in the plasma ashing chamber 11, an upper region, for example 1 µm thick, of the resist layer 2 is etched off, so that the carbonized region 2a is completely etched, leaving a lower region 2c of the resist layer 2, as shown in Fig. 1(c).

0022After removing the carbonized region 2a, the lower region 2c is removed in the next step. In this next step, the wafer 100 on the table 14 in the plasma ashing chamber 11 is transferred to a table 24 in the downstream ashing chamber 21 through the load block 32 without breaking the vacuum in the apparatus, and the lower region 2c is removed in the downstream ashing chamber 21, applying a downstream ashing method.

0023In the downstream ashing chamber 21, a microwave plasma is generated by a magnetron source 25 oscillating RF at 2.45 GHz and confined in a space between a window 26 and a shower head 27. Meanwhile, a mixed gas composed of 97% (in volume) oxygen and 3% tetrafluoromethane is introduced through an inlet 22 and exhausted to an evacuating system Vac. 2, not shown in Fig. 2, through an outlet 23. Consequently, the wafer 100 is etched in a space between the shower head 27 and the table 24 filled with oxygen and other gas species being neutral in atomic state. This kind of etching is called downstream ashing, and by this etching the lower region 2c is completely removed as shown in Fig. 1(d). The power required to perform the downstream ashing is lower, compared to that of the plasma ashing performed in the chamber 11, so that problems do not arise in respect of the substrate 1 as they have previously done.

0024Other methods can be used for etching the lower region 2c, for example a wet stripping method. However, when the wet stripping method is used, substrate 1 (wafer 100) must be taken out of chamber 11, breaking the vacuum, after the plasma etching of the upper region 2a.

0025Using a method embodying the present invention for removing resist layer 2, almost no residue remains on the surface of the substrate 1. For evaluating how satisfactorily the resist layer 2 is removed, a particle counter for counting the number of the residues, such as phosphorus oxides, heavy metals and carbon compounds, remaining on the surface of the subsrate 1 is employed. Counting only residues having diameters larger than 100 µm, the number of residues present after use of an embodiment of this invention is 300 to 350 per 4-inch wafer for instance. This number is very small, compared with residue numbers previously achieved. That is, when an oxygen plasma etching method is used for removing the resist layer 2, the residue number is about 8000 per 4-inch wafer. It is clear that the present invention can provide for remarkable improvement in relation to the removal of an ion-implanted resist layer.

0026Although an ashing process in accordance with an embodiment of the present invention can generate a few lattice defects, the lattice defects can be eliminated by annealing the substrate 1 at a temperature higher than 400°C.

0027An embodiment of the present invention provides a method for removing a resist layer, in which a high dose of ions has been implanted, by etching in two steps:- in a first step, a carbonized region produced in the resist layer due to the high dose ion implantation is etched by applying plasma using hydrogen as a reactive gas at a temperature lower than a softening point of the resist layer; and in the second step, a lower region of the resist layer, left after the etching of the first step, is etched by a method such as a downstream ashing method or a wet stripping method.