Apparatus for data reception.

The invention relates to an apparatus for receiving data via radio waves, in particular together with other information transmitted, wherein the data is represented by binary output signals of a threshold value that is assigned to a demodulator, in each case a data word from an information word and a checkword and wherein a syndrome is generated from the received data word and a parity check matrix, which is used for error detection and optionally error correction.

The reception of data transmitted by radio waves may be disrupted in many ways. There are, therefore, methods for the detection and / or correction of transmission errors become known. In the so-called Radio Data System (RDS), a subcarrier with digitally-coded signals is modulated, and that the data is transferred in groups of four data words, each data word from an information word of 16 bits and a check word of 10 bits. The checkword is formed, in a radio data system according to a predetermined algorithm from the information word, wherein the actual checkword a so-called offset word is superimposed on yet, which is used for synchronization.

When receiving an error checking and error correction is performed after demodulation using the check word. A detailed description of the Radio Data System RDS is present in the publication: "Specifications of the Radio Data System RDS for VHF / FM sound broadcasting", Tech. 3244 - E, March 1984 published by the European Broadcasting Union (EBU). The syndrome formation requires a considerable computational effort.

The object of the invention is therefore to provide a device for receiving data transmitted by radio waves, wherein the simplest possible syndrome formation.

The device according to the invention with the characterizing features of the main claim has the advantage that the computational complexity is reduced in the formation syndrome.

For the device according to the invention also hardwired circuits are suitable in principle, even though the device according to the invention can be formed with microprocessors advantageously. Thereby, the other required components, such as memory, be adapted to the requirements of the device according to the invention. Depending on each selected version, further refinements of the device according to the invention so as to reduce the circuit complexity directly or in terms of a reduction of the computation time affect what ultimately leads to a reduction of expenses or an increase the correction capacity.

The measures specified in the dependent claims, advantageous refinements and improvements of the main claim invention are possible.

Embodiments of the invention a number of figures are presented and explained in detail in the following description in the drawing at hand. It shows:<ul><li>Fig. 1 is a schematic representation of the syndrome formation with the aid of a parity check matrix,</li><li>Fig. 2 is a block diagram of a first embodiment and</li><li>Fig. 3 is a block diagram of a second embodiment.</li></ul>

To distinguish between the reference numbers in the figures 2 and 3 the numbers, which indicate the number of each parallel bits, is provided with a p.

To explain the formation syndrome is 1 in Fig. Proposed in the above-mentioned EBU publication parity check matrix H, and an example of a data word Y and the syndrome formed from this data word, and the matrix H S_Y shown. The matrix H is composed of 26 lines and 10 columns. According to the known method, the calculation of the syndrome S is performed_Y for the data word Y is now such that all rows of the matrix H are each exclusive-OR-linked, in which the data word having the value 1. The multiple exclusive OR operation results known if there is an odd number of ones a 1 and with an even number of ones a 0th

Are many ones in the data word Y exist, many exclusive-links are used to calculate a single syndrome already required. Depending on the system parameters and the required quality of the error detection and correction in detail many syndrome calculations may be necessary in a given time.

For Syndrome Education invention the data word Y is divided into several groups to Y₀ Y₄. A corresponding classification is also made in the matrix H. From each one of the groups Y₁ to Y₄ formed to T₄ and stored for all occurring values ​​of Y₁ to Y₄ in store with the corresponding sub-array a partial syndrome T₁.

The formation of partial syndromes in Fig. 1 with reference to partial syndrome T_1x explained. Given the occurring values ​​of Y₁ are listed both in hexadecimal and as a binary number, plus the respective lines zuverknüpfenden H₁₁ to h₁₄ the matrix H₁ to given. For clarity, the lines for the values ​​9 are not shown to E.

The formation of a partial syndrome from the group Y₀ requires no further action because the partial syndrome T₀ is the group Y₀ because of the partial matrix H₀ property equal.

In each case a data word Y is in the arrangement of Figure 2 in a memory. 1 - for example, a shift register - cached. For this, the bits of the data word Y are read in serially via an input 2 and can be taken in parallel with 26 different outputs. It outputs for the first ten bits (Y₀) of the data word Y are directly connected to inputs of a ten-fold parallel exclusive-OR circuit. 3 The other outputs of the memory 1 are connected combined in four bits into four groups and to address inputs of further memory to 7 (hereinafter called table memory). 4 Each of the four table memory contains 16 10-bit words as the partial syndromes. Depending on the supplied address x of the partial syndromes 16 is read out and supplied to one of inputs of the exclusive-OR circuit 3rd At the output 8 of the exclusive-OR circuit 3 then is the syndrome S_Y to disposal. Unlike the well-known form of the syndrome, only an exclusive OR operation of five partial syndromes is required in the arrangement of FIG. 2 - ie, a serial processing of the exclusive-OR operations just four computational steps are required.

Fig. 3 shows another inventive device, wherein the data word Y is also read via an input 2 in a memory 1 and a first group Y₀ of ten bits directly to the corresponding inputs of an exclusive-OR circuit 11 supplied is. The further portion of the data word Y is divided into two groups Y₁ and Y₂ of eight bits each. The memory 12, 13 have correspondingly eight-bit addresses and each contain 256 partial syndromes with ten bits. In the subsequent exclusive-OR operation 11 then only the combination of three partial syndromes, each with ten bits is required. then is the syndrome S at the output 14_Y to disposal.

Compared to the arrangement of FIG. 2 requires more space in the arrangement of FIG. 3. However, this is a shorter computing time over. 8-bit microprocessors a subdivision of Y in 8-bit groups is present anyway, so that the actual syndrome calculation is then reduced to two exclusive-OR derivatives.