Method of producing highly integrated complementary mos field-effect transistor circuits

The invention relates to a method for the manufacture of highly integrated, complementary MOS-field effect transistor circuits (CMOS-circuits), in which p for accommodating the n- or p-channel transistors of the circuit in the semiconductor substrate or n-doped wells are generated, in which the respective dopants are introduced by lonenimplantationen for setting the various transistor threshold voltages, in which n as a semiconductor substrate^{+ -} or p^{+ -}doped silicon having thereon n-- or p - doped epitaxial layer is used and in which carried out the manufacture of the source / drain and gate regions as well as the generation of the intermediate and insulating oxide and the conductor track level according to known method steps of MOS technology becomes.

Such a method is disclosed, for example, from European Patent Application 0,135,163.

The task underlying the present invention is to increase the latch-up resistance of CMOS circuits with consistently good transistor characteristics as well as in the implementation of a CMOS process in which these properties of an integrated circuit can be obtained without great technical effort.

Modern CMOS processes using technologies which are both n- and p-channel transistors in wells.

The setting of the various Transis gate-threshold voltages (thin oxide transistors and field oxide transistors of both types) is carried out by multiple, coordinated lonenimplantationen.

An increased latch-up resistance (= suppressing the parasitic bipolar effects) was obtained previously by either using an epitaxial layer on a low-resistance substrate or by using a "retrograde well".

The use of an epitaxial layer in a CMOS process is from an article by LC Parillo et. al. from the Technical Digest IEDM 1980, 29.1, pages 752-755, known. The two n-or. p-doped wells are produced in a CMOS process using self-aligned process steps using a mask. The self-adjusting implantation of the two tubs leads in the usual depth of penetration of 5 11m (p-and n-well) at the implantation edge to a strong spatial overlap and moderate charge compensation of the n- or p-implanted regions. A negative consequence of this is that the threshold voltage of the field oxide is reduced and the current gain of the parasitic npn and pnp bipolar transistors is increased, which leads to an enlarged latch-up susceptibility.

Another method which uses an epitaxial layer to increase the latch-up strength is to be taken from European Patent Application 0,135,163. In this method, the threshold voltage of n- and p-channel CMOS FETs by special gate materials and adapted gate oxide thicknesses, and a special channel implantation is adjusted.

Both methods have the drawback that the sheet resistance of the p-well in the region of a few ohms per square is located, which, while the latch-up susceptibility decreases, but does not exclude. Furthermore, the sensitivity of the bath-MOS FET with respect to the substrate is relatively high currents.

The use of a "retrograde-well" in a CMOS process is from an article by RD Rung et al. from IEEE Transactions on Electron Devices, Vol. ED-28, no. 10, October 1981, pages 1115-1119, is known. In this method, a deep implantation with a subsequent short annealing step is generated in the depth a p- or n-well profile with an increased doping by using, creating a shallower trough formed at constant layer resistance and the n⁺/ p^{+ -}Spacing is reduced to a third of its value. A disadvantage of this method lies in the technical overhead of the high energy implantation.

From Patent Abstracts of Japan, Vol 9, No 251 (E-348) (1974) 80/10/85 & JP-A 60101963 is a process for producing a C-MOSFET is known, in which a p-doped well is generated, characterized in that p-doping ions are implanted into a substrate. an n-doped epitaxial layer is then grown on the substrate. In the n-doped epitaxial layer, in turn, p-doping ions are implanted. Through-diffusion of p-doping ions from the substrate and downward diffusion of the p-doping ions from the epitaxial layer, the p-well is produced.

From Patent Abstracts of Japan, Vol 9, No 251 (E-348) (1974), 08/10/785 & JP-A 60101964 is a process for producing a C-MOSFET is known in which a p-well by generated diffusion of a buried in the substrate p-doped layer in an overlying epitaxial layer.

The invention solves the problem of suppressing the parasitic bipolar effects, thus increasing the latch-up resistance in a method of the type mentioned in that<ul><li>a) on the n--, or p - doped first epitaxial layer a second epitaxial layer which is applied by the same conductivity type as the first epitaxial layer is,</li><li>b) epitaxial before application of the second overlying (upper) layer buried in the upper region of the deeper, first epitaxial layer in the subsequent well regions zones (so-called buried layers) of comparatively high dosage are implanted and</li><li>c) the trays are produced by diffusion of these highly doped buried zone in the second (upper) epitaxial layer.</li></ul>

It is within the scope of the invention to generate the troughs in addition by diffusion of implanted in the second epitaxial layer ions.

Further embodiments of the invention, especially two very advantageous process consequences follow from the dependent claims.

Since the tub is formed by diffusion of the highly doped "buried layers" in the upper epitaxial layer and possibly by diffusion of an implanted in the upper epitaxial layer well doping, which may be weak comparatively to the highly doped buried layer, can at a given bath depth which for When the production required diffusion constant-time product will be greatly reduced. In addition, the bath and the epitaxial layer doping at the surface and at depth can be adjusted independently in addition, so that these allocations can be optimally adapted to the transistor and latch-up strength requirements.

By the method according to the teachings of the invention are evident from the reduced diffusion constant-time products the following benefits:<ul><li>a) less crystal defects,</li><li>b) lower dopant diffusion from the highly doped substrate,</li><li>c) no special equipment for Hochtemperaturtemperung greater than 1000 ° C, as usual for Sink drive-in needed</li><li>d) shorter, common drive-in-time for both wells,</li><li>e) less lateral diffusion and compensation of the near-surface regions, despite self-aligned trays,</li><li>f) reducing the spacing tub / epilayer edge because of the steeper When profile.</li></ul>

It also allows the use of "buried layer":<ul><li>a) low When resistance and thus improved latch-up resistance without MOSFET deterioration,</li><li>b) flat pan with constant parasitic collector-emitter breakdown voltage U_CEO.</li><li>c) no mobility reduction due to high doping in the channel region,</li><li>d) no complex and costly high-energy implantation and</li><li>e) less well contacts.</li></ul>

3. Due to the reduced lateral diffusion or the steeper When profile is a lesser n + / p^{+ -}Distance allows. Combined with the reduced number of required contacts When this results in a higher packing density with improved latch-up resistance.

In the following two process sequences for the manufacture of a CMOS circuit will be described in more detail according to the teaching of the invention with reference to FIGS 1 to 17. The process sequences are described for a p-well process, which is based on n-doped silicon base material; accordingly, they are based on p-type silicon base material also be applied to an n-well process.

Figures 1 to 9 show in sectional view the structures generated by the individual process steps, the simplicity are shown summarized several process sequences because in each figure.

Figures 10 to 14 show another process sequence, wherein the generation of the two tubs is performed by outdiffusion from buried layers.

In all figures are for the same parts the same reference numerals.

Figures 15 to 17 show the achieved in the active regions of the n- and p-channel transistors doping profiles, the figure 15 shows the doping profile in the active region of the n-channel transistors of the embodiment described in Figures 1 to 9, while the 16 and 17 on the active region of the n-channel (figure 16) and p-channel transistors (figure 17) refer reached doping profiles of the embodiment of the figures 10 through 14th

1. AusführunosbeisDiel:

<ul><li>Figure 1: On a, a first n-doped epitaxial layer 2 of 3 microns thickness and 0.5 ohm cm resistivity provided n⁺ doped (100) -oriented silicon substrate 1 having a resistivity of 0.02 ohm cm is one of Si0₂ (50 nm) and silicon nitride (140 nm) existing double layer 3, 4 is generated and the silicon nitride layer 4 and the photoresist mask 32 is structured such that the subsequent n-well region remains covered. Then, by a boron ion implantation with a dose of 5 and energy of 1 x 10¹⁴ cm-² and 25 keV in the areas not covered with the photoresist layer 32 and the silicon nitride layer 4 surface areas (later p-well region) a highly doped buried zone 6 (so-called buried layer) produced. This zone 6, the connection to the p-well is produced in the later course of the process by outdiffusion then. In addition, the zone 6 leads to a reduction of the well resistor (p-well) and to increase the collector-emitter breakdown voltage UcEO.</li><li>Figure 2: is in the p-well region is now, after removal of the photoresist mask 32 by oxidation of the surface of a Si0₂ Layer 7 (200 nm) produced and thus the structure edge 8.</li><li>Fiaur 3: shows the arrangement after removal of the silicon nitride (4) and the oxide layer (3, 7).</li><li>Figure 4: shows the arrangement after the deposition of the second n - type epitaxial layer 9 in a thickness in the range of 1 11m and a resistivity of 20 Ohm cm.</li><li>Figure 5: After the preparation of another, from 50 nm Si0₂ and 140 nm silicon nitride existing double layer 10, 11, and structuring the silicon nitride layer 11 with the photoresist mask 33, the p-well 12 in the n-type epitaxial layer 9 by boron ion implantation with a dose and energy of 2 x 1012 cm-2 and 160 keV produced.</li><li>Figure 6: For the phosphorus-ion implantation 14 (1 x 10¹² phosphorus cm-² and 180 keV) for producing the n-well 15 is formed over the p-well region 12 before further oxidation through a Si0₂ Layer 16 produced, the nitride mask 11 is removed and carried out an annealing process.</li><li>Figure 7 shows the arrangement according to the drive-in process for the two wells 12 and 15 at 1000_°C in two to three hours. After bath-drive-in, there is now a connection between the p-well 12 and the underlying p^{+ -}buried layer. 6</li><li>Figure 8: The entire oxide layer 10, 16 is removed and again a 50nm Si0₂ and 140 nm silicon nitride existing double layer 17, 18 in preparation for the LOCOS process (= local oxidation of silicon) produced and structured; the usual photographic technique (not shown in the figure) is performed. The figure shows the assembly during the ion implantation 19 of the field oxide regions of the n-channel transistors with boron ions (1 x 1013 cm-2 and 25 to 90 keV). Here, the n-well region (15) is covered with a photoresist mask 20th The result of 9 with 25 designated in FIG p + doped region, which ensures a sufficiently high threshold voltage of the n-channel field oxide transistors.</li><li>Figure 9: After removal of the photoresist mask 20 and the production of the field oxide 21 by oxidation (using the Nitridstrukturen as oxidation mask = LOCOS) is in an oxidation process, the oxide layer 17 is oxidized (Figure 8) after removal of the nitride 18th Then after etching away the oxide layer 17, the generation of the gate oxide 22 in a defined layer thickness. A full-surface boron ion implantation 23 at a dose and energy of 5x10¹¹ cm-² 25 keV and generates the channel doping 24 of the p- and n-channel transistors, and serves to adjust the threshold voltages of both types of transistors. From this process step, the process of a conventional technology, wherein one or more channel implants are performed depending on gate oxide thickness and gate material follows. These processes are known and can be seen for example from the above-mentioned European patent application 0135163.</li></ul>

The reached in the active region of n-channel transistors as shown in FIG 9 doping profile is qualitatively shown in FIG 15th It is as ordinate the concen tration of boron, phosphorous, antimony c_B. _CP, C_Sb (= First epitaxial layer) and as abscissa the penetration depth of X in microns.

2. Ausführunasbeispiel:

The difference from the first embodiment is that in this process variant with the generation of a p₊ (6) and n^{+ -}buried layer (28) is started. The well implants (13 and 14) made in the first embodiment are replaced by the out-diffusion of the buried layers (6, 28) and thus a photolithography step is saved. Compared to Embodiment 1, this variation allows for an increase of the tub breakdown voltage and a decrease in the bath-substrate capacitance.<ul><li>Figure 10: The process flow is obtained for the beginning of the process analogous to Figure 1. The oxidation of the surface to mask the buried p-layer region 6 (see Figure 2) is here carried out so that the oxide layer 7 with a long bird's beak-like outlet 27 separation of the two buried layers (6 and 28) is formed.</li><li>Figure 11: For the production of the buried n-type layer 28 is now after the nitride etch (4) a phosphorus ion implantation with a dose and energy 29 of 1 x 10¹⁴ cm-² and 40 keV.</li><li>Figure 12: After etching away the oxide layer serving as a mask (3, 7, 27), the second n-doped epitaxial layer 9 (1 gm fat, 20 ohm cm) and about the whole area an insulating Si0₂Layer 30 in a layer thickness of 50 nm. Now the common diffusion takes place of the two "buried layers" 6 and 28 at 1000_°C in 200 to 250 minutes.</li><li>Figure 13: is now analogous to Figure 8 a of 50 nm Si0₂ and 140 nm silicon nitride existing double layer 17, 18 formed on the LOCOS process for the preparation and structured. The figure shows the arrangement during the ion implantation 19 of the areas of the n-channel field oxide transistors with boron ions (1 x 1013 cm-2 and 60 to 90 keV). It is, as described in Figure 8, the cover n-well region (15) with a photoresist mask 20th The result is the one denoted 25 p-doped region.</li><li>Figure 14: After removal of the photoresist mask 20 is generated the field oxide 21, similar to FIG. 9 The removal of the nitride mask and the oxidation of the oxide layer 17 is initially analog, just as all of the following processes, as already described in Figure 9 with the exception of the channel implant 31. This is carried out in two successive steps (not shown in detail in the figure), whereby a deep boron ion implantation at a dose and energy of 5 to 10 x 1011 cm² and 60-120 keV, and then a shallow boron ion implantation with a dose and energy of 5 to 7x10¹¹ cm-2 and 25 keV is performed. The doping of the p-channel transistors will be made accordingly.</li></ul>

The reached in the active region of n-channel transistors doping profile is high doping profile qualitatively shown in Figure 16, which reached for the p-channel transistor in Figure 17 (subject to the same designations as in Figure 15).