DPCM coder and associated decoder.

0001The invention relates to a pulse code differential modulation coding device comprising an input for receiving the signal to be coded, a difference circuit for supplying a difference signal formed by a number of bits representing the difference between the signal to be coding and a prediction signal, a transmission prediction circuit for supplying this prediction signal, a transmission transcoding circuit for reducing the number of binary elements of the difference circuit as a function of control information, an activity measurement circuit for providing activity information, a statistical word coding circuit digital variable length to code the output signal of the transcoding circuit, a buffer memory circuit for storing the words of the statistical coding circuit and for supplying them to the output of said device and a occupancy measurement circuit for providing occupation information of the buffer memory circuit.

0002A coding device of this kind finds important applications in particular in the field of digital television. On this subject, we can refer to the article by PETER PIRSCH entitled "Design of DPCM Quantizers for Video Signals Using Subjective Tests" and published in July 1981 in the review "IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.COM-29, N^o7.

0003We know that in this type of device we are confronted with the problem of the overflow of the memory circuit due to the statistical decoding circuit. Indeed, it may happen that the coding of an image involves the use of words of great length so that more data arrives in the memory circuit than it leaves it.

0004To solve this kind of problem, it is known to act at the level of the transcoding circuit in a direction such that the statistical coding circuit provides words of shorter length (see for example the article by TOSHIO and others entitled: " Statistical Performance Analysis of an Interframe Encoder for Broadcast Television Signals "and published in December 1981 in the journal IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.COM-29, N^o12).

0005However, with this kind of measurement, the image is then coded in a too coarse form and it becomes of poor quality.

0006The present invention provides a coding device of the kind mentioned in the preamble which makes it possible to save an image of sufficient quality in a greater number of cases where a risk of overflow is detected.

0007For this, this device is remarkable in that it further comprises a combination member for providing the control information from the activity information and the occupation information.

0008The invention also relates to an associated decoding device and a transmission system comprising at least one such coding or decoding device.

0009The following description with reference to the accompanying drawings, all given by way of example, will make it clear how the invention can be implemented.<ul id="ul0001" list-style="none"><li>Figure 1 shows a coding device according to the invention.</li><li>Figure 2 shows the appearance of transcoding characteristics.</li><li>FIG. 3 shows how the statistical coding circuit, the memory circuit and the occupation measurement circuit forming part of the device of FIG. 1 are produced.</li><li>Figure 4 shows a decoding device according to the invention.</li><li>FIG. 5 shows how the prediction circuit, the activity measurement circuit and the combination member can be produced.</li></ul>

0010In FIG. 1, the reference 1 indicates a television camera; the analog signal at its output is coded, in digital form by a sample-and-hold coder 2, at the rate defined by a clock circuit 5.

0011The sample at the output of the encoder is compared with the sample supplied by a prediction circuit 10. For this comparison, a difference circuit 12 is used; the resulting difference signal is applied to the input of a transcoding circuit 15 which reduces the number of bits of the difference signal. This reduction is carried out according to characteristics Q1, Q2 and Q3, the shape of which is shown in part in FIG. 2. Thus, in the example in question, the difference signal is coded according to NE on 511 levels (- 255 to + 255) at the input, while the signal at the output only has 15, according to NS; the choice of these different characteristics Q1, Q2 and Q3 is determined by control information applied to an input 20. The output code of the transcoding circuit 15 is applied on the one hand to the input of an adder 21 further receiving on its other input the signal of the predictor 10 and on the other hand, to the input of a circuit statistical coding 22 which matches short digital words for the most frequently occurring input words, i.e. words representing low value difference signals. So for NS = 8 we will have a word of a binary element, for NS = 9 or 7 a word of 3 binary elements and for NS = 10 or 6 a word of 5 binary elements and so on ... according to the coding due to Huffman. On this subject, see paragraph 6.2.3.2. of the work entitled "Digital Image Processing" by RC GONZALEZ and P. WINTZ published in 1977 by ADDISON-WESLEY PUBLISHING Company.

0012The code supplied by this encoder 22 is in serial form at its output and is applied to a buffer memory circuit 25 essentially constituted by a memory of the first input data type, first output data better known by the name of FIFO memory.

0013To determine the transcoding characteristic Q1, Q2 and Q3 offered by the transcoding circuit 15, an activity measurement circuit 30 cooperating with the prediction circuit 10 is used. The activity values ​​produced by this circuit are compared with threshold values ​​SP1 and SP2 by means of comparators 32 and 34.

0014We know that activity defines a luminance transition between picture elements; the activity is all the stronger as the transition is brutal. A strong activity is associated with a coarse characteristic, for example Q3 since it is not necessary (see the first article cited) to precisely code the levels located on either side of the transition. A weak activity is therefore associated with a fine characteristic Q2 or better Q1. Thus by the choice of these characteristics we try to locate ourselves towards the levels NS close to 8 corresponding to words of short length worked out by the coder of Huffman 22. However, we can be in unfavorable cases where the words are very long and where the transmission rate authorized by the transmission channel (represented in FIG. 1 by a coaxial cable 40) is insufficient. It follows that the memory circuit 25 risks overflowing, this risk being assessed by occupation information produced by means of an occupation measurement circuit 45 connected to the buffer memory circuit 25.

0015To avoid this overflow, the coding device further comprises, in accordance with the invention, a combination member 50 for supplying the information for controlling characteristics from the activity information and the information occupation.

0016This combination member 50 is formed, in addition to the comparators 32 and 34, of two multipliers 52 and 54 to multiply by a factor α two values ​​of preset thresholds S1 and S2 and to provide: SP1 = α.S1 SP2 = α.S2

0017The elements 32, 34, 51 and 52 are part of a common assembly 55 which will be found in the decoding circuit associated with this coding circuit. This factor α is established by means of a calculation circuit 60 which performs the following operation: α (T + 1) = α (T) - k. {ρB (T) + [B (T) - B (T)]} where k = [α (T) - α (T-1)] / [B (T) - 2B (T-1) + B (T-2)] and ρ is a damping coefficient whose value can be equal to 0.5.

0018It should therefore be noted that the coefficients α are calculated for successive periods of time τ at times i.τ where i = - ∞, ..., T-2, T-1, T. The instant T.τ corresponding to the present moment. The duration τ corresponds in practice to the duration of an image frame. We call B (T) the degree of filling of the memory circuit encrypted in number of binary elements and considered at time T, B (T-1) the degree of filling at time T-1 and B (T- 2) at time T-2. We therefore propose to determine α (T + 1) which reduces the degree of filling B (T + 1) to zero or better which decreases it by the damping coefficient <img file="EP0246701A1_D0001.tif" /> to reduce it to a fraction of the previous degree, i.e. B (T + 1) = (1-<img file="EP0246701A1_D0002.tif" />) B (T).

0019To calculate α (T + 1) we admit that the variations in degree of filling are a linear function of α, which allows us to write in the present case, with α₀ constant to be eliminated: α (T) = k [B (T) - B (T-1)] + α₀ To estimate α (T + 1) it is therefore necessary that: B (T + 1) - B (T) = -ρB (T) from where α (T + 1) = α (T) - k. [B (T) - B (T-1)] + k. [- ρB (T)] and from there, the proposed formula.

0020The calculation circuit 60 establishes the evaluation of α (T + 1) only on the reading of the degree of filling of the memory circuit; it is this degree of filling which constitutes, in this described example, the occupancy information.

0021In Figure 3, where there is shown in more detail the encoder 22 cooperating with the occupancy measurement circuit 45, it is shown how the occupancy information is produced.

0022The encoder 22 is essentially constituted by a read only memory 100 which is addressed by the output code of the transcoding circuit 15. The code at the output of this memory is split into two parts: a part is applied to the parallel inputs of a register 102 and the other party to the parallel inputs of a shift register 104; register 102 intended to contain a value indicating the width of the word in register 104. The loading commands of these registers 102 and 104 receive an HC signal which is active, at the same rate at which the sampling is carried out by the sampler encoder. The serial output of shift register 104 is connected to the memory input. The recording of this memory is carried out by a WFO signal at the same rate as the shift of the register 104. This WFO signal comes from the output of an AND gate 106 with two inputs: the first receives periodic W signals whose cadence is a multiple of the frequency of the HC signals, this multiple corresponding to the maximum length of the codes contained in the register 104. The second input of gate 106 is connected to the output of a code comparator 108 which provides a blocking signal for gate 106 when an equality of continuous codes is detected, on the one hand in register 102 and d on the other hand in a counter 110 counting the WFO signal pulses. This counter is reset as soon as the HC signal is active.

0023In this way, the memory 25 is successively filled with the binary elements constituting each word of variable length. To obtain the degree of filling of the memory 25, an accumulator circuit formed by an adder 115 and an accumulation register 117 is used. The adder 115 performs the sum of the content of the register 102 with the content of the register 117 reduced with a value "BR". This reduction is carried out by a subtraction circuit 20. The value BR defines the optimal degree of filling of the memory 25, for example, half of its capacity. A signal Hτ which becomes active after each period of time τ allows loading in a register 122 of the degree of filling B (...) useful for the calculation circuit 60. It will be noted that the memory 25 becomes empty at the rate of a RFO read signal. In order to be able to transmit the information thus coded, a multiplexer 150 is used (see FIG. 1); this multiplexer transmits, via a line transmission circuit 151, on the transmission channel 40 for a first time a synchronization code "SYT" supplied by the time base 5 then, for a second time the value α coming from a shift register 152 whose parallel inputs are connected to the output of circuit 60 and finally, for a third time, the image information originating from memory 25, and this is repeated for each image frame. The various signals W, Hτ, HC and RFO, which have been mentioned, come from time base 5.

0024The decoding device according to the invention consists of a line reception circuit 161 whose input is connected to the transmission channel 40 and whose output is connected on the one hand to the input of a base of reception time 165 and on the other hand to a demultiplexer 170 which is controlled by the reception time base 165 and which makes it possible to supply on the one hand to a register 175 the value α and on the other hand the different words of lengths variables to a decoder 172 performing the reverse operation of the decoder 22. A transcoding member 180 performs the reverse operation to that performed by the circuit 15, that is to say one of the reverse characteristics Q<img file="EP0246701A1_D0003.tif" />¹, Q<img file="EP0246701A1_D0004.tif" />¹, Q<img file="EP0246701A1_D0005.tif" />¹. The value to be taken will be taken in the middle of each level. Thus for a code NS = 10 will correspond a code NE = 9 for the characteristic Q<img file="EP0246701A1_D0006.tif" />¹, the choice of one of these characteristics being defined by code information applied to its inputs 181. An adder circuit 185 performs the sum of the output code of the transcoder 180 with the output code at the output of a prediction circuit 190 of the same structure as the circuit 10; there is also an activity measurement circuit 192 of the same structure as the circuit 30; the indication of the measurement is combined with the information α by the circuit 195 to supply the control information in the same way as the assembly 55. A digital-to-analog converter 200 makes it possible to provide the appropriate information so that a display device 210 can operate.

0025FIG. 5 shows a possible example of how to carry out the prediction circuit with the activity measurement circuit and how to obtain the control information. These circuits use the luminance of the points on the previous line and of the previous points of the same line.

0026The assembly shown in FIG. 5 is built around a set of delay elements 200, 201, 202 and 203 mounted in cascade; elements 200, 202 and 203 provide a delay of one picture element while element 201 brings a delay equivalent to a picture line reduced by two picture elements. It is from the various signals at the outputs of these elements that we can, on the one hand, make the prediction and, on the other hand, measure the activity.

0027With regard to prediction, different multiplexers 210, 211, 212 and 213 respectively produce the product by the prediction coefficients KM, KD, KC and KB of the signals at the outputs of elements 200, 201, 202 and 203; an adder 215 supplies the prediction value by summing the products.

0028Regarding the activity, different operators 220, 221, 222, 223, 224 and 225 are used which give the absolute value of the difference of the signals applied to them in inputs. These inputs are connected to each of the outputs of elements 200 to 203. A first series of comparators 250 to 255 detects if one of the results obtained by one of the operators 220 to 225 exceeds the threshold value SP1; an OR gate 228 collects all the results of this series of comparators 250 to 255 in order to restore the first binary element of the control information. A second series of comparators 260 to 265 detects if one of the results obtained by one of the operators 220 to 225 exceeds the threshold value SP2; an OR gate 238 collects all the results of this second series of comparators 260 to 265 to constitute the second binary element of the control information.

0029The transcoders 180 and 15 are advantageously constituted by a read-only memory whose addresses are constituted, on the one hand for the least significant, by the output signal of the subtraction circuit 15 or the decoder 172 and, on the other share for the most significant by order information.

0030FIG. 6 shows how the factor α acts on the entropy S which defines the lower limit of the bit coding by picture element. This therefore gives the possible flow regulation.