Nova Patents
EP0245955A2

Amplifying circuit arrangement.

Abstract

A robust amplifier consists of two delay lines 12 and 23 linked by a number of discrete amplifiers 13. Distortion correction is carried out by distortion feed forward. This is achieved by sampling the output of each amplifier 13 at a coupler 17 and then subtracting this sample from the input signal to later amplifiers (13) along the delay line 12 at directional coupler 19. As a result each discrete amplifier's distortion is corrected by all of the following discrete amplifiers (13) in the amplifying circuit.

EP0245955A2, drawing sheet 1
Sheet 1 of 3

Term

Term ended

Projected expiry passed 10 April 2007, 19.5 years ago.

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6 claims: 3 independent, 3 dependent

  1. 1
    An amplifying circuit arrangement including a plurality of discrete amplifiers (13) connected between succesive points of an input delay line (12) and corresponding points of an output delay line (23);the discrete amplifiers (13) forming a series which is fed in order by a plurality of power dividers (11) positioned along the input line (12) so as to share the power of an input signal between the amplifiers (13), the outputs of the amplifiers (13) being connected to said output line (23) by a corresponding plurality of power combiners (22);means (17,18,19) for separately sampling the output signals of each of a plurality of said amplifiers (13) and utilising the sampled signals for modifying the input signal on said input line (12) and which is fed to subsequent amplifiers (13) in said series so that the distortions of said sampled amplifiers (13) are compensated by the subsequent amplifiers (13).
  2. 4
    An arrangement as claimed in any of the preceding claims, and wherein the means for separately sampling the output signal of an amplifier and utilising the sampled signals to modify the input signal fed to subsequent amplifiers in the series are arranged to attenuate the sampled signal such that all signal paths through the amplifying circuit arrangement have equal gain.
  3. 6
    An arrangement as claimed in any of the preceding claims, and wherein each delay line comprises discrete delay elements connected between adjacent power combiners or power dividers, as the case may be.