Write request buffering apparatus

Apparatus (10) for buffering writes from a CPU (12) to main memory (22), in which sequential write requests to the same address are gathered and combined in a buffer into a single write request. The arrangement described does not permit gathering with the write request in the buffer which is next scheduled for action by the main memory bus controller (20), nor does it permit gathering with other than the immediately preceding write request. The technique is implemented using a plurality of buffer ranks, each comprising a data rank, an address rank, and a valid rank for indicating which bits or bytes of the data rank contain data to be written to memory.