Encapsulation method for integrated circuits
3 claims: 1 independent, 2 dependent
- 1Procédé d'encapsulation de circuits intégrés fixés sur un ruban diélectrique souple (10) portant des conducteurs électriques imprimés constituant les broches de connexion extérieures (20) des circuits intégrés, caractérisé en ce qu'il consiste à placer le ruban diélectrique à plat entre une première (44) et une seconde (46) plaques d'un moule, les deux plaques définissant entre elles, lorsqu'elles sont en contact avec le ruban, un plan de joint (52) dans lequel est placé le ruban et au moins une cavité (40) entourant un circuit intégré et entourant partiellement les conducteurs imprimés situés autour de ce circuit, la cavité étant pourvue d'un orifice (48) d'injection de résine situé en dehors du plan de joint, et à injecter une résine thermodurcissable dans la cavité par l'orifice.
- 2Procédé d'encapsulation de circuits intégrés selon la revendication 1, caractérisé en ce que l'orifice est situé dans l'une des plaques (46).
- 3Procédé d'encapsulation de circuits intégrés selon la revendication 1, caractérisé en ce que l'orifice est constitué entre l'une des plaques (66) et une plaque intermédiaire (76) séparant cet orifice du ruban diélectrique (10) lorsque celui-ci est placé dans le moule.
Independent claims3
59 paragraphs, as filed
p0001The present invention relates to an integrated circuit encapsulation process.
p0002Some users of integrated circuits wish that their book tours as continuous flexible bands (rolls) with integrated circuits.
p0003In this way these users can more easily automate the assembly of these integrated circuits on printed circuit boards or on other media. This applies especially in the case of integrated circuits to be mounted on the surface; the mounting surface mounting components is a type more easily automated than the assembly of components by insertion into holes in printed circuit boards.
p0004The surface mount machines receive, as a source of supply components, wound strips carrying the components, these strips are not entrained by step in the manner of a film spool. It was not until the time of mounting on a printed circuit as an individual component is separated from the rest of the band.
p0005To produce strips of integrated circuits, is provided essentially two types of manufacturing.
p0006The first is used as a carrier strip cut metallic grid (copper grid for example) that comprises, for each component location on the one hand a base for receiving an integrated circuit chip and the other individual conductors serving as external connection pins for the integrated circuit. To keep a sufficient mechanical strength of the grid, the conductors constituting the external pins are connected to each other by elements of the grid and are thus short-circuited with each other. It was not until the detachment of an individual component for mounting the pins on circuits Décourt by cutting the elements that connect them drivers.
p0007The second type of manufacturing is to use a dielectric film as a support band (typically polyimide) having formed a pattern of thin film conductors, drivers, again, serve as external pins for the component during assembly on a printed circuit. The conductors are printed on the dielectric film; so this is the dielectric film that ensures their mechanical strength, although in places the film has openings over which pass the conductors. It is not necessary to provide connecting elements between the various conductors to provide mechanical rigidity thereof.
p0008Two major problems arise in practice. The first problem is the test of integrated circuits, the second is their protection.
p0009Regarding the test, the strips made from a cut-out metal grid priori make it impossible to test the circuits as they are on tape since their pins are all short-circuited to the separation into individual components; the test can be done on the integrated circuit chip before it is fixed on the grid and connected to the conductors of the grid (test group); it can also be done after detachment of an individual component when mounting on a printed circuit, but it's too late because we prefer to deliver the user already tested components rollers.
p0010This is also one of the reasons why we felt the need to mount ICs on dielectric films, because then the pins are not shorted and circuits can be tested on the tape.
p0011As regards the problem of the protection of integrated circuits, they are known to be chemically and mechanically very fragile and it is obviously out of the question to deliver to a user a web of integrated circuits in which the circuit chips would not be protected in one way or another against mechanical shocks, against corrosion agents and optionally against electromagnetic radiation.
p0012For strips made from a conductive grid, this does not pose a problem, the protection is by encapsulation in a thermosetting resin housing; the technique is that which is commonly used for producing integrated circuits in plastic housing; this technique is the transfer molding process comprising placing in a mold the grid bearing the chips, and injecting a thermosetting resin around the assembly.
p0013Experience shows that this protection technique, as used conventionally for the encapsulation of integrated circuits in plastic box does not lend itself at all to the encapsulation of circuits mounted on dielectric tape. Indeed, the thermosetting resin is injected at an elevated temperature and the dielectric deforms irreversibly ribbon; the deformed tape is not satisfactory from the point of view of appearance and it does not lend itself to a tight coil winding.
p0014To protect integrated circuits mounted on dielectric tape, so we use a simpler technique that transfer molding: a drop of curable resin is deposited on the chip that comes coat the chip and the ends of the printed conductors connected to the chip. But the mechanical protection and protection against radiation are much lower than those that can be obtained with a thermosetting resin. Sometimes parts of the chip are bare (back, sides). Furthermore, depositing a drop of resin absolutely not possible to form a component with calibrated dimensions as is the case for Moulded case; the resin is formless, it spreads more or less, the overall amount deposited is variable etc ...
p0015To reconcile the conflicting test requirements and protection of quality, one leading to choose a dielectric tape with printed conductors and the other leading to choose a cut metal band, it has already been proposed a complex and expensive solution that is follows: a metal mesh is used, and, during the molding operation of a thermosetting resin, it not only makes the plastic housing encasing the integrated circuit chip and leaving exceed the external connection pins short-circuited by tie bars, but also a plastic peripheral ring around the housing; the external connection pins then extend between the housing and the peripheral ring; they are rigidly held by the housing on one side, by the ring from each other, and they can then be Décourt-circuited by disconnecting the connecting bars without the mechanical strength of the tape being affected; outside of the peripheral ring, test pads connected to the connecting pins are held in place by the ring. The individual test components is facilitated through these pads; However, this test is only possible after component separation into individual elements and not as they are in band. The protection is of good quality since it is made by molding a thermosetting resin.
p0016The disadvantage of this solution is its high cost because the molds to be used are complex, and the size resulting from the use of a peripheral ring is particularly important. In addition, the test strip is not possible.
p0017The invention is based on the experimental finding that the deformation of the dielectric tape which makes a priori unusable transfer molding with a thermosetting resin may be avoided by using a different operation of molding the one usually used.
p0018In known techniques for the encapsulation of integrated circuits in thermosetting resin, is always used molding between two separable mold plates which is closed after placing the conductive plates between the grid bearing the chips; injecting thermosetting resin is made by the joint plane between the two mold plates. This enables easy cleaning of molding plates and the resin injection port after the molding has been performed and we have removed from the mold the band encapsulated components.
p0019The present invention as claimed intends to carry out said molding tip molding which is usually used for molding thermoplastic resins rather than thermosetting resins but we will use here with a thermosetting resin. The tip molding comprises injecting the resin into the molding cavity formed between the mold plates through a hole which is not located in the parting plane between the mold plates.
p0020It is noted that this type of molding eliminates difficulties encountered with conventional mold.
p0021It must be understood that if the thermosetting resins are usually injected through the parting, it is because these resins solidify irreversibly cooling and injection through an orifice that does not open with the mold makes it much harder to clean the hole after each molding operation. Instead thermoplastic resins can be injected through a port which does not open with the molding plates because even if the resin hardens as it cools, it melts again by warming. Here, one will use an advanced molding, an orifice which can not be opened with the mold, but with a thermosetting resin.
p0022So instead of staying on the idea that the thermosetting resin is at too high a temperature to be used without damage to the dielectric tape bearing the integrated circuit, the present invention proposes injecting the same resin, at the same temperature , but in a way that is uncommon for the integrated circuits and which is not a priori desirable for thermosetting resins.
p0023Other features and advantages of the invention appear on reading the detailed description which follows and which is given with reference to the accompanying drawings in which: <ul><li>1 shows a perspective view of a dielectric strip bearing printed conductors,</li><li>2 schematically shows an enlarged section of this strip at a chip</li><li>Figures 3, 4, 5, 6 represent the encapsulation methods variants of the prior art,</li><li>7 shows, in side view, a strip of encapsulated components according to the present invention,</li><li>Figure 8 shows schematically the constitution of the mold for the encapsulation,</li><li>9 shows a mold of the embodiment.</li></ul>
p0024In Figure 1 we recognize a flexible dielectric material 10 of continuous tape for supporting integrated circuits and to be wrapped to be delivered in roll form to a user.
p0025The ribbon 10 is for example of polyimide of a thickness of about 0.125 millimeter.
p0026It has side perforations 12 such as those found on the edges of the motion picture. These perforations are intended to allow the automatic advance continuously or step by step of the ribbon 10, both during the manufacture of tapes with integrated circuits that during the use of these bands for the supply of components of a mounting machine components on printed circuit boards. The tape 10 also has other perforations which will be explained the role further.
p0027The tape 10 also comprises electrical conductors 14 thin film printed on the upper surface of the ribbon. By printed conductors refers conductors formed in a specific pattern, either by photo or by any other means, and that adhere to the surface of the tape.
p0028These conductors are adherent to the surface of the dielectric film but in some places they extend above perforations formed in the dielectric tape; in these places, the natural rigidity of the conductive film to switch above the perforations without breaking the conductors (the thickness of the conductive film is chosen accordingly).
p0029The conductor pattern 14 and the pattern of perforations which pass above the conductors is repeated at regular intervals along the strip 10, each pattern corresponding to the location of an integrated mounting on the band circuit.
p0030The conductors 14 are individualized, they are not short-circuited with each other as is the case in the strips formed from a cut-out metal grid.
p0031Each conductor consists essentially of three parts:<ul><li>an inner end, toward the center of the conductor pattern; this end is intended to be connected to a respective contact pad provided on an integrated circuit chip to be placed in the center of the pattern; the inner end is in cantilever over a central hole 16 formed in the tape 10 at the center of the pattern, the integrated circuit chip being located in this central perforation in principle on the side of the rear face the ribbon (if we take as the front face carrying the printed conductors).</li><li>an outer end adheres to the dielectric tape and preferably comprising a test pad 18 said pad through which may be applied or collect electrical signals for testing the circuit after fixing on the tape.</li><li>a central portion 20 passing over a peripheral perforation 22 formed in the ribbon. This central part is that which will serve as external connection pin for the integrated circuit when it is encapsulated.</li></ul>
p0032In the example shown in Figure 1, the central hole 16 and the peripheral perforations 22 are separated by bridges 24 of dielectric material of the tape. These bridges 24 are used to improve the mechanical strength of the conductors 14 that adhere to the dielectric of both the outer side (the side of the test pads, beyond the peripheral perforation 22) and the inside (on deck 24 side the inner end of the conductors).
p0033In some cases, for small circuits, it may provide that the central perforation 16 and the peripheral perforations 22 are combined into a single perforation, the conductors 14 then being supported only on one side and being in door false over the entire length corresponding to the central part and at the inner end. It is understood that this provision is only possible if the length is not too large.
p0034In the prior art, the manufacture of the component tape was first electrically connecting the inner ends of the conductors to an integrated circuit chip implementation at the center of the conductor pattern; This connection is done for example by direct welding conductor terminations on the various contact pads provided on the chip; the welding is in principle a thermocompression bonding; then a drop of curable protective resin is deposited (epoxy resin) on the upper face of the chip (the one with the contact pads); this resin drop roughly coats the sides and in general not the back of the chip.
p0035After polymerization of the resin the component tape is ready; the individual components can be tested through the testing pads 18 corresponding to each of the outer connection conductors of the integrated circuit.
p0036The user receiving the band no longer has to perform a cutting operation for:<ul><li>an integrated circuit separate from the rest of the band,</li><li>cutting the dielectric tape around the encapsulated circuit and cut the conductors 14 between their outer end and their central part, so as to obtain an encapsulated circuit which emerge external connection pin formed by the central portion 20 extending previously over a peripheral perforation 22.</li></ul>
p0037Figures 2, 3, 4, 5 and 6 show diagrammatically various sectional structures thus obtained; references are the same as in Figure 1, the chip is designated by 26, the curable resin by 28.
p0038Figure 2 corresponds to the case where dielectric tape bridges 24 between the central hole 16 and the peripheral perforations 22.
p0039Figure 3 corresponds to the case where there is a central perforation and no peripheral perforation.
p0040Figure 4 corresponds to the case where it was placed at the back of the chip, prior to the deposition of the drop of resin, a back protective sheet 30, for example glass cloth impregnated with epoxy resin.
p0041Figure 5 corresponds to the case where the conductors formed on the dielectric tape are not welded directly on the chip contact pads, but the bridges conductors 32 are welded between the printed conductors 14 and the contact pads of the chip.
p0042Figure 6 corresponds to the case where son 34 (gold or aluminum) are welded between the printed conductors 14 and the contact pads of the chip.
p0043In the case of Figures 5 and 6, the central perforation of the dielectric tape 10 becomes unnecessary, only the peripheral perforations remain; bridges 24 drawn in Figure 1 then occupy all the space of the center hole and the chip is based on the tape, possibly metallic at the location of the chip.
p00447 shows a section of a strip of encapsulated components of the invention.
p0045Each component is coated with a thermosetting resin 38 obtained by transfer molding around the dielectric strip 10 bearing the chips 26 and the conductive thin film.
p00468 shows the schematic sectional structure of the mold used in the process according to the invention.
p0047This mold has two movable plates defining between them when are applied one against the other (mold closed) the mold cavities corresponding to the location of each component to be coated.
p0048In Figure 8, the mold comprises two cavities 40 and 42 for the simultaneous molding of the two components shown in Figure 7.
p0049Mobile plates defining these cavities are respectively a bottom plate 44 and said plate intermediate plate 46.
p0050In the intermediate plate 46 is provided, resulting in each of the cavities, a respective port of thermosetting resin injection, respectively 48 for the cavity 40 and 50 for the cavity 42.
p0051This aperture is not placed in the closure plane of the plates 44 and 46, that is to say the plane containing the strip 10 during the molding operation (plane perpendicular to the sheet in Figure 7 and s extending along the dotted line 52).
p0052On the contrary, as seen in Figure 7, the injection port of each chamber, is located well away from the plane containing the tape 10.
p0053The intermediate plate 46 and bottom plate 44 are formed in their surfaces vis-a-vis one another, so as not to crush the different portion of the dielectric strip (ribbon itself, bridges 24, printed conductors, chip 26 etc ...) when the mold closes.
p0054Finally the mold has a top plate 54 provided with holes (56 and 58) facing the respective injection orifices (48 and 50) of the intermediate plate, and provided with resin injection means, symbolized by respective pistons 60 and 62 capable of discharging the liquid thermosetting resin of the orifices 56 and 58 of the upper plate 54 towards the openings 48 and 50 of the intermediate plate and from there into the cavities 40 and 42.
p0055The holes of the top plate 54 are preferably cylindrical. Those of the intermediate plate 46 are preferably conical to facilitate the extraction of the "cores" of resin after a molding operation, that is to say, the extraction of cured resin remaining in the ports 48 and 50 after cooling the mold. Is obtained by the method according to the invention of the well-protected compound, encapsulated in a very reproducible size box, and this by allowing a storage dielectric flexible band allowing the tape component of individual test.
p0056In another embodiment, the injection port is not oriented vertically, ie perpendicular to the plates closure plan, but horizontally, parallel to the plane of the strip 10.
p00579 shows the configuration of the mold, with an orifice. The mold essentially comprises an upper plate 64 and a lower plate 66 defining between them, when closed, a mold cavity 68.
p0058The injection is done by a piston (or pistons) 70 horizontal repressing the thermosetting resin in a conical opening 72 generally parallel to the plates closing plane (plane indicated by the dashed line 74). The orifice 72 is however away from this plane and is, in this embodiment, bounded on one side by the bottom plate 66 and from each other by an intermediate plate 76 which is in contact with the dielectric film 10 when it is placed in the mold and which thus separates the film of the injection port 72.
p0059The method according to the invention is usable for various configurations of printed conductors on the tape perforations, and connection mode between the printed conductors and the chip, and in particular to configurations corresponding to the components of Figures 2 to 6.
2 sheets
Sheet 1 Sheet 2
Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| EP0110518A | Cites | European Patent Office (EPO) |
| FR2390008A | Cites | France |
| FR2520541A | Cites | France |
| GB2164794A | Cites | United Kingdom |
13 members in 8 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 8606333 | France | – | |
| 8606333 | France | A |
Members13
| Document | Office | Kind | |
|---|---|---|---|
| EP0244322A1 | European Patent Office (EPO) | A1 | |
| WO8706763A1 | World Intellectual Property Organization (WIPO) | A1 | |
| FR2598258A1 | France | A1 | |
| EP0264416A1 | European Patent Office (EPO) | A1 | |
| KR880701460A | Republic of Korea | A | |
| FR2598258B1 | France | B1 | |
| JPS63503265A | Japan | A | |
| US4857483A | United States of America | A | |
| EP0244322B1This record | European Patent Office (EPO) | B1 | |
| AT64493T | Austria | T | |
| ATE64493T1 | Austria | T1 | |
| DE3770691D1 | Germany | D1 | |
| JP2759083B2 | Japan | B2 |
41 legal events, as 3 offices reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | Office | |
|---|---|---|---|
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Notification of lapseLapsedST | ST | FR | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Annual fee paid to national office [announced via postgrant information from national office to epo]GrantedPGFP | PGFP | EP | |
| Annual fee paid to national office [announced via postgrant information from national office to epo]GrantedPGFP | PGFP | EP | |
| Gb: european patent ceased through non-payment of renewal feeCeasedGBPC | GBPC | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Annual fee paid to national office [announced via postgrant information from national office to epo]GrantedPGFP | PGFP | EP | |
| Patent endorsed licences of rightsD6 | D6 | FR | |
| Undeliverable decisions opened (patents)LE BREVET CI-DESSUS EST TOMBE EN DECHEANCE FAUTE DE PAIEMENT, DE LA 6E ANNUITE.AUV | AUV | CH | |
| Patent ceasedCeasedPL | PL | CH | |
| Be: lapsedLapsedBERE | BERE | EP | |
| No opposition filedOpposition26N | 26N | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| No opposition filed within time limitOppositionORIGINAL CODE: 0009261PLBE | PLBE | EP | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: NO OPPOSITION FILED WITHIN TIME LIMITSTAA | STAA | EP | |
| Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents actLapsedNLV1 | NLV1 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| It: translation for a ep patent filedITF | ITF | EP | |
| It: translation for a ep patent filedITF | ITF | EP | |
| Corresponds to:REF | REF | EP | |
| Gb: translation of ep patent filed (gb section 77(6)(a)/1977)GBT | GBT | EP | |
| Designated contracting statesAK | AK | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Corresponds to:REF | REF | EP | |
| Miscellaneous (additional remarks)VERBUNDEN MIT 87902560.9/0264416 (EUROPAEISCHE ANMELDENUMMER/VEROEFFENTLICHUNGSNUMMER) DURCH ENTSCHEIDUNG VOM 19.11.90.XX | XX | EP | |
| (expected) grantORIGINAL CODE: 0009210GRAA | GRAA | EP | |
| Designated contracting states (corrected)RBV | RBV | EP | |
| Miscellaneous (additional remarks)VERBUNDEN MIT 87902560.9/0264416 (EUROPAEISCHE ANMELDENUMMER/VEROEFFENTLICHUNGSNUMMER) DURCH ENTSCHEIDUNG VOM 19.11.90.XX | XX | EP | |
| Party data changed (applicant data changed or rights of an application transferred)RAP1 | RAP1 | EP | |
| First examination report despatched17Q | 17Q | EP | |
| Request for examination filed17P | 17P | EP | |
| Designated contracting statesAK | AK | EP | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI | EP |
Numbers
- Publication
- 0244322
- Application
- 874009863
Titles3
- German
- Verkapselungsverfahren für integrierte Schaltungen
- English
- Encapsulation method for integrated circuits
- French
- Procédé d'encapsulation de circuits intégrés
Classification
- CPC, 9
- H10W74/016
- H10W74/01
- B29C45/14655
- B29C70/72
- Y10T29/49121
- Y10T29/49172
- Y10T29/49158
- H10W90/756
- H10W72/5522
- IPC, 3
- B29C45 14
- B29C70 72
- H10W74 01
Designated states1
- Contracting states, 1
- Sweden
