Method and arrangement to accelerate the transfer of an instruction to the instruction register of a micro-programme-controlled processor.

The invention relates to a method and a system for rapid deployment of a command in the command register of a microprogram controlled processor according to the preamble of claim 1.

The performance of modern computers is primarily determined by the commands per unit time editable. Regardless of the operating speed of circuits and circuit components, the speed of a computer can be increased mainly through structural measures. Such structural measures consist, inter alia, the use of a fast buffer memory between RAM or central memory and processor as well as an instruction buffer which receives foresight subsequent instructions of a program from the buffer memory and the instruction register fed successively with the commands - you see, for example "Electronic computing systems", 1973 , No. 2, pages 60 to 65th

The storage of the commands are independent of the length of the individual instructions that can comprise, for example 16,32 or 48 bits, continuously on data units of constant length, for example 64 bits in accordance with a double-word of 8 bytes, distributed, so that the start of a command usually does not coincide with a double word boundary, and thus the beginning of a data unit. To select a command from the data units stored in the instruction buffer separate select switches are therefore necessary to refer to the respective instruction aligned left-justified to the instruction register - you see, eg, "computer", Vol 7, No.. 11 (Nov. 1974), pages 24 to 38th

In each case, a plurality of data units to be provided in advance in the instruction buffer and the instruction buffer duplicated, so when possible program branches as a result of fulfilled jump instructions and the first orders for the branch direction may be provided in advance as a rule.

But the path from the command buffer to the command register means always a delay of an elementary cycle of the processor when in filled jump commands the jump decision exists prior to the transfer from the buffer memory into the instruction buffer or has to be reloaded for any reason, the command buffer. It is therefore an object of the invention to control the deployment of the commands in the command register so that no unnecessary waiting times for the instruction decoding occur and unnecessary waiting elemental cycles are avoided.

This object is achieved with respect to the method according to the invention by the characterizing features of claim 1.

Thereafter, the respective first instruction to be transferred from the buffer memory new command sequence from the buffer memory is already left-aligned in the form of an aligned data unit delivered, so that it can be directly zugleitet the instruction register.

At the same time aligned data unit is fed via a return host the first register of the instruction buffer so that this saved since data unit of unaligned form in the buffer corresponds again and join the subsequently be passed to the buffer memory unaligned data units from its address forth seamlessly to the first data unit , Immediately to the transmission of the first command in the command register can therefore be started with the interpretation of the command in the same elementary cycle already.

From British Patent Specification 11 56 249 it is already known to simultaneously supply the respective first data unit from the buffer memory, both the instruction buffer and a separate register. This register is followed by a selection switch on the respective first, beginning at one of the half-word boundary 8 bits of the operation code of an instruction can be adjusted by the corresponding least significant address of the command, so that a downstream operation code decoder can begin immediately with the command Query.

Since the instruction length may be different and an instruction can begin at any halfword boundary, the entire command is often not immediately available, so that a complete interpretation only after replenishment of the special register is possible. This costs time and again requires additional effort for the replenishment, as each half-word section of the register for each half word of the subsequent data unit must be separately selectable.

The achievable with the new procedure time saving primarily comes fully into play when, are detected with a data unit at least two orders of the longest length, ie at least 1.5 double words, so that the next command can be respectively provided in time from the command buffer. Shorter data units, for example a double word can be hand then use, according to a further according to claim 2 during a Elementarzyklusses two data units from the buffer memory with a time interval of one another are provided for the adoption in the command buffer.

An assembly according to the invention results from the features of claim 3. The starting point is a buffer memory, in which two successive data units can be simultaneously read always, from which then left-aligned beginning with the desired command data unit is formed so that the instruction register can be driven directly. In order to still maintain the operation of the command buffer in the conventional manner, this unit aligned data is supplied in parallel to the instruction buffer via a second selection switch as a back organizer. All other data units from the buffer memory are then passed unchanged in the previous example, from the buffer memory to the instruction buffer so that it contains a copy of each group of data stored in the buffer memory data units, from which the commands are selected in sequence for the instruction register.

Following the usual linear addressing may be used for setting the selector switch easily the corresponding least significant address of the respective instruction addresses are used while defining the action timings of the elemental cycles forming clock pulses is expediently in conjunction with the triggering read commands. Corresponding further developments emerge from the dependent claims.

Details of the invention are explained below with reference to an embodiment shown in the drawing. Specifically show<ul><li>FIG 1 is a schematic block diagram for an arrangement according to the invention,</li><li>2 shows a data structure diagram for explaining the operation of the arrangement of Figure 1 and</li><li>3 shows pulse diagrams for explaining the timing sequence of the invention.</li></ul>

The block diagram of FIG 1 shows in the upper left part of the buffer memory CACHE with his control C-ST and at the bottom of the instruction buffer IB with control IB-ST and downstream instruction register IR.

The instruction buffer IB consists of two sets of registers Iba1 to IBA4 and IBB1 to IBB4, of which the second group is used in a conventional manner in the case of a program branch. Each of the register groups is coupled to a selector switch or IALA IALB that of the corresponding least significant bits of each instruction address selects the associated command from the data units stored in the registers depends in a known manner.

The data units correspond, for example 64 bits each corresponding to a double word DW, which is subdivided into 4 half words of 16 bits each, of which make up the individual commands. The 4 register each group can thus accommodate a total of 4 double words, from which the required half-phrases of a command can be selected in cyclic sequence.

If the instruction buffer IB empty, all 4 double words are read sequentially from the buffer memory CACHE and the instruction buffer IB filled. If two double words DW under the command processing has expired, the associated register to be refilled in cyclic sequence.

This automatic vorauschauende refilling of the instruction buffer IB is caused in a conventional manner by the associated control IB-ST.

The memory units of the buffer memory CACHE have a memory width of two double words DW, and there are always two address moderate consecutive double words DW read simultaneously, even if they are stored in different rows of a storage unit. This is in a simple manner by using separate memory halves with a width of only one double word DW - as shown - is possible.

In effect the invention the read output of the buffer memory CACHE is a selection switch IALC downstream which selects DW each 4 consecutive and in a double word forming as data half-words from each read two double words, and in such a manner that the respective desired and by the read address certain command is left-justified contain aligned in this data unit. Through timely reversal of the directional switch MUX2 at the input of the instruction register IR so the first command of a new command sequence, bypassing the instruction buffer IB can be directly supplied to the instruction register IR.

Furthermore, the input of each first register is Iba1 or IBB1 another selection switch IBAL upstream, which operates as return aligner and the effect of the first selection switch at the output of the buffer memory CACHE makes reverses so that the einzuspeichernde in the first register of the buffer memory IB data unit originally read from the buffer memory cACHE data unit corresponds with respect to the location of valid bytes in the full and the address of linearity with the following, unchanged in the instruction buffer IB transferred data units is maintained.

The selector switch can be made in a conventional manner of a series of multiplexers, all input is connected to all selectable halfword areas in cyclically wrong order - you see, for example DE-OS 31 38 897th

This results in accordance with the data structure diagram of FIG 2 following procedure:

Starting from 2 memory lines in the buffer memory CACHE with the bytes 0 to V, each of which 2 bytes form a half-word, is dependent on the read address AD, showing the example chosen to byte 6 as command early, the corresponding double word with the bytes 0 to 7 and read the following double word with the bytes 8 to F simultaneously. These two double words could also be shifted to a double-word length and are in different memory lines.

Since the double word boundary does not coincide with the command beginning, wherein a first instruction of a sequence characterizing read command, for example, RIE, the selection switch IALC effective and from the two read double words DW a beginning with the desired instruction double word 1.DW selected as the data unit and transmitted, comprising bytes 6 to D. Subsequently the selection switch IALC is only set to the second read full double word with the bytes 8 to F and transfer this.

While the double word 1.DW unchanged reaches the instruction register IR, it is back again aligned for storage in register Iba1 the instruction buffer IB. The locations of the original, but now invalid bytes 0 to 5 are thereby filled with zeros so that the bytes 6 and 7 slip back to their original locations. The second transmitted double word 2.DW will hand over to the IBA2 register unchanged. To further fill the instruction buffer IB two subsequent doublewords 3.DW and 4.DW are subsequently read by bytes G to N or O to V and transferred to the register or IBA3 IBA4 by in this case, automatically triggered further read command RIH , The same applies for the more cyclical refilling now freed-register IBA ....

Simultaneously with the filling of the first register Iba1 including the instruction register IR is loaded with the first full command so that the command interpretation of the full instruction can be started immediately, without any additional transfer operation from the first register Iba1 the instruction buffer IB to the instruction register IR required is.

The timing diagrams of FIG 3 illustrate the associated control sequence from a temporal perspective. In the top two rows of the diagram that is represented by the elementary cycles EOZ of the processor with the associated clock phases CL1 to CL4 predetermined time period. Below it are two groups A and B of chart lines that reflect the course once in a conventional manner with control of the instruction register IR alone on the instruction buffer IB to the other according to the invention.

In the elementary cycle EOZ1 previous elementary cycle of the case is, for example, occurred in that the instruction buffer IB reset become or a jump instruction has come to perform, having a read operation in the buffer memory CACHE result. This is indicated by the marked as read command RI or RIE control command CMD, which is started at the beginning of the elementary cycle EOZ1. This command runs with the start of the subsequent cycle EOZ2 for providing the first double word 1.DW at the output of the buffer memory CACHE, so that it is transferred to the subsequent clock pulse CL-IB1 corresponding to the clock pulse CL2 in cycle EOZ2, into the instruction buffer IB.

Under the assumption that the rapid filling of the instruction buffer IB in an elementary cycle two double words can be transmitted at the output of the buffer memory CACHE with the beginning of the clock pulse, the second double word 2.DW provided CL3 and in the triggered by clock CL4 clock pulse CL-IB2 the register of the instruction buffer IB IBA2 transferred. Only in the subsequent elementary cycle EOZ3 can therefore be applied and interpreted in the instruction register IR with the triggered by the clock pulse CL2 clock pulse CL-IR, the first instruction from the instruction buffer IB. From the beginning of the elementary cycle EOZ1 until at least the beginning of the clock pulse CL2 in Elementrazyklus EOZ3 so the processor with further processing of commands has to wait which is indicated by hatching in the line I-EX.

If, however, the one provided by the buffer memory CACHE first double word so collected or aligned such that it already includes left-aligned the entire first command corresponding to the lower part B of the diagram, it can travel through gleichzeitigt in this case already triggered with the clock pulse CL-IB1 clock pulse CL-IR transferred directly into the instruction register IR and the first command already interpreted an elementary cycle earlier in the elementary cycle EOZ2. The waiting time for the continuation of the command handler so shortened each time by the duration of a Elementarzyklusses.

This time saving is both independent of the rest of the structure of the processor - so it also comes at a pipeline structure for supporting - as the decision is also independent of the type of jump instructions when the jump condition and possible before the appropriate commands in instruction buffer ready.