Method for manufacturing a power mos transistor

A process for manufacturing a DMOS transistor in accordance with the present invention including the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask is used to define the polycrystalline silicon gate. A layer of silicon dioxide (20) is then formed on the polycrystalline silicon gate. A second photolithographic mask is formed on the wafer. The second photolithographic mask defines the region where electrical contact is to be made to the polycrystalline silicon gate as well as where a deep body region (24) is to be formed in the semiconductor substrate. The deep body region is then formed. There­after, portions of the gate insulation layer not covered by the polycrystalline silicon gate are removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the polycrystalline silicon gate. A conductive layer 30 is formed on the wafer and photolithographically patterned, thereby leaving a gate contact and a source and body contact. A passivation layer 34 is then formed on the wafer, portions of which are photolithographically removed, thereby defining bonding pads. Of importance, the above-­described process uses only four photolithographic masking steps.