Memory access control circuit

Memory address signals (UA, LA) consisting of upper and lower address signals output from a memory access circuit (11) are retained by an address counter (12). An address comparator (16) compares the upper address signal retained by the address counter (12) and the next upper address signal (UA) from the memory access circuit (11). If these upper address signals coincide with each other, a multiplexer (13) is controlled by a timing control circuit (17), and only the lower address signal (LA) held by the address counter (12) is supplied to a memory (18) via an address bus (14). However, if the above upper address signals do not coincide with each other, the multiplexer (13) is controlled by the timing control circuit (17). In this case, the upper and lower address signals retained by the address counter (12) are multiplexed, and the multiplexed signals are supplied to the memory (18) via the address bus (14). The timing control circuit (17) also supplies a row address strobe signal (R AS) and a column address strobe signal (C AS to the memory (18).