Method for transmitting digital information in word blocks.

The present invention relates to a method of transmitting digital information word blocks. It relates more particularly to a coding and decoding technique in which transmission blocks are formed each composed of a series of digital information words and associated redundancy words, these redundancy words being constructed so as to detect and to correct, upon reception, packets of errors of great length, such as those encountered in digital recording on magnetic tape.

Conventionally, in the field of digital recording on magnetic tape, the information to be recorded is organized in frames each comprising a synchronization word, an identification word, one or more information words and a detector code d 'mistake. This error detecting code may not detect all errors.

To improve the error detection and correction capabilities, it is known to group the frames into sets of frames and to link the homologous information (ie the bits of the same rank) of the frames of the same set by simple mathematical relationships such as than the parity of the sum of the homologous bits. It is also known to form a transmission block by interleaving the series of frames of several linked sets so as to make the probabilities of errors on the frames of the same set independent of each other.

The article "Improved two channel PCM tape recorder for professional use" by K. Tanaka et al presented at the 64th congress of the Society of Audio Engineers, New York, November 1979 describes such a method of transmission in blocks of information words digital. The recording is carried out on a magnetic strip with 8 tracks, 6 of which are assigned to the information words and 2 to the redundancy words connecting the homologous information of the frames of the same set. These redundancy words are obtained using a code of the Reed-Solomon type.

This known method is not fully satisfactory because the Reed-Solomon code is a complex code. Detecting and correcting errors using this code therefore requires long and complicated calculations. Furthermore, the correction capacity of the method described, that is to say the probability of having an uncorrectable error, is proportional to p 'when the probability of having an error is equal to p. This correction capacity is not very high. The performance to complexity ratio therefore appears very average.

Transmission methods are known in which the probability of non-correctable error is proportional to p^*. Such a method is described in French patent application No. 2,467,510 entitled "Method and device for transmitting a sequence of digital information words".

In this method, the information words are separated into a sequence of even information words and a sequence of odd information words. These sequences are coded and transmitted with a time offset. This technique makes it possible to prevent a fault affecting the transmission channel, or the recording medium, from causing an error on two consecutive information words. An incorrectly recognized information word can thus be corrected or, if correction is not possible, interpolated from the previous information word and the next information word. This interpolation obviously only has a meaning if the successive information words are correlated, which is in particular the case in digital recording of a sound signal.

In this method, the transmission or recording format has a sliding structure, that is to say that the interlacing of the frames is such that it is impossible to define independent blocks as is the case in article cited. This results in a complication during electronic editing of sound programs, in particular due to the fact that the sliding structures are broken at the mounting point, which induces a loss of correction capacity.

The object of the invention is in particular to remedy the drawbacks of known transmission methods. The object of the invention is to provide a method of transmission in independent blocks, in order to be able to mount easily, in particular electronic mounting.

Another object of the invention is a transmission method capable of withstanding a loss of information occurring over the entire width of a magnetic tape over a length of approximately 5 to 10 mm, in the case where the recording is carried out in parallel on several magnetic tracks, and able to resist the complete loss of a magnetic track when the information is distributed for example on four magnetic tracks.

The invention also has as an objective a transmission method making it possible to correct at least 3 errors, that is to say a transmission method in which the probability of error which cannot be corrected is proportional to p^*, when the probability of having an error is equal to p.

Finally, the invention aims to detect and correct errors not detected by the error detector codes protecting the information and redundancy words.

Specifically, the subject of the invention is a method of transmitting in blocks of digital information words each having a length of n, bits, where n, is an integer, said method consisting in successively adding to the information words to be transmitted words of an error correcting code and words of an error detecting code, said method being characterized in that:<ul id="ul0001" list-style="none"><li>the error correcting code is a Hamming code by means of which k redundancy words are added to each sequence of n₂-k (n₂&gt; k) consecutive information words, said n₂-k information words forming with the k redundancy words a set of words called a linked set, each redundancy word having n, bits and, for each rank i, where 1 ≦ i ≦ n₁, the k bits of rank i of the redundancy words are redundancy bits of the n₂-k bits of rank i of n₂-k information words, said coding being carried out by a Hamming matrix whose column vectors are chosen so as to allow correction of a determined subset of the possible errors,</li><li>the error detector code is applied to sequences of information words or to redundant word sequences, the words of the same sequence belonging to different linked sets, each transmitted block comprising a plurality of sequences of n₂-k information words and associated code words detector and error corrector.</li></ul>

The redundancy words are preferably obtained by an extended Hamming code, that is to say of the form (2^m, 2^m-m-1), where m is an integer. But it is also possible to use a normal Hamming code of the form (2m-1, 2^m-m-1). In both cases, the code can be shortened. It is then respectively of the form (2^m -p, 2m-m-1-p) or form 2^m-1-p, 2^m-m-1-p). This shortening consists in forcing the value of p bits of each information word to a particular binary value, in general the value "0".

Preferably, a transmitted block comprises several interleaved linked sets. The homologous words in each set form a group. These homologous words are distributed in one or more frames each provided with an error detecting code, for example a code word of the CRC type.

Advantageously, to produce the k redundancy bits associated with n_Z-k bits of information, we use a Hamming matrix with n₂ columns and k rows of which all the column vectors are of odd parity.

The Hamming code does not allow all errors to be corrected, unlike the Reed-Solomon code generally used. However, it has the advantage over this latter of a simpler decoding, which is important if this decoding has to be done in real time.

The Hamming matrix is ​​chosen according to the errors that one wishes to be able to correct.

For the correction of long errors on a one-dimensional signal, a Hamming matrix is ​​chosen, of which any sequence of k consecutive column vectors forms a linearly independent system.

For the correction of periodic errors on a one-dimensional signal, which corresponds to long errors affecting one track among P when the signal is recorded on a ratio with P tracks in parallel where 1 / p is the frequency of errors in the one-dimensional signal, we choose a Hamming matrix of which any sequence of column vectors of index i, i + P, i + 2P, ..., i + (k-1) -P, where i is an integer, forms a linearly independent system.

The characteristics and advantages of the invention will emerge more clearly from the description which follows, given by way of illustration but not limitation, with reference to the appended drawings, in which:<ul id="ul0002" list-style="none"><li>FIG. 1 illustrates the format of a transmission block obtained according to the transmission method of the invention,</li><li>FIG. 2 represents an embodiment of a coding device for implementing the method of the invention,</li><li>FIGS. 3 and 4 illustrate two methods of storing groups of a block on a 4-track recording medium,</li><li>FIG. 5 illustrates an embodiment of the stage for recognizing valid frames of the decoding device implementing the method of the invention,</li><li>FIG. 6 illustrates an embodiment of the stage for calculating the syndrome of the decoding device associated with the method of the invention, and</li><li>FIG. 7 illustrates an embodiment of the error correction stage of the decoding device associated with the method of the invention.</li></ul>

We will first describe with reference to Figure 1 the structure of an emission block produced by the method of the invention.

A block constitutes an independent entity. It consists of a series of n2 groups G ,, G2, .... G_n2. Each group contains a determined number of words which are either information words or redundancy words. To reduce the risk of errors, these groups are organized in frames. By way of example, in the representation of FIG. 1, each group consists of a series of 8 frames T ,, T2, ... T_s, each frame comprising a synchronization word SY, an identification word ID noting the number of the frame in the group and the number of the group in the block, a series of 16 words M ,, M2, ... M ,, and an error-detecting code word. This identification word can possibly be extended to carry various information associated with the words M, to M,₆ of the frame, such as a scale factor.

This block contains 8 linked sets each formed by a sequence of n₂-k frames of 16 information words and k frames of 16 redundancy words. The elements (bit, word or frame) of a linked set are distributed at the rate of one element per group, these elements occupying homologous positions in each group. The N₂-k first groups contain for example the n2-k information words of each linked set and the last k groups the associated redundancy words.

The number of words per frame, frames per group and groups per block depend on the transmission channel or the recording medium used. In the case where the transmission is carried out in packets, it may be advantageous to match frame and packet. In the case of recording on a magnetic tape, two main types of errors can occur: long errors due to large mechanical incidents affecting the magnetic tape over a length of about 5 to 10 mm, and errors - short due to dust or a magnetic defect affecting the strip over a length of the order of a tenth of a millimeter.

Preferably, each frame has a length of the order of a tenth of a millimeter to avoid losing an entire group when there is a short error. The number of frames per group depends on the correction capabilities desired. For example, for n2 = 16, we have ak = 5 (extended Hamming code (16, 11)) and we can correct long errors spanning 5 consecutive groups, as we will see in the following description. In this case, each group must have a length of 1 to 2 mm, which represents about ten frames per group.

As described in the French patent application No. 2 467 510 already cited, it is advantageous, in the case of the recording of information words corresponding to a sound signal, to geographically separate the even information words and odd information words. This can be achieved in the context of the method of the invention by placing the redundancy frames in the middle of the block, between frames of even information words and the frames of odd information words.

FIG. 2 shows an embodiment of a transmission device for implementing the method of the invention. This device uses an extended Hamming code (16, 11) to associate 5 redundancy words with each sequence of 11 information words.

This device includes a set of 11 shift registers 2 ,, 22, ... 2 ,, of N bits connected in series, a coding circuit 4 to 11 inputs each connected to an output of a shift register 2 ,, 2₂, ..., 2 ,, and with 5 outputs, a set of 16 registers of the first input-first output type 6 ,, 62, ... 6.6, the first 11 being each connected to one of the shift registers 2 ,, - 2 ,, and the other 5 being connected at the input each to one of the 5 outputs of the coding circuit, a set of 16 framing means 8 ,, 8₂, ... 8₁₆ each linked to one of the registers 6 ,, 6₂, ... 6.6 and a means of multiplexing and mixing 10.

The device receives suites of 11 ^x N bits on the input of the shift register 2 ,. These 11^xN bits load shift registers 2 ,, 2₂, ... 2₁₁ of N bits each. Preferably, N is a multiple of the length n, of the information words. Thus, each register contains, at the end of the loading, an integer number of words. For example, we have N = 256 and n, = '16.

After the loading operation, 11 bits are available in parallel, one at the output of each register 2 ,, 22, ... 2 ,,. These 11 bits are homologous bits, ie of the same rank, of 11 different information words.

The coding circuit 4 performs, by means of a set of OU-EXCLUSIVE gates, the calculation of the 5 redundancy bits associated by Hamming coding with these 11 information bits. These 5 redundancy bits and these 11 information bits form a set of 16 linked bits which are stored, one bit per register, in registers 6 ,, 62, ... 6₁₆.

The Hamming coding of the 11 information bits is represented by a Hamming matrix with 16 columns and 5 lines. This matrix is ​​chosen according to the transmission or recording format of the blocks. By choosing a matrix whose column vectors are of odd parity, it is certain that any triplet of column vectors forms a linearly independent system. This allows at least three errors to be corrected in all cases, if the frame error detection codes have detected three erroneous frames.

In the case where the frame error detection codes have detected all the erroneous frames, the matrix can be optimized to correct up to 5 errors relating to consecutive linked elements (up to k in the general case, where k is the number of redundancy words).

The column vectors of the matrix can also be chosen as a function of the recording format of the block on the recording medium or of the transmission format of the block in the transmission channel. For example, in the case of the recording of a block on a magnetic tape comprising P tracks in parallel, it is advantageous to choose the column vectors such as the vectors of index i, i + P, i + 2P,. .. form a linearly independent system (or 1 ≦ i ≦ P). This ensures the correction of a track among P, for P sufficiently large.

In the case of the extended Hamming code (16, 11), chosen as an example, we can take the following Hamming matrix:<maths id="math0001"><img file="EP0204635A1_D0001.tif" /></maths>

This matrix is ​​such that:<ul id="ul0003" list-style="none"><li>- any triplet of column vectors forms a linearly independent system; it is possible to correct any triplet of frames recognized as erroneous by the error detector codes of each frame,</li><li>- any quintuplet of consecutive column vectors forms a linearly independent system; it is possible to correct the loss of 5 consecutive linked frames recognized as erroneous by the error detector codes of each frame,</li><li>-the row column vectors (1, 5, 9, 13), (2, 6, 10, 14), (3, 7, 11, 15) or (4, 8, 12, 16) form linearly independent systems ; it is possible to correct the loss of one of 4 tracks if the consecutive linked frames of a block are recorded cyclically on 4 magnetic tracks.</li></ul>

Returning to FIG. 2, the coding operation is repeated N times for each of the N sets of 11 bits contained in parallel in the shift registers 2 ,, 2₂, ... 2_". The registers 6 ,, 62, ... 6₁₆ each then contains N bits.

Each set of N bits is transmitted to a framing means which delivers by means of a frame containing a synchronization word, a frame identification word, N information or redundancy bits and an error detecting code. , for example a code word of type CRC.

The set of 16 frames delivered by the framing means constitutes a linked set. The multiplexing and shuffling means 10 can form a transmission block by simply multiplexing these frames. The block then includes a single linked set and each of the 16 groups in the block contains a single frame.

Preferably, the means 10 is provided with storage means for storing several linked sets and mixing or interleaving means for interleaving the frames of the linked sets in order to deliver a block of which each group comprises several frames. The purpose of this interleaving is to geographically separate the frames of the same linked set so as to limit the probability of losing several frames of the same linked set. These interleaving methods are well known to those skilled in the art.

The block produced by the device in Figure 2. and the structure of which has been described with reference to FIG. 1 is transmitted over a transmission channel or recorded on a recording medium. The recording medium may include one or more tracks in parallel.

In the case where the recording medium comprises a single track, it is analogous to a transmission channel. The block is recorded linearly according to the format of Figure 1.

In the case where the recording medium is a magnetic tape, it generally comprises several tracks in parallel. Each linked assembly of the block is then preferably distributed over several tracks of the magnetic strip.

FIG. 3 shows a recording format of 4 blocks G, H, J, K comprising the groups G, to G, 6, H, to H respectively.₁₆, J, to J, 6 and K, to K₁₆. Successive groups of the same block are arranged sequentially in the longitudinal direction of the strip and with a cyclic shift of a track in the transverse direction of the strip.

Thus, for each linked set, composed of 11 information words and 5 redundancy words distributed in the 16 groups of a block, 4 words appear on each track. These words are linked to independent column vectors if the coding of each block is obtained with the matrix H indicated above. In this case, the 4 words of a linked set recorded on the same track can be lost simultaneously without exceeding the error correction capacity, i.e. these 4 words can be corrected by the 12 words of all linked spread over the other 3 tracks.

The blocks G, H, J and K being independent, the coding of the invention makes it possible to correct a track of which all the information has been lost. The set of 4 blocks G, H, J, K has limits defined on the recording medium. This set itself constitutes a block. The structure in independent consecutive blocks on the recording medium is therefore preserved, which makes it possible to easily do electronic editing.

The correction property is linked to the fact that the words of a linked set which are recorded on the same track are associated with vectors linearly independent of the Hamming matrix. This property can be obtained in different ways.

As an example, another possibility consists in using a single block in which each group is divided into a number of frames p prime with the number of tracks on the magnetic tape and by recording the successive frames in the transverse direction of the tape. .

Such a format is represented in FIG. 4 for a block of 16 groups G, at G,₆ each comprising three frames T ,, TZ and T, recorded on a magnetic strip with 4 tracks. The 16 words forming a linked whole are divided into the 16 groups at the rate of one word per group; each word occupying a homologous position in each group is contained in a frame of the same index. With the matrix H chosen, in particular, the column column vectors (1, 5, 9, 13) are linearly independent. This makes it possible to correct in particular the frames G, T ,, G_sT ,, G₉T₁, and G_'3T, from T frames, from other groups. More precisely, the matrix chosen and the recording format of FIG. 4 make it possible to completely correct the information of a track from the other three tracks.

We will now describe a strategy for detecting and correcting errors when reading a block. This restitution of the information words transmitted or recorded is done in three stages:<ul id="ul0004" list-style="none"><li>a step of recognizing valid frames; this is mainly achieved by the error detection code,</li><li>a step of calculating the syndromes associated with each set of n2-k linked bits, each bit occupying a homologous position in n₂-k different frames,</li><li>a step of detecting errors not detected by the error detector codes and of correcting the information words as a function of the result of the syndromes.</li></ul>

These three steps are implemented in three circuits constituting a decoding device. An embodiment of each of these circuits is shown in FIGS. 5 to 7. For a better understanding of the invention, the method of the invention will first be described by successively considering the different cases of possible errors. This description is made for an extended Hamming coding (16, 11) defined by the matrix H whose value is recalled:

<maths id="math0002"><img file="EP0204635A1_D0002.tif" /></maths>

The decoding method of the invention at least makes it possible to correct the following errors:<ul id="ul0005" list-style="none"><li>-3 errors on any 3 bits of a set of linked bits recognized as invalid by the error detector codes of each frame,</li><li>-5 errors on 5 consecutive linked bits (ie associated with 5 consecutive column vectors of the matrix H) of a set of linked bits recognized as invalid by the error detector codes of each frame,</li><li>an error on a bit of a linked set, when no bit of the set has been invalidated by the error detector codes,</li><li>an error on a bit of a linked set, when only one other bit of this set has been invalidated by an error detecting code.</li></ul>

This method also makes it possible, with the matrix H chosen, to correct a large number of configurations in which any 4 or 5 bits (consecutive or not) of a linked set have been invalidated by the error detecting codes. The correctable error configuration rates are respectively 93% and 66% of the cases for 4 and 5 errors.

We note a₁, at₂, ... a ,, the linked bits or homologous bits of information words of a linked set. Suppose that the values ​​transmitted to₃, at₄, at_s, at₆ and a₇ have not been validated by the frame error co-detectors, i.e. they are likely to be erroneous, and note that₃, at'₄, at'_s, at'₆ and a^,₇ the values ​​received and (e₃, e4, e_s, e_s, e₇) the error vector.

We have :<maths id="math0003"><img file="EP0204635A1_D0003.tif" /></maths>

Consider the matrix H 'formed by the column vectors of rank 3, 4, 5, 6 and 7 of the matrix H:<maths id="math0004"><img file="EP0204635A1_D0004.tif" /></maths>

We have the relation:<maths id="math0005"><img file="EP0204635A1_D0005.tif" /></maths>where (s ,, S₂, S₃, S₄, S₅) is the syndrome defined by<maths id="math0006"><img file="EP0204635A1_D0006.tif" /></maths>We can deduce :<maths id="math0007"><img file="EP0204635A1_D0007.tif" /></maths>

The correction of the vector received (a '₃ at'₄, at'₅, at'₆, at'₇) to obtain the transmitted vector (a₃ a ,, as, as, a₇) is therefore reduced to the calculation of the inverse of the matrix H '. This inverse matrix only exists if the column vectors of H are linearly independent. In the example chosen, the matrix H 'is invertible and we have:<maths id="math0008"><img file="EP0204635A1_D0008.tif" /></maths>

It is therefore possible to correct the 5 detected errors contained in the received vector. The correction capacity stops there; it is not possible to correct errors not detected by the frame error detector codes.

When the matrix H 'is not invertible, the missing bits can be estimated by known masking techniques such as by interpolation between consecutive information words.

In the case where 4 bits of a linked set have not been validated by the frame error detector codes, the correction is carried out in substantially the same manner as in the previous case.

Suppose that the bits of rank 8, 9, 10 and 11 are invalidated. We consider the matrix H 'composed of the columns of rank 8, 9, 10 and 11 of the matrix H, that is:<maths id="math0009"><img file="EP0204635A1_D0009.tif" /></maths>and we have:<maths id="math0010"><img file="EP0204635A1_D0010.tif" /></maths>We are looking for H "such that:<maths id="math0011"><img file="EP0204635A1_D0011.tif" /></maths>Calculation gives: e<maths id="math0012"><img file="EP0204635A1_D0012.tif" /></maths>

The last equation of the system, i.e. 0 = s, + s₃ + ss is a compatibility equation. When this compatibility equation is not verified, it is because the frame error detecting codes have not detected all the errors. In this case, it is not possible to correct the words received. The erroneous bits can then be estimated by masking techniques.

These masking techniques are also used when the matrix H "does not exist.

The cases where 3, 2 or 1 bits of a linked set are invalidated are treated in the same way as the case where 4 bits of a linked set are invalidated, the only difference being that for 3 bits, 2 bits or 1 bit , there are respectively 2, 3 and 4 compatibility equations which must be satisfied.

The method of the invention also makes it possible to correct an error not detected by the error detector codes in a set of linked bits, when no error has been detected by these frame error detector codes. This situation occurs when all the bits of a linked set are validated and the associated syndrome is not zero.

The location of the error in the bits of the linked set is determined by the value of the syndrome. If the undetected error is unique, which is the most probable case, the syndrome is equal to the column vector of the matrix H whose rank is the same as that of the erroneous bit.

The method of the invention finally makes it possible to correct an error not detected by the frame error detecting codes when a bit of the set of linked bits has been invalidated.

Two cases arise depending on whether the bit not validated is right or false. These cases are distinguished by the parity of the syndrome. If the number of bits at "1 of the syndrome is odd, the non-validated bit is correct and the syndrome is equal to the column vector of the matrix H whose rank is identical to that of the erroneous bit not detected. If the number of bits at "1" of the syndrome is even, the non-validated bit is false and the syndrome is equal to the sum of the column vectors associated with the non-validated bit and the erroneous undetected bit. For example, if the syndrome is (1, 1, 0, 0, 0) and if the bit of rank 2 is not validated and erroneous, the column vector of the matrix H associated with the erroneous bit not detected is<maths id="math0013"><img file="EP0204635A1_D0013.tif" /></maths>

The erroneous bit not detected is therefore that of rank 11.

We will now describe an embodiment of the decoding device implementing the decoding method of the invention. This device comprises three circuits shown respectively in FIGS. 5 to 7.

The circuit of FIG. 5 is a circuit for recognizing valid frames in the received frames. This circuit has a classic structure.

It includes as input a demodulation and synchronization extraction means 12 successively receiving the different frames of a block. The demodulation operation makes it possible to detect the frame synchronization word in the event that it is transmitted by code violation. Such a technique is particularly advantageous in the case of a long interruption of the received signal, as is the case when a fault affects a magnetic tape, because it allows very rapid resynchronization of the means 12 on the received frames.

The means 12 delivers the frame identification word to an index recognition means 14, the information necessary for the detection of frame errors to a test means 16 and the N bits of the information or redundancy words to a buffer 18. The entry of data into the means 14, 16 and into the buffer 18 is timed by clock signals produced in a known manner by the means 12.

The useful information bits of the frame are validated by a validation means 20 if the identification word is recognized by the means 14 and if the error detector code indicates the absence of errors. The validation means can also decide to invalidate a frame based on other information which can be communicated by the means 12 such as an abnormal frame length or a code violation for the useful information bits. .

In this circuit, the frame is considered as an indivisible entity as regards its validity. If the error detection code of a frame detects an error, the frame is considered invalid and all the bits of this frame are marked.

According to an alternative embodiment, the error detector code invalidates only the bits of the frame considered to be erroneous. The processing for detecting and correcting errors using redundancy words is then a bit-by-bit processing, that is to say that this processing affects sets of n₂ bits, of which n₂-k of information and k of redundancy, extracted from n2 linked frames, and that this processing is repeated for each set of n2 bits which occupies a given rank in said frames.

It was previously indicated that this treatment notably includes a matrix inversion step. It is understood that the bit by bit processing of a frame can be long. It is therefore generally preferable to simultaneously validate or invalidate all the bits of the frame. Thus, the same matrix is ​​used for each set of n₂ bits; in this case there is only one inverse matrix calculation per set of linked frames. This results in a much higher processing speed. In addition, it should be noted that this frame processing is entirely suited to the probability of error on the recording medium since, as indicated above, the. the length of a frame is chosen to be of the same order of magnitude as the short errors (about 1/10 of a millimeter) on the recording medium.

Now back to Figure 5. When a frame is validated, it is stored in one of the 16 memories 22 ,, 22₂, ... 22,₆. These memories are shown separately for better understanding. In practice, these are areas of the same working memory. These memories are addressed by an address bus 24 by the validation means 20. A data line 26 connects the data output of the buffer 18 to the inputs of the memories 22, 22₁₆ ; the transmission of data in series on this data line is controlled by a connection 28 connecting the validation means 20 to the buffer 18. The addressing of the memories 22, to 22₁₆ is made so as to memorize the linked frames in the same order as in the framing means of the transmission device of FIG. 2.

The circuit of FIG. 5 finally comprises a register 30 connected to the address bus 24. This register is emptied before a block is received by the circuit. This is achieved by the validation means 20 by a control signal sent over a connection 32. Then, for each frame received, the validation means 20 sends data to said register 30 to mark the valid frames received.

The content of the memories associated with the invalid frames is irrelevant for the correction as long as the correction capacities are not exceeded. In addition, the memory loading strategy is linked to the masking methods possibly applied to the information transmitted. In the case of packet transmission, an erroneous or lost packet will be considered as an invalid frame.

The circuit shown in FIG. 5 corresponds to the case where the signal received comes from a single transmission channel or from a recording medium with a single track. In the case for example of a recording medium with several tracks, it is necessary to provide for each track an assembly consisting of the means 12, 14, 16, 18 and 20.

Memories 22, to 22₁₆ are accessed in writing by the frame recognition circuit of FIG. 5. They are also accessed in reading by the syndrome calculation circuit in FIG. 6. Several known solutions exist for achieving this double access. A first solution consists in providing two sets of memories 22, 22₁₆ and two registers 30, one set being accessible in reading and the other in writing during the reception of a block, the role of the two sets being swapped after each block. Another solution is to use memories with several ports organized in pages, each page being assigned to the frames of a block. This solution also makes it possible to ensure the deinterlacing function when the linked frames are interlaced with other frames, as is the case in the format of FIG. 1.

The circuit shown in FIG. 6 calculates the syndromes associated with the sets of 16 linked bits received. It compares these syndromes to zero and is able to memorize two different non-zero syndromes.

The possibility of memorizing two different syndromes does not cover all cases. This particular value of two memorizable syndromes is chosen here because it is sufficient to detect an error not detected by the frame error detecting codes and because the probability of having two errors not detected by the error detecting codes is very unlikely .

On the circuit of FIG. 6, the memories 22, to 22 have been reproduced,_s access to which is shared with the valid frame recognition circuit of FIG. 5. Each memory comprises a single data output which is connected to an input of a syndrome calculation means 34 with 16 inputs E ,, E2, ..., E, 6. This means delivers on 5 outputs S ,, S₂, S₃, S. and S_s the syndrome defined by the product between the Hamming matrix H and the vector of the 16 linked bits received.

An OR gate 36 whose inputs are connected to the outputs of the means 34 makes it possible to detect if the syndrome is zero. The circuit also includes two D type flip-flops 38, 40 in series, each flip-flop containing 5 bits, flip-flop 38 being connected to the output of the means 34 by a data bus 42. The two flip-flops are loaded simultaneously by the output signal from an AND gate 44, one input of which is connected to the output of the OR gate 36 and the other input of which is connected to the output of a comparison means_46 which delivers a signal at the high level when the syndromes delivered by the means 34 and the rocker 38 are different.

This set, in which the flip-flops are initialized to zero at the start of the block, makes it possible to store the first non-zero syndrome of a block in flip-flop 38 and, when a second non-zero syndrome is detected, to shift the first syndrome flip-flop 38 to flip-flop 40 and store the second syndrome in flip-flop 38. If a third non-zero syndrome is detected, there is a new shift in the content of flip-flops 38 and 40 and the first syndrome is lost. Generally, flip-flops 38 and 40 store the last two non-zero syndromes of a frame.

All the calculated syndromes, whether they are zero or not, are reintroduced into the memories 22.2 to 22.6 in replacement of the corresponding redundancy bits. This is achieved by means of the data bus 42, each data line of which is connected to a data input of the memories 22,_z at 22₁₆

At the end of the calculation of the syndromes of a set of linked words, three cases can arise:<ul id="ul0006" list-style="none"><li>-all syndromes are zero; flip-flops 38 and 40 contain zero values,</li><li>- a single syndrome is not zero; it is contained in scale 38,</li><li>-at least two different union girls are not void; two of them are contained in scales 38 and 40.</li></ul>

As explained above, the value of the syndrome associated with a set of linked bits and the state of validity of the frames each containing one of these linked bits makes it possible to correct the set of linked bits received in order to find the set of linked bits transmitted. This correction is implemented in the correction circuit, an exemplary embodiment of which is given in FIG. 7.

In this figure, the memories 22, 22.6, the register 30 and the flip-flops 38 and 40 which reproduce respectively sets of linked frames, frame validation bits and, where appropriate, non-zero syndromes have been reproduced. .

The circuit shown in FIG. 7 comprises a multiplexer 48, the inputs of which are connected to the outputs of memories 22, 22,, containing information bits. The output of this multiplexer is connected to an input of a parity operator 50 of the OU-EXCLUSIVE type. For each memory 22₁₂ at 22,₆ containing the syndrome bits, the data output is connected to the input of an AND gate 52,₂ to 52.6, the output of which is applied to an input of the parity operator 50. The second input of each AND gate is supplied by a bit of a 5-bit mask contained in a random access memory - (RAM) 54.

The circuit also includes a calculation means, such as a microprocessor 56, for calculating this mask as a function of the content of the register 30 and flip-flops 38 and 40. The microprocessor 56 is synchronized with a sequencer 58 which ensures the selection of the data in input of the multiplexer 48 and into the random access memory 54.

The processing carried out by the microprocessor 56 relates to a complete set of linked frames and comprises two successive stages: the search for erroneous frames not detected by the frame error detector codes, and the calculation of the correction coefficients forming the mask applied to the second inputs of AND gates 52,₂ at 52,₆.

In a first step, the microprocessor reads the content of register 30 to determine the number of invalid frames detected, that is to say the number of linked bits invalidated among the 16 bits of a linked set. If this number of invalid frames is greater than 5 (number of redundancy bits), the correction is impossible and the 11 information bits of the set of linked bits are estimated by masking techniques.

In the case where the number of frames declared invalid by the register 30 is equal to 0 or 1, the microprocessor examines the syndromes K, and K₂ contained in flip-flops 38 and 40 to detect a possible false frame which would not have been invalidated by its error detecting code.

Observation of syndromes K, and K₂ makes it possible to detect, in certain cases, two false frames not invalidated by the error detector codes. This eventuality is very unlikely and is not taken into account here.

If no error has been detected by the error detector codes, three cases are possible:<ul id="ul0007" list-style="none"><li>a) the K and K2 syndromes are zero; no frame is erroneous, the microprocessor 56 written in the RAM memory 54, for each frame, a mask consisting of 5 "0". This mask is applied to the inputs of AND gates 52.2 to 52.6: the parity operator 50 is transparent for the serial words delivered by the multiplexer 48.</li><li>b) syndrome K, has an odd number of "1" and syndrome K₂ is zero. There is then an invalid frame not detected by its error detecting code. This frame is the one associated with the column vector equal to the K syndrome.</li><li>c) syndrome K, has an even number of "1" or syndrome K₂ is not zero. There is then more than one invalid frame not detected by the error detector codes; the correction is not undertaken (this case is very unlikely).</li></ul>

Now consider the case where an error was detected by an error detecting code. Four cases arise:<ul id="ul0008" list-style="none"><li>a) the K and K syndromes₂ are zero. It is then considered that the error detected by the error detector code relates to bits of the frame other than linked bits, for example bits of the error detector code,</li><li>b) syndrome K, has an odd number of "1" and syndrome K₂ is zero. If the syndrome K, corresponds to the frame already detected by the error detecting code, ie if the syndrome K, is equal to the column vector of the Hamming matrix whose rank is the same as that of the invalid frame in the set of linked frames, there is no additional error. On the other hand, if the syndrome K, corresponds to another frame, it is considered that this other frame is invalid,</li><li>c) syndromes K, and K₂ are non-zero.</li><li>c1) if the syndromes are odd, they correspond to two different invalid frames. The correction is only undertaken if one of these two invalid frames is that detected by the error detecting code,</li><li>c2) if the syndromes are of different parity, the syndrome having an odd number of "1" results from an error on the associated frame, ie whose rank corresponds to the column vector of the matrix equal to the syndrome, and the syndrome having a even number of "1" results from an error on two different frames. The second invalid frame is associated with the column vector equal to K, + K₂. The correction is only undertaken if one of the two frames found invalid by the K and K syndromes₂ is equal to the detected frame invalidated by the error detecting code,</li><li>d) in the other cases, there is more than one error not detected by the error detector codes and the correction is not undertaken. It should be noted that this is a particular strategy which is linked to the fact that the probability that two errors have not been detected by the error detector codes is very low. However, only from a mathematical point of view, the correction remains possible, in this case, in a certain number of error configurations.</li></ul>

Observation of syndromes K, and K₂ therefore makes it possible to modify, if necessary, the content of the register 30 containing the state of validity of each frame.

The next step consists for the microprocessor 56, in forming the matrix H ′ with c (c ≦ 5) columns and 5 lines formed by the c column vectors associated with the c invalidated frames classified by increasing rank. This matrix H 'is transformed in a conventional manner, for example by triangulation, to produce a matrix H'^-1 with 5 columns and 5 rows.

If this is not possible, this can happen when there are 4 or 5 errors; the correction is not undertaken. In the case where the operation is possible, a relationship is obtained linking the errors of the erroneous frames to the 5 frames of syndromes. This relation is expressed, for each frame, by a set of 5 binary correction coefficients which constitute a line of the matrix H '^-1 or H ". For validated frames, the correction coefficients are equal to" 0 ".

The sequencer 58 simultaneously controls the multiplexer 48 and the RAM memory 54 to deliver to the parity operator 50 a bit of a frame and the associated correction word, this word being equal to the syndrome multiplied by the mask formed by the 5 coefficients correction binaries.