Electronic circuit for connecting a processor to a high-capacity memory

The present invention relates to an electronic circuit for connecting a processor to a high-capacity memory in which the processor is provided with an address bus having a given width, for example 16 bits, for addressing the memory. In that way the processor can directly address a given number of bytes at a time, for example 64K, but it is desirable for it to be able to address a memory which is larger than this.

It is known from US-A-4 037 215 to provide a processor with means for connecting it to a segmented memory, in which the memory segments each have a capacity such that they can be directly addressed by means of a first portion of the address supplied by the processor. A translator or auxiliary memory is interposed between the processor and the memory and comprises a plurality of registers, subdivided into groups with each group comprising a number of registers which is equal to the number of memory segments which can be addressed at one time by the processor. In use one of the groups is selected and the registers in the selected group are addressed by a second portion of the address supplied by the processor. The registers identify which of the segments of the processor are to be addressed.

To change the segments which are addressed, a different one of the register groups can be selected. Sufficient bits are required to address the selected one of the groups of registers. The information in the registers can also be changed.

The present invention provides an improved circuit for connecting a processor to a high-capacity memory as defined in claim 1 below. Advantageous features are set out in the dependent claims.

It is thus not necessary to provide for selection bits to select a group of registers, and the whole of the address output of the processor can be used to address the memory. However, changing (or loading) the content of the registers is possible at any time by performing a simple modification sequence to read information from the predetermined memory segment.

These and other features of the invention will be clearly apparent from the following description of a preferred embodiment which is given by way of non-limiting example with reference to the accompanying drawings in which:- <ul id="ul0001" list-style="none"><li>Figure 1 is a block diagram of an electronic circuit embodying the invention, and</li><li>Figure 2 is a block diagram showing the map for addressing of the high-capacity memory of the circuit shown in Figure 1.</li></ul>

Referring to Figure 1, an electronic circuit 10 embodying the invention provides the connection between a processor 20 and a memory 21 having a high capacity, for example 1 Megabyte.

The processor 20 may be of any known type but in the embodiment described herein reference will be made to a Zilog Z80 microprocessor which comprises an 8 channel data bus 22 for bi-directional transfer of the 8 bit data (D0-D7), and a 16 channel address bus 23 for addressing the memory 21 and the devices connected thereto, by means of 16 addresses (AO-A15).

The high-capacity memory 21 (Figures 1 and 2) is connected to the processor 20 by means of the data bus 22 and is subdivided into 256 segments (SEG 0 - SEG 255), each of which has a capacity of 4 Kbytes. The memory 21 can be addressed by twenty address bits MAO-MA19, the 12 least significant of which (MAO-MA11) are connected by means of two portions 24 and 26 of the address bus 23 directly to the 12 least significant address bits (AO-A11 ) of the processor 20.

The circuit 10 further comprises a random access memory 30 (RAM) formed by 16 registers (RO-R15), each of 8 bits. The RAM 30 is associated with a first decoder 31 whose input, by means of a portion 27 of the bus 23, receives the addresses A12, A13, A14 and A15, and whose outputs are capable of enabling the registers RO-R15 one at a time.

The RAM 30 is also connected to the processor 20 by means of the data bus 22 for receiving the data DO-D7 and is capable of generating eight signals RA12-RA19 which, by means of eight corresponding NAND gates 32, generate the eight most significant address signals MA12-MA19 for the memory 21, to which they are passed by means of a bus 28.

The circuit 10 further comprises a second decoder 35 which is capable of generating an enabling signal CS for the first decoder 31 and whose input receives the addresses AO-A7 from the processor 20 and a signal WRE which is generated by an AND gate 36. The inputs of the AND gate 36 receive from the processor 20 a signal WR which is indicative of the fact that a certain item of data (DO-D7) is to be written or stored in one of the memories, and a signal IORQ which is indicative of the fact that the addresses AO-A7 are intended for an input/output unit for data input or output operations.

The NAND gates 32 are enabled by a signal RDE generated by a flip-flop 38 which has a set input connected to the output of an AND gate 39 and a reset input connected to a general reset signal RS which is also passed to the processor 20.

The AND gate 39 receives from the processor 20 the signal IORQ and a signal RD which is indicative of the fact that data are to be read from one of the memories or an input/output unit.

The mode of operation of the circuit 10 as described hereinbefore is as follows:

Initially, by means of the reset signal RS, the flip-flop 38 is reset in such a way as to put the signal RDE at level 0, and consequently all the outputs MA12-MA19 of the gates 32 at level 1. In that way the first of the segments (SEG 0) of the memory 21 is addressed, being the segment containing the items of information relating to the number of the other segments, among the total of 256, to be associated with the processor 20 in this first phase.

The processor 20 reads the items of information stored in the segment SEG 0 and "writes" in each of the registers R00-R15 of the RAM 30 the value of the sixteen memory segments 21 with which it is successively connected. For each cycle in the RAM 30, the signals WR and IORQ are brought to level 1 so that the signal WRE, going to level 1, enables the decoder 35 to generate the signal CS which in turn enables the decoder 31. The addresses A12-A15 which are combined together address one at a time the registers RO-R15 in such a way that, when the data DO-D7 arrive from the processor 20, they are stored in the addressed register.

During that writing phase, the signal RDE remains at level 0 and maintains at level 1 the outputs MA12-MA19 of the NAND gates 32.

When the processor 20 is to perform a cycle of reading the RAM 30, it brings to level 1 the signals RD and IORQ which, by means of the AND gate 39, set the flip-flop 38, sending the signal RDE to level 1. In that way, with the RAM 30 being addressed by means of the addresses A12-A15, the registers RO-R15 are read. The content of the each register RO-R15 comes out of the RAM 30 by means of the eight signals RA12-RA19 and, by way of the NAND gates 32, becomes the address code for one of the 256 segments of the high-capacity memory 21.

In that way the processor 20, with 16 bit addressing (A0-A15), manages to be connected to each cell of any one of the 16 segments of the memory 21, which were previously selected among the total of 256 segments.

At any time moreover the processor 20 is capable of changing the content of the registers RO-R15 of the RAM 30, effecting a writing cycle in the manner described hereinbefore, and thus being connected to other segments of the memory 21.

It will be clear therefore that the processor 20, while being capable of addressing only 64 Kbytes of memory 21 at a time, has the entire 1 Megabyte memory available.

An electronic circuit of the type described hereinbefore may be used in any data processing or word processing units or in electronic typewriters provided with processors.