Carrier recovery circuit for digital transmission systems.

0001The invention relates to a circuit for recovering the carrier wave of a digitally modulated wave with phase symmetry 2n / M, where M is the order of symmetry, provided with automatic and rapid acquisition means, comprising an oscillator. voltage-controllable having an output delivering said carrier wave and a control input to which an error signal ε (φ) is applied in order to modify the phase of the oscillator and subject it to that of the digitally modulated wave, this being introduced:<ul id="ul0001" list-style="none"><li>. on a first track comprising in series:<ul id="ul0002" list-style="none"><li>- a demodulator receiving the modulated wave and the output of the oscillator, and delivering a demodulated signal X₁,</li><li>- a low-pass filter acting on the demodulated signal X₁ and delivering a filtered signal X,</li><li>means of reconstruction of a signal X and of determination of the error e_x = XX between signals X and X,</li></ul></li><li>. on a second channel comprising in series:<ul id="ul0003" list-style="none"><li>- a 90 ° phase shifter of the oscillator signal</li><li>- a demodulator receiving the modulated wave and the output of the phase shifter and delivering a demodulated signal Y_i,</li><li>- a low-pass filter acting on the demodulated signal Y₁ and delivering a filtered signal Y,</li><li>means for reconstructing a signal Y and for determining an error ey = YY between the signals Y and Y, the two channels coming together using a phase comparison device which receives the signals X, e_x, Y, ey and a base clock H (recovered symbol clock), which delivers a comparison signal S, as well as a variable-rate sampling clock which reproduces the base clock H, excluding certain edges, the comparison signal entering a flip-flop under the control of the sampling clock, the output of the flip-flop being connected to an amplifier filter which delivers the error signal ε (ø) for controlling the oscillator, the representation of the signals in phase and in quadrature defining the states of a constellation.</li></ul></li></ul>

0002The invention also relates to devices where a carrier wave recovery circuit finds its application, such as digital transmission devices, in particular those for which information, after having been transmitted by modulation of an electromagnetic wave is restored. by coherent demodulation. These devices find their application in data transmission modems, radio-relay systems, spatial or optical communications systems in the case of heterodyne links.

0003To carry out the coherent demodulation, the phase of the carrier wave is generally restored using an oscillator placed in a carrier recovery loop. This oscillator is voltage controlled by a filtered version of the output signal from a phase comparator which detects the phase error between the oscillator and the transmission carrier wave.

0004For digital modulations with a large number of states, the phase difference between the oscillator and the carrier wave must imperatively be limited to small values. The noise band of the recovery loop is then reduced using narrow low-pass filtering. This reduction results in low phase noise, and also a considerable reduction in the acquisition range. To overcome this drawback, acquisition aid devices are used.

0005Among these devices, frequency discriminators are commonly used which generate a voltage which depends on the frequency difference between the oscillator and the carrier wave such as that described in French patent application No. 2,552,959. This application relates a carrier recovery circuit for digital modulations of 2π / M symmetry in which variable rate sampling of the output of the phase comparator transforms it into a frequency discriminator. This property is obtained by eliminating the zero transitions of the phase comparator output which occur when the phase error between the oscillator and the carrier wave is equal to X + 2k^w, MM where k and M are whole numbers.

0006However, in the presence of digital amplitude modulations of two multi-state quadrature carriers, the frequency discriminator described in this application has drawbacks, its gain being degraded, since it remains on the sampled output of the phase comparator transitions by zero which are taken into account, and which do not correspond to a zero phase error. Indeed, this discri_- frequency timer generates a sampling clock, from a base clock H, in which certain active edges of the latter are eliminated. This elimination occurs when zero transitions are detected for which the phase difference between the oscillator and the carrier wave is equal to Ξ + 2kπ.

0007MM But experience shows, in phase and amplitude modulations, that there are other zero transitions at the output of the phase comparator which defeat a correct acquisition of the carrier wave. For example in the case of a 16 QAM modulation, the output of the phase comparators commonly used have zero transitions while the phase difference is equal to 8 = Arc tg 1/3 for the states (3,1) , (-1.3), (-3, -1), (1, -3). Other states exhibit similar behavior. In addition, with a greater number of modulation states, the number of these undesirable zero transitions will increase, and this results in a deterioration in the performance of the discriminator.

0008The object of the invention is therefore to avoid this degradation by eliminating the consideration of all the undesirable zero transitions.

0009For this, the invention as defined in the preamble is remarkable in that the carrier wave recovery circuit has a phase comparison device which includes means for selecting the points received using selection zones located around certain diagonal states of the constellation so that the circles passing through the non-diagonal states do not intersect said selection areas, and that the areas drawn around the points of type (i1, ± 1) do not come into contact with the axes OX, OY of the constellation, and means for generating the sampling clock in which all the active edges have been eliminated, capable of validating the zero transitions of the signal for comparing the output of the phase comparator which does not correspond to a phase difference equal to 2kπ / M, where k and M are whole numbers.

0010This device is based on the memorization of the sign of the output of the phase comparator when the absolute value of the phase difference exceeds a certain value. This storage takes place in a flip-flop whose output has a voltage which remains constant between two zero transitions recognized as valid. This constant voltage has the same sign as the frequency difference between the oscillator and the carrier wave.

0011To carry out the storage, zones are defined for which the phase error at the output of the comparator is canceled out only once, the sign of the output of the phase comparator remaining identical to the sign of the phase error.

0012This carrier wave recovery circuit uses a phase comparator which has the following properties:<ul id="ul0004" list-style="none"><li>- its characteristic is canceled for a zero phase error;</li><li>- Its characteristic is periodic with a period 2π / M where M is the order of symmetry of the modulation.</li></ul>

0013The invention finds its application for digital modulations of phase symmetry 2n / M where M is the order of symmetry of the constellation. Thus, a 4-state phase modulation has a 4-order symmetry, for an 8-state phase modulation the symmetry is of an 8 order, for a phase and amplitude modulation of two carriers in quadrature MAQ 16, symmetry is of order 4.

0014However, the invention has its decisive advantages in the case of amplitude and phase modulations for which the phase differences between certain points of the constellation are less than the 2r / M symmetry. Thus in MAQ 16 modulation the symmetry is π / 2, but the phase difference between the states (1,1) and (1,3) is π / 4 - arc (tg.1 / 3) therefore less than w / 2.

0015During the carrier acquisition period, the digitally modulated wave will be able to present all the points of the constellation. The invention therefore eliminates all the points received which are likely to cause an erroneous acquisition.

0016Thus, the carrier wave recovery circuit according to the invention has means for selecting the points received using zones located around certain states of the constellation.

0017This selection is made by determining whether or not the points received belong to areas with the following properties:<ul id="ul0005" list-style="none"><li>- any point received in these zones has a phase difference with the transmitted point, such that the absolute value of this phase difference remains less, to within 2ku / M, than a chosen value, which makes it possible to eliminate the transitions by zero to ku / M;</li><li>- any signal reconstructed from a point received in these areas is identical to within 2kπ / M, with the corresponding transmitted signal.</li></ul>

0018Thus, the information taken into account is only that provided by the points received in these zones. In MAQ modulation these zones can be formed by squares centered on diagonal states of the modulation. More generally, the zones can consist of a closed contour, bounded in X and Y, surrounding these diagonal states.

0019To determine the membership of these zones, then the taking into account of the information relating thereto, the invention constructs a phase comparison device which is inserted in a circuit for recovering a carrier wave. For this, the digitally modulated wave is introduced simultaneously on two demodulators, one also receiving the output of the oscillator and the other this same output but after having passed through a phase shifter of t / 2 and respectively delivering the demodulated signals X, and Y₁. These are filtered and respectively provide the signals X (in phase) and Y (in quadrature) from which reconstructed signals X and Y are obtained. The errors e_x and ey between the filtered and reconstructed signals, as well as the X and Y signals, are introduced into the phase comparison device which delivers a binary signal indicating the sign of the characteristic of the phase comparator for the angle φ appearing between the modulated wave received and the oscillator wave. This binary signal is introduced into a flip-flop under the control of the sampling clock which only includes the desired active edges. The output of the flip-flop is filtered then amplified to deliver the control signal ε (φ) for the oscillator. The comparison device generates a signal P_z characterizing the selection of the zones which is used to construct the sampling clock.

0020The invention will be better understood using the appended drawings, given by way of nonlimiting examples, and which represent:<ul id="ul0006" list-style="none"><li>Figure 1: the representation, in a quarter of a plane, of the constellation of an MAQ wave 16.</li><li>Figure 2: the representation, in a quarter of a plane, of the constellation of an MAQ 64 wave.</li><li>Figure 3: a representation of the characteristic of the phase comparator and the variations, with the phase, of the output signal of the phase comparator before and after storage in a flip-flop.</li><li>Figure 4: a representation of the variations, with the phase, of the output signal of the phase comparator, for certain states of the constellation in MAQ 16.</li><li>Figure 5: a block diagram of the carrier wave recovery circuit according to the invention.</li><li>Figure 6: a logic diagram of the phase comparison device according to the invention in the case of square areas centered on the states of the constellation.</li><li>Figure 7: a logic diagram of the phase comparison device according to the invention in the case of eccentric square zones on the states of the constellation.</li></ul>

0021Figure 1 represents in a quarter of plane XOY the part of constellation MAQ 16. It presents four states (1,1), (3,1), (1,3), (3,3) in this quarter of plane. For the total plane this constellation has a symmetry 2π = π. It pre-M 2 feels a minimum phase difference such that<maths id="math0001" num=""><img file="EP0200271A1_D0001.tif" /></maths>

0022Lines 41, 42 and axes OX and OY define the decision zones for the states of the quarter plane shown in FIG. 1.

0023According to the phase variation of the incident modulated wave with respect to the oscillator, for a particular state of the constellation, the received point will move on a circle centered in 0 and passing through the particular state. On the circle 40 appears a position A which corresponds to the smallest distance between the circle 40 and the state (3.3). A detected state located at A is interpreted as being a state (3.3) whereas it is a state (3.1) or a state (1.3) with a phase difference. For this, the invention defines around each state an acquisition zone 43 which does not come into contact with the circle 40 for the example chosen. In the case of MAQ 16 modulation, the states selected for acquisition are states (1,1) and (3,3) because indeed the phase difference between the 4 type states (± 1, ± 1), as well as between the 4 type states (± 3, ± 3), is π / 2. On the other hand, between the 8 type states (± 1, ± 3) and (± 3, ± 1) the minimum phase difference is 2.Arc tg (1/3) = 36 ° 87. A β phase error, between transmission and reception, greater than around 19 ° for example, brings a point (+1, +3) into the decision area of ​​the point (-1, +3). Consequently with the points (i1, ± 3) and (± 3, ± 1) a phase error of β cannot be distinguished from an error 2. (Arc tg1 / 3) -β or from a phase error 2α-β (for a, see Figure 1). When issuing a state (+3, +1) and for a phase error of + 48 ° for example, the point can be detected as a state (+1, +3) with an estimated phase error at -5 °. Similarly for a state (3, -1), with a phase error of + 48 ° for example, the point can be detected as a state (+3, +1) with a phase error estimated at + 11 °. Thus, if we set ourselves to take into account the phase error, modulo π / 2, only when it is less than 15 ° for example, it is clear that we cannot take into account the non-states diagonals, since it would be impossible to determine whether the detected phase error is within the predetermined interval.

0024The invention therefore selects the states which have the same symmetry as the modulation itself and defines around each state an area where the acquisition can be carried out. The acquisition area 43 is centered on the selected state. On the other hand, the acquisition area 44 is eccentric.

0025Figure 2 shows the same type of representation for a 64 QAM modulation. In this case the acquisition problems are much more numerous due to the existence of a large number of states which can lead to a disturbance of the mechanism d 'acquisition. In this case, the states selected are the states (1,1), (3,3), (7,7) which have an order of symmetry identical to that of the modulation itself. The state (5, 5) cannot be selected because it is on the circle which passes through the states (1, 7) and (7, 1). Around each of the selected states, an acquisition zone 43 or 44 is defined in which the acquisition must take place, this acquisition zone not coming into contact with the circles passing through the other states.

0026FIG. 3 shows in B the characteristics of a phase comparator for a phase between -w / M and + π / M. On either side of point o (zero phase difference), the phase comparator delivers a voltage as a function of the phase difference which makes it possible to control the frequency of the oscillator. The comparator output voltage is shown in C. The average value of this output voltage is zero. To effect the frequency correction of the oscillator, the value of the output voltage of the phase comparator is memorized using selection and acquisition means which characterize the invention. When the absolute value of the phase difference exceeds a value 8₀, which corresponds to crossing the selected acquisition area, an acquisition circuit stores the state of the comparator output signal. Such a stored signal is represented in D, its average value is no longer zero. It allows the frequency correction of the oscillator. The curves C and D in FIG. 3 are representative of a positive frequency difference, that is to say a frequency of the modulated wave carrier greater than the frequency of the oscillator. For a negative frequency difference the curves C and D have an inverted shape.

0027FIG. 4 represents, in the case of an MAQ 16 modulation, the state of the output signal of a phase comparator for a phase difference varying from 0 to v / 4. This domain is sufficient because the characteristic of the comparator is periodic of v / 2 and is odd. The comparator considered is a comparator of a conventional type which delivers an output signal S such that S = -sgn (ey) .sgn (X) if sgn (ey) .sgn (X) is of opposite sign to sgn (e_x) .sgn (Y), and such that S keeps the value present at the previous instant otherwise. Such a comparator will deliver a signal which, examined over a half-period (O, w / 4), will present certain singularities depending on the state of the constellation studied. Thus by limiting the analysis to the half-period (0, π / 4), that is to say half of the symmetry, we note that certain states will lead to transitions by zero of the output of the comparator but for which the error of phase is not zero. Thus Figure 4 shows that a state (3,1) can lead to zero transitions of the comparator output which must be eliminated to carry out the acquisition.

0028FIG. 5 represents the block diagram of the carrier wave recovery circuit. The digitally modulated wave arrives at the input connection 5 and is subdivided into two channels 10 and 20 respectively in phase and in quadrature with the wave of the oscillator 17. The latter delivers its signal directly to the demodulator 11 of the channel in phase, and also to the demodulator 21 of the quadrature channel through the r / 2 phase shifter 24. The outputs of the demodulators 11 and 21 are filtered respectively in the low-pass filters 12 and 22 having the output signal respectively X and Y. These signals penetrate into reconstruction circuits, respectively 13 and 23, which respectively deliver the errors e_x = XX and ey = YY between the filtered signals X and Y and the reconstructed signals X and Y.

0029Error signals e_x and ey as well as the filtered signals X and Y enter the phase comparison device 30, which also receives the base clock H and which delivers the binary comparison signal S and the sampling clock. These two signals enter a flip-flop 14 the data input of which receives the comparison signal S and the clock input receives the sampling clock from the selection and comparison means 31 and from the generation means 32 constituting the phase comparison device 30 which contains the invention. The output signal from flip-flop 14 passes through a low-pass filter 15 and then through an amplifier 16 to supply the control signal ε (φ) which controls the oscillator 17.

0030FIG. 6 represents the logic diagram of an exemplary embodiment of the phase comparison device 30 according to the invention in the case of square zones centered on the diagonal states of a constellation MAQ 16. It receives as input the signals X, Y, e_x = _X-X, ey = YY and the basic clock H. It delivers the signal S and the sampling clock He. Signal Y enters:<ul id="ul0007" list-style="none"><li>- a comparator 61 at threshold -2 which delivers the signal Ty</li><li>- a comparator 62 at threshold 2 which delivers the signal Ry</li><li>- a comparator 63 at threshold 0 which delivers the signal Qy.</li></ul>

0031The signals Ty, Ry, Qy enter a selection circuit 64 which performs the logic operation defined by Ay = Ry.Qy + Ty.Qy, where the symbol (.) Represents the logic function AND and the symbol (+) represents the OR logic function. This is done using an ET 64 gate₂ which receives Ry and Qy, from an inverter 64₃ which delivers Qy, reverse signal of the input signal Qy, an AND gate 64₁ which receives signals Ty and Qy, the outputs of gates ET 64₁ and ET 64₂ entering a door OR 64₄ which delivers the Ay signal.

0032Signal X is treated in the same way as signal Y. It enters:<ul id="ul0008" list-style="none"><li>- a comparator 51 at threshold -2 which delivers the signal T_x</li><li>- a comparator 52 at threshold 2 which delivers the signal R_x</li><li>- a comparator 53 at threshold 0 which delivers the signal Q_x.</li></ul>

0033T signals_x, R_x and Q_x enter a selection circuit 54 which performs the logic operation defined by A_x = R_x.Q_x^{+ T}x.Qx.

0034This is done using an ET 54 gate₂ Who receives _Rx and _Qx, of an inverter 54₃ who delivers Q_x, signal opposite of the input signal Q_x, an AND gate 54₁ who receives the signals <o>T</o>_x and <o>Q</o>_x, the outputs of doors ET 54₁ and 54₂ entering a door OR 54₄ which outputs signal A_x.

0035On the other hand, the signal ey enters:<ul id="ul0009" list-style="none"><li>- a comparator 65 at threshold -a which delivers the signal Ny</li><li>- a comparator 66 with threshold a which delivers the signal My The signals Ny and My enter an AND gate 67₅ which performs the logical operation defined by P_y = N_y.<o>M</o>_y.</li></ul>

0036In the same way the signal e_x enters :<ul id="ul0010" list-style="none"><li>- a comparator 55 with threshold -a which delivers the signal N_x</li><li>- a comparator 56 with threshold a which delivers the signal M_x. N signals_x and M_x enter an AND gate 57₅ which performs the logical operation defined by P_x = N_x.^Mx.</li></ul>

0037Signals A_x and Ay enter a NON-OR-exclusive gate 70 whose output enters, with the signals P_x and Py, in an AND gate 71 which delivers the signal P_z. This signal P_z indicates whether the point (X, Y) received belongs to or does not belong to the particular zones which one wishes to detect.

0038The P signal_z and the base clock H enter an AND gate 32 which delivers the sampling clock He.

0039On the other hand we determine the sign of the signals e_xi ey, X, Y in order to determine, at a given instant, the output signal S such that:<maths id="math0002" num=""><img file="EP0200271A1_D0002.tif" /></maths>if e_X.Y is of opposite sign to ey.X, and such that S keeps the value of the previous instant in the opposite case. For this we bring in<ul id="ul0011" list-style="none"><li>- the ey signal in a comparator 81</li><li>- the signal e_x in a comparator 83.</li></ul>

0040The outputs of comparators 81 and 53 enter an exclusive OR gate 85 and the outputs of comparators 83 and 63 enter an exclusive OR gate 86. The outputs of doors 85 and 86 enter an exclusive OR gate 87 whose output enters, with the base clock H, into an AND gate 88 which delivers a signal which serves as a clock for a flip-flop 89 whose input data come from the output of the OR-exclusive gate 85. This flip-flop 89 delivers an output signal S which enters the data input of flip-flop 14 of FIG. 5, the clock of the latter being constituted by the sampling clock.

0041FIG. 7 represents the logic diagram of an exemplary embodiment of the phase comparison device 30, according to the invention, in the case of zones eccentric on the diagonal states of a QAM constellation 16.

0042A first difference lies in the fact that the signals Ny, My and Qy enter a selection circuit 67 which performs the logical operation defined by:<maths id="math0003" num=""><img file="EP0200271A1_D0003.tif" /></maths>

0043This is done using an ET 67 gate₂ which receives Ny and Qy, from an inverter 67₃ which delivers Qy, reverse signal of the input signal Qy, an AND gate 67₁ which receives the signals My and Qy, the outputs of the gates ET 67₁ and 67₂ entering a door OR 67₄ which delivers the Py signal.

0044A second difference lies in the fact that the signals N_x, M_x and Q_x enter a selection circuit 57 which performs the logical operation defined by:<maths id="math0004" num=""><img file="EP0200271A1_D0004.tif" /></maths>

0045This is done using an ET 57 gate₂ who receives N_x and Q_x, of an inverter 57₃ who delivers Q_x, signal opposite of the input signal Q_x, an AND gate 57₁ who receives the signals <o>M</o>_x and <o>Q</o>_x, the outputs of doors ET 57₁ and 57₂ entering a door OR 57₄ which delivers the signal P_x.

0046All the signals are then processed in a similar manner to that used for FIG. 6.

0047Obviously the logic diagrams given in FIGS. 6 and 7 are nonlimiting examples and any other logic diagram corresponding to the object of the invention also forms part of it.