Data capture logic system.

This invention relates to data capture logic systems for use with very large scale integrated circuit chips, also known as VLSI chips, for example, to provide test and error checking functions in addition to the operational functions of the chip. A data capture logic system according to the present invention may be located on a VLSI chip and programmed to store certain operands from a VLSI logic function circuit during operation, as well as storing operands at different time cycles during operation so that the functioning of the circuit may be analysed. The present invention has particular application to VLSI chips that have a pipeline or pipe sequence of operations.

The increasing complexity of logic design as implemented on VLSI chips has created problems with respect to the fact that large amounts of the circuitry contained within a single VLSI array cannot be directly sampled or tested. With very large arrays, a substantial number of logic or functional steps can occur between input operands and output operands so that if some types of error are present in the output operand, it is difficult to determine where or in what manner the error came about. The ability to test or otherwise determine the functioning of a logic circuit in a VLSI array is especially important during the design check-out process so that internal logic can be sampled to verify the logic system, as well as to identify "weak" areas in the array design or layout which might be especially sensitive to error development during the life of a VLSI chip. Such "weak" areas may have poor tolerance or margins to voltage fluctuation, timing variations or other factors. Therefore, it is important in VLSI logic design to create an internal system which can test or sample preselected, important data points internal to the logic structure. Because some errors are intermittent and do not occur under all conditions, but only under certain conditions, it is especially difficult to diagnose these errors in large systems. Diagnosis of intermittent errors can be especially aided if the failing input data at various positions internal to a logic circuit can be captured along with the input operands to the logic structure. Similarly, because input and output connections or pins to VLSI logic chip arrays are limited in number and primarily used for operational purposes, tests for error function logic must be allowed to take only a very small number of the input and output pins that can be placed on a VLSI chip.

Error checking and test logic is extremely important in VLSI design and, consequently, there is a substantial amount of prior art directed to this problem.

One known technique for analysing VLSI logic design and error functions is known as the level sensitive scan design in which a substantial number of registers are combined with the logic system on a VLSI chip so that on demand the contents of all of the registers may be delivered in a continuous serial fashion to an output pin of the chip. This system requires the stringing together of a significant number of operand registers in the VLSI chip in order to output a substantial body of serial data. All of this data is captured at the same time and represents a burden to analyse all of the particular operands and unnecessary information captured by this method. Also, this method does not capture the correct input operands to correlate with operands in various processing steps.

Another method of VLSI chip design is represented by US-A-4233682 which shows that a fault detection and isolation system can be designed using a substantial amount of duplicate logic in the system design combined with comparators at various stages of processing. As long as the comparators show that the processing steps are producing identical operands, then no error output is indicated. However, when the operands at a particular point in the logic function are not identical, then an error output is indicated and the correct operand is selected for output if it is possible to determine which operand is correct. This system creates a burden in the logic design of duplicating all essential functions of the logic together with comparator logic for comparing the operands at various stages of processing. This design and the comparator logic will penalise the speed performance of the circuit. While this duplication of logic may be necessary in some applications, it should not be necessary for all applications. Also, this duplicate logic system may show that an error is occurring internal to a logic system, but does not help determine the type of error that is occurring by capturing both input and failing output operands from the same internal function.

A forerunner of a data capture logic system according to the present invention is shown and described in US-A-4357703 which shows that certain test functions could be performed with LSI logic and that input and output operands could be captured in parallel fashion in registers for serial shifting into and out of the chip for test purposes. This system was good for LSI level logic design but VLSI demands other techniques because of the high logic density on a chip. Moreover, US-A-4357703 does not show a system for capturing data operands internally in the VLSI logic structure at different times during functioning of the VLSI logic.

According to one aspect of the present invention there is provided a data capture logic system to be associated with a VLSI logic array having a plurality of data registers characterised by comprising: a control register for holding various input data representing control functions for data capture mode logic; a plurality of data capture registers, each of which is connectable to one of the data registers in said logic array holding a selected operand from the logic array under test and responsive to a control function, wherein said data capture. registers are connected to receive control signals from said control register; a plurality of error detection means located in said logic array under test which will detect errors in operands occurring in the VLSI logic array under test; means responsive to said error detection means and connected to said data capture registers to store data in said data capture registers when an error is detected; and an output data capture register connected to said data capture registers and having a control portion and a data operand portion wherein said control portion holds control signals representative of an indication of the type of data failure which has occurred and wherein said data operand portion is arranged to control selected failed data operands received from said data capture registers.

The data capture logic system may include a soft memory connectable to one of the input registers for holding predetermined values of operands for determining the data capture functions to be performed, and a capture mode select and delay device connected to receive signals from said soft control memory and from said control register and connected to at least one of said data capture registers so that predetermined operands can be captured at preselected times. The data capture logic system preferably includes at least one multiplex data capture register which can select possible capture operands from a plurality of data registers, and select network means associated with the or each said multiplex data capture register for controlling which data operand is selected for capture, said select network means being connected to and responsive to said control register, said capture mode select and delay device and said error detection means for selecting which operand is to be captured by the associated multiplex data capture register.

Said control register may have means for storing a selection override enable signal and at least one multiplex data capture register being connected to receive more than one data operand and connected to said control register to receive said override enable signal so that said multiplex data capture register can be controlled to capture a different data operand from a different data register than would normally be captured.

Alternatively, said control register may have means for storing a selected override value signal, at least one multiplex data capture register being connected to receive more than one data operand and a select network connected to said control register to receive said selection override value signal so that said multiplex data capture register is responsive to said select network to capture a different data operand in response to said preselected value from a different data register than would normally be captured.

The data capture logic system, in the preferred embodiment, comprises means for producing an output hold source signal indicative of an error in input operand so that a device preceding the VLSI logic array can capture data.

The data capture logic system may include hold source control means for receiving an input hold source control signal indicative of an output operand error, said hold source control means connected to said output data capture register to cause said output data capture register to capture data operands.

Said data capture logic system may include a capture mode select and delay device connected to receive signals from said control register and connected to control at least one of said data capture registers, said control register having means for storing a capture delay select control signal for controlling said capture mode select and delay device to cause said at least one of said data capture registers to capture data operands at a preselected time different from the time at which other of said data capture registers capture data operands.

Preferably a soft control memory is connectable to one of the data registers for holding predetermined values of data operands for determining the data capture functions to be performed, said soft control memory being connected to con- trot said capture mode select and delay device.

According to another non-restrictive aspect of the present invention there is provided a data capture logic system to be associated with a VLSI logic array comprising: a plurality of logic error detection circuits connected to data registers in said logic array and in operation producing output logic error signals when an error occurs; a control register for holding various input data representing control functions for the data capture logic system; a soft control memory which holds predetermined values for determining the time of a data capture function to be performed in the event of a detected error and selected time of a data capture function when no error is detected; a capture mode select and delay device connected to receive signals from said soft control memory and from one of the data registers to determine a forced data capture when no error is detected; a plurality of data capture stages, each of which has one or more registers for holding selected operands from the logic array under test and selected control status flags, said registers, in operation, receiving control signals from said data registers, said soft control memory, said capture mode select and delay device, and said logic error detection circuits; multiplexer control means for selecting which operand of several predetermined operands is selected by at least one of said data capture stages; and an output data capture operand register having a control portion and a data portion wherein said control portion holds control signals representative of an indication of the type of data failure which has occurred and wherein said data operand portion contains selected failed data operands received from said plurality of failed data operand registers.

Said logic error detection circuit may be parity check circuits.

Said control register may have means for storing a selection override enable signal, at least one multiplex data capture register veing connected to receive more than one data operand and connected to said control register to receive said override enable signal so that said multiplex data capture register can be controlled to capture a different data operand from a different data register than would normally be captured.

Alternatively said control register may have means for storing a selection override value signal and further comprising at least one multiplex data capture register connected to receive more than one data operand and a select network connected to said control register to receive said override enable signal so that said multiplex data capture register is responsive to said select network to capture a different data operand in reponse to said preselected value from a different data register than would normally be captured.

The data capture logic system may include means for producing an output hold source signal indicative of an error in input operands so that a device preceding the VLSI logic array can capture data.

In one embodiment a data capture logic system may include hold source control means for receiving an input hold source control signal indicative of an output operand error, said hold source control means being connected to said output data capture operand register to cause said output data capture register to capture data operands.

The invention is illustrated, merely by way of example, by Figures 1A and 1 B which, when viewed in left to right order, are a schematic drawing of a logic circuit together with a data capture logic system according to the present invention.

Referring now to Figures 1A and 1B, a combined VLSI logic array and data capture logic system 10 according to the present invention is shown. The VLSI logic array does not form a part of the present invention but the data capture logic system according to the present invention can only be shown in connection with such a VLSI logic array. A sample gate logic array 11 is shown within dotted lines. The array 11 contains a pipe structure of sequenced operations.

An "A" operand is inputted in parallel through a channel 12 to a register 14. A "B" operand is inputted in parallel through a channel 16 to a register 18. A control operand is provided through a data channel 20 to a register 22. Associated with each register 14, 18, 22 is a parity check circuit 24, 26, 28, respectively. Each of the parity check circuits is connected respectively to a logic circuit 30 and to a register 32, the operation of which will be explained later.

The register 14 has an output connected to an input of an adder 34. The register 18 has an output which is connected as the other input to the adder 34. The output of the adder 34 is the sum of the "A" and the "B" operand which is connected to a register 36. The register 36 has an associated parity check circuit 38 which has an output connected to additional circuits, as will be explained later. The output of the register 36 is connected to an additional combinational logic circuit 40, which is part of the VLSI logic array. The combinational logic circuit 40 performs additional operations on operands it receives.

The register 22 is connected to a soft control memory 42, which stores the control operands it receives. The output of the soft control memory 42 is connected to a register 44, which also has an associated parity check circuit 46. The output of the register 44 is connected as an input to the combinational logic circuit 40. The output of the soft control memory 42 is also connected with a capture mode select and delay logic circuit 50 which is part of the data capture logic circuit of the present invention as will be described later.

The output result of the combinational logic circuit 40 is connected to a multiplexer register 52 which selects inputs from different sources. One input to the register 52 is indicated schematically as a constant on a data line 54. This constant might be all binary 1's or all binary 0's, or some other appropriate constant, for use with the circuit. The control for the register 52 is provided on a data channel 56 from the output of the register 44. The register 52 also has an associated parity check circuit 58. Finally, the output of the register 52 is provided as an output to the logic array 11 on a data channel 60, which represents the results of the operations performed on the input operands.

The capture mode select and delay logic circuit 50 is an optional system for controlling the time of data capture. The soft control memory 42 has an input line to the circuit 50, which can provide a capture signal to provide a capture of particular data at a predetermined time. In addition, an external capture signal can be provided on a data channel 70 to control a particular capture of data from outside of the system. The specific data capture trigger is selected by a channel 80 and the additional delay factor is selected by a channel 82.

An input register system with its controls is shown generally within a dotted line box 72. This input register system consists of a register having various sections into which data is serially shifted and from which data may be removed in parallel to drive various portions of the data capture logic system according to the present invention. The first two sections of a control register 74 are a section 76 containing the capture mode select logic and a section 78 containing the capture delay select logic. The section 76 provides a capture mode select signal on the channel 80 to the capture mode select and delay circuit 50 and the section 78 provides a signal on the channel 82 to the capture mode select and delay logic 50. The output of the capture mode select and delay logic circuit 50 is connected to a register 84 and provides a control signal to capture data. The output of the register 84 is passed on to a register 86.

The logic circuit 30 is an OR gate which receives inputs from the parity check circuits 24, 26, 28. If any one of the input registers 14, 18, 22 shows an input parity error then the OR gate 30 is activated to produce a "hold source" data signal on a data path 88 to a register 90. The data path 88 also has an external output pin external to the logic array 11, which indicates that input data to the chip is in error and that, therefore, the logic array itself may not be the cause of the error. This signal on the output pin is sent to the VLSI logic chip(s) which is (are) sending the input data. This signal causes the data being sent to be captured and to keep it available for error analysis.

The register 90 has an output which is connected to a register section 92 and to an OR gate 94. The register section 92 has an output which goes to a section of an output shift register 100, which will be described later. The OR gate 94 also receives inputs from the outputs of the parity check circuits 38, 46 either one of which can activate the output of the OR gate. Registers 110, 112, 114 receive inputs from the input registers 14, 18, 22, respectively, and capture the content of these input registers.

The function of error status registers 31, 32, 33 is to allow the capture of the data represented at the time of the first error rather than subsequent errors. Subsequent error information might be totally irrelevant or confusing in terms of analysis. Thus, the control mechanism functions as the first parity check error or the first error of other types in order to capture the input operands and the failing data occurring the first time an error is triggered.

The register 110 has an output connected to a register 130 for passing the "A" operand forward in the pipe. Similarly, the register 112 is connected to a multiplex register 132 for passing the "B" operand to the multiplex register 132 when it is selected. The register 132 has an additional input of data from a data path 56, which comes from the register 44 and can represent the capture of data at a different point in the operational process. The register 132 has a select network 138 which produces selection control signals to determine which operand is selected to be stored in a particular data capture situation. Similarly the register 114 is connected to a multiplex register 134 for passing the control operand forward. The multiplex register 134 has a second data input which is connected to a data path 39, which connects the register 36 to the combinational logic circuit 40. A select network 136 controls the operation of the multiplex register 134 and has various inputs that select the conditions by which the operand held in the multiplex register 134 is selected.

The combinational logic circuit 40 may be used to perform any desired type of function and is shown to indicate that there will be additional logic steps on the VLSI logic chip of the logic array. For example, the combinational logic circuit 40 might be a masking network, exclusive ORs, AND gates, etc. that performs some desired logic function. The combinational logic circuit 40 does not contain registers, however, because registers would be connected to the data capture logic system of the present invention.

The intention is that the illustrated data capture logic system according to the present invention is that it can be used with a more complex VLSI logic system than is known. The system could have more data capture registers of the type shown, for example, by registers 110, 112, 114, and additional data capture multiplex registers similar to the registers 132, 134, where a choice of inputs can be selected depending on the type of data capture that is desired in the system. Similarly, the select networks 136, 138 can operate to select different operands in the system depending on various selected input control signals. These are shown by way of example only to indicate the types of data capture modes that are available, but not to limit the system with respect to other possible modes of data capture.

For example, the select network 136 receives a control error signal from the parity check circuit 46 if there is an error in the operand in teh register 44. This can then be used to select, for example, the operand coming out of the register 44 for data capture purposes. Similarly, the select network 136 has a control code error input from the register 32, which represents an error in the parity check circuit 28 associated with the input register 22. This can have a different function for retaining captured data from a previously detected error at a different level of input to the system.

Finally, the input register system 72 has a section 77 which provides a selection override enable signal, and a section 79 which provides selection override values. The sections 77, 79 have outputs which are connected with the selection networks 136, 138, respectively. If the override control is activated to the select network 136, then other values can be selected to be captured based on these external control signals regardless of the output conditions of the parity check circuits 46, 28, for example. Similarly, the select network 138 has as inputs an override enable signal and an override value signal which forces the selection and capture of a predetermined field of data. This allows for the capture of operands at a different time sequence than other operands, or for the capture of operands other than the preselected default operands in the same time period.

A control device 95 is connected to receive the output of the OR gate 94. The OR gate 94 receives information from the parity check circuits 38, 46, as well as hold source data signal from the register 90, when activated. Thus, if the OR gate 94 is activated, a signal is placed into the control device 95 associated with the registers 130, 132, 134. This control device gives status information on the data captured in these registers and will be used to make data selections at the next period in time. An OR gate 96 is in turn connected to receive signals from the control device 95 and the parity check circuit 58.

Control blocks 150, 152, 154, 156, 158 are also associated with the control of the registers 130, 132, 134. The control blocks 150, 152, 154 receive the indicated signals from the registers 31, 32, 33 associated with the registers 110, 112, 114. Thus, the passing on of the control signals from one set of control blocks to another can provide for either simultaneous data capture at the different positions or sequenced data capture. In addition, the control block 156 is associated with a sum error signal which is initially generated by the parity check circuit 38. The control block 158 is associated with a control error signal which is initiated by the parity check circuit 46.

The input register system 72 is a shift register which has a shift data input channel 73. The input register system 72 also has a control channel 75 which controls the shifting function of a shift register by operating a gate data shift control 81. The register 100 is a serial shift output register in which data is captured in parallel form but shifter out upon command in serial fashion. The register 100 contains control status flags 200, 202, 204, 206, 207, 208, 209, 210, 212, 214. Data is captured in data capture registers 216, 218, 220. The data capture registers 218, 220 receive their input data directly from the registers 132, 134, respectively. The data capture register 216 is a multiplex register which can select the data it captures from either the multiplex register 52 or from the register 130. A select network control 222 is provided to control the operation of the data capture register 216. The select network 222 receives control input signals from the sections 77, 79 of the input register system 72, which is a selection override control from an external command to the system. The other input to the select network 222 is a previous error signal received from the control device 95 as a result of the operation of the OR gate 94. The OR gate 96 operates from the control device 95 to set the error flag 206 showing an internal error.

Output signals from the data capture logic system include a hold source signal out, representative of a parity error in one of the input registers 14, 18 or 22, representing the fact that input data was in error. A channel 242 is the channel from which the register contents are shifted out. A channel 244 is a hold source channel into the data capture logic system, indicating that the succeeding VLSI chip device received an error signal and that this VLSI chip device should capture its output data for error analysis. An OR gate 246 receives signals from the various control blocks, as shown, and produces a data captured signal on an output line 248. When a data captured signal appears on the line 248, a register 250 is set, holding up the error captured signal on the line 248 and thus locking in the data in the register 100. This register is cleared by the process of shifting the data out so that when the data is removed, the data capture logic is ready to begin checking again.

The data capture logic system according to the present invention and described above operates in the following fashion. The essential concept of the data capture logic system is that data will be selected into the register 100 and captured at a specific time determined by the control logic. The exact use is controlled by the status of the input register system 72. The different modes of operation are as follows: <ul id="ul0001" list-style="none"><li>1. Capture of failed operand and its input operands. The normal use of this logic is to capture either solid or intermittent failures that cause parity errors. The parity error signal will cause the operands, which immediately preceded the failed logic, and which were error free, to be captured into the register 100 along with the failing data. The maintenance hardware can then shift the data out of the register and analyse the error.</li><li>2. Modified capture of failing data. If the default operands for an error are not sufficient to diagnose the failure, the input register system 72 can be loaded with multiplexer selection values that would capture data other than the default data specified by the hardware. These multiplexer selection values would operate the registers 132, 134, as well as the register 216, for example.</li><li>3. Internal array data inspection. Some failures or design errors will not cause parity errors. In these cases, the data capture logic system can be used to capture operands, specified by the input register system 72, at a specific time. The timing of the capture control can be through a bit set in the soft control memory 42 or from an external timing signal. These signals can be further delayed by the section 78 in the input register system which is connected with the capture mode select and delay logic circuit 50. The use of this function on a looping test can provide data for use in logic analysis.</li><li>4. Array testing. The complexity of testing large arrays can be reduced by making internal nodes visible outside of the array. The data capture logic can be used in a test mode to shift internal data out of the array during array testing.</li></ul>

The output of the data capture logic system not only provides the appropriate operand values when a failure mode occurs, but it also provides information as to where and what type of failure was detected. For example, if a parity failure has occurred, the output will indicate at which level of logic the parity error occurred.

The data capture logic system has a number of benefits which include the ability to capture intermittent failing data when the failure occurs and still allow correct data to pass through the system. At the time of data failure, both the failed data and inputs to the failing logic can be captured. One of the significant features of the data capture logic system is the flexibility in capturing data from error signals, from internal control signals, or from an external control signal line. These non-error capture signals can also be delayed based on a value in the input register system 72. The system also has the flexibility to provide an override operand selection to replace the default operands at the time of failure.

Finally, because all data for either logic purposes or control purposes is shifted into the data logic capture system in a serial shift fashion, comparatively few additional pins are needed on a logic chip to implement this system.

The design of a data capture logic system is tailored to the particular logic of a particular VLSI chip. The illustrated embodiment is only a very general case, but shows the method that would be implemented for any logic system. First, an analysis is made of the logic array with which the system is to be associated. This analysis shows where the detectabls faults in the logic would occur. A chart is then formed which indicates the data operands to be reported with each particular type of fault and the priority with which multiple faults are to be evaluated. It is particularly useful that the present system can deal with a logic array in which more than one fault can occur, but the system reports the priority fault selected by design. However, the system can be used to report other faults than those selected by the default priority. A particularly useful function of the data capture logic system is the "hold source" function. When the data capture logic detects an error on the first rank of operand registers of the array, no valid data is available by which the logic array can isolate the failure. In these cases, the "hold source" signal is sent to the sending array and the outputs of that array are captured. This allows for the detection of an error which may be represented by the interconnection of one or more logic arrays and the interconnection system.

Another significant feature of the data capture logic system is that it does not save all data in a logic array. If all data in a logic array is saved, unnecessary data or correct data may be saved, but it would all have to be analysed. The data capture logic system performs an automatic data reduction function by reducing the captured data to only that data representing a failure mode or that representing preselected data. This saves considerably in the error analysis if unneeded data is not present. Thus, data reduction can take place at all error operand delay ranks. If an error is not detected- at a certain point, the original operand is discarded, unless for some reason according to the logic system, it is needed elsewhere. The system used as an example shows data reduction but does not show the benefit of this data reduction function as much as would occur in a very large and complex array. For purposes of this specification, however, the showing of an array with numerous additional registers and other functions would merely be redundant. Yet it can be seen even from the present example that only certain registers have data passed externally to the system. As logic within the VLSI logic array increases, more data is discarded at each rank and the improvement over a system which shifts all data out of the array becomes more obvious. This particular system is designed to capture the earliest error in a pipeline data path. When there is more than one error possible at a single time clock or data cycle, the selection network can be designed to give a priority to certain errors.

Another feature of the present invention is referred to as the "capture mode select" function. The function is controlled by the 2 bit signal sent from the section 76 of the input register system 72 to the capture mode select and delay logic circuit 50 with respect to use of the external capture signal on the channel 70 and the signal from the soft control memory 42. The capture mode select function can be defined as follows: <tables id="tabl0001" num="0001"><img file="EP0198568A2_D0001.tif" /></tables>

With respect to Figures 1A and 1B, the following information explains notes in the drawing.

The symbol "PC" stands for parity check circuit.

Triangle symbol 2 on the status flag 200 stands for "redundant array checksum error".

Triangle symbol 3 on the status flag 202 stands for "forced data capture".

Triangle symbol 4 on the status flag 204 stands for "uncertain source of error".

Triangle symbol 5 on the status flag 206 stands for "internal error detected".

Triangle symbols 6 to 11 are error flags standing, respectively, for: <ul id="ul0002" list-style="none"><li>6 operand "A" error</li><li>7 operand "B" error</li><li>8 control code error</li><li>9 sum error</li><li>10 control error/ reloadable soft control error</li><li>11 output error.</li></ul>

Triangle symbolb 12, 13 and 14 represent registers for captured data. The following table shows the default data capture value associated with the registers: <tables id="tabl0002" num="0002"><img file="EP0198568A2_D0002.tif" /></tables>