Data processor system and method.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates generally to a data processing system and more specifically to a data processing system suitable for processing image information composed of a large amount of digital data indicative of an image including pictures and characters such as in document or drawing.

Description of the Prior Art

The field in which data processing systems for image information of the above-mentioned kind is applicable is now expanding. Therefore, if document preparation, electronic files, mutual communications, etc. can be configured as a series of systems simply at a low price, it is possible to provide a data processing system useful for general business processing transaction in various fields such as office automation, future of the office, paperless office, etc.

The image information of this kind, however, includes a great amount of information about 100 times or more greater than that of the case where the general data coded into a predetermined code are processed (for instance, numerical value calculation, data processing, word processing, etc.). Therefore, in digitally processing image information, it is necessary to adopt hardware having a throughput 100 times or more qreater than that of the case where general data are processed. For the reason as described above, conventionally, there have been adopted various methods such that a special processor, a special hardware logic, or a large-scale electronic computer all desiqned in accordance with special specifications so as to be able to process a great amount of data have been so far adopted, while reducing the load applied to hardware by compressing data in order to reduce the amount of data to be processed.

In the case where the conventional method is adopted, however, there exist problems in that it is unavoidable that the overall system configuration of the data processing system is large in size and complicated, and additionally a costly system should be used.

To solve these problems, it may be considered that image information can be processed by use of personal computers, mini-computers, office computers, etc. which are all available as versatile units. However, since these versatile units are not configured so as to process a great amount of data; since the processing speed is slow; and since these units have no processing capability to execute various tasks independently, it is impossible to process a great amount of data in a short time even if the functions of these units are utilized simply as they are.

SUMMARY OF THE INVENTION

With these problems in mind, therefore, it is the primary object of the present invention to provide a data processing system for processing image information at a practically and sufficiently high data execution and processing speed by arranging a number of devices such as versatile microprocessors, memory units, etc. of low processing speed and low processing capability which are all connected to each other through a system bus and by providing arbitration functions such that each device can process data in simultaneous parallel fashion.

To achieve the above-mentioned object, the data processing system according to the present invention, which includes data input means for inputting data, display means for displaying inputted data and processed data, storage means for storing the input data and the processed data, and shared storage means connected to each of the above means through a system bus, said system executing data processing designated by the data input means, comprises, in particular, (a) a plurality of processor means provided for the data input means, the display means and the data storage means, respectively, for executing data processing, separately; (b) a plurality of memory bank means connected to the system bus, respectively, and constituting the shared storage means; (c) means for generating an enable signal to acknowledge an occupation of one of said designated memory bank means, respectively, in response to each memory request from any of said processor means indicative that data should be transferred through the system bus to a designated one of said memory bank means; and (d) means for dividing data transferred between said processor means and memory bank means into a predetermined divisional data and for executing data processings with respect to a plurality of simultaneously outputted memory requests in synchronization with a bus clock in the system bus and in simultaneous parallel fashion for each divisional data when a plurality of memory requests are outputted simultaneously from a plurality of said processor means.

In the data processing system according to the present invention, said executing means further comprises means for allocating each time slot so formed so as to synchronize with the bus clock in the system bus to a plurality of said memory bank means, respectively and for transferring a unit of processed data constituting the divisional data through the system bus at the timing of the time slot allocated to the memory bank means designated by the memory request.

Further, said executing means comprises second means for transferring a unit of processed data for said memory bank means other than that designated by the memory request through the system bus at the timing of the allocated time slot corresponding to one memory bank means not designated by the memory request.

Further, said executing means comprises third means for forming a time slot allocated to no memory bank means in addition to the time slots allocated to a plurality of said memory bank means and for transferring a unit of processed data for the memory bank means designated by the memory request through the system bus at timing of the non-allocated time slot.

Furthermore, said executing means comprises fourth means for transferring data corresponding to the memory request to the memory bank at the timing of the time slot next to an empty time slot, when an empty time slot not designated by the memory request is produced in a series of time slots.

In the data processing system, the time slot is selected to have a time duration shorter than a memory cycle required when the memory bank means writes or reads data or the time duration is selected to be shorter than the data processing time required when said processor processes the data read through the system bus.

The data processing system according to the present invention further comprises arbitrating means for selecting one of simultaneously outputted memory requests in accordance with a priority order previously determined with respect to each processor means and for processing data corresponding to the memory request selected on the basis of priority, when a plurality of memory requests are outputted simultaneously from two or more processor means to the same memory bank. Said arbitrating means comprises a lock function such that a selection of other memory requests are refused until data corresponding to one of the priority-selected memory requests have been processed by a predetermined amount.

In summary, the data processing system divides data to be processed respectively in response to a memory request outputted from each processor into a predetermined amount of divisional data and executes the data processing corresponding to each memory request being classified according to the divisional data in synchronization with the clock of the system bus in simultaneous parallel fashion.

Therefore, when memory requests for each processor are generated in sequence, all the data corresponding to each memory request can be processed for each divisional data without processing all the data simultaneously; that is, the divisional data are processed in sequence simultaneously in parallel fashion, so that it is possible to markedly reduce processing time on the whole, because almost all parts of the data processing corresponding to all the memory requests can be processed within a short time during which the divisional data corresponding to a plurality of simultaneously outputted memory requests are executed simultaneously.

Therefore, even if versatile devices of small throughput are used as the processors and memory banks, it is possible to execute the processing of all the data at a practically and sufficiently high data execution processing speed. In other words, in processing the data including non-coded data such as image data, it is possible to readily configure a data processing system having the same degree of throughput as in a specially ordered computer by simply adopting several versatile devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the data processing system according to the present invention will be more clearly appreciated from the following description of the preferred embodiments of the invention taken in conjunction with the accompanying drawings in which like reference numerals designate the same or similar elements or sections throughout the figure thereof and in which: <ul id="ul0001" list-style="none"><li>Fig. 1 is a schematic block diagram showing the general system configuration of the data processing system according to the present invention;</li><li>Fig. 2 is a diagram showing a series of data processing steps to be processed by the system shown in Fig. 1;</li><li>Fig. 3 is a similar diagram showing a plurality of a series of data processing steps to be processed in simultaneous parallel processing fashion;</li><li>Fig. 4 is a schematic block diagram showing a configuration section related to the bus system shown in Fig. 1;</li><li>Fig. 5 is a schematic block diagram showing a detailed configuration of the time slot allocator 16A shown in Fig. 4;</li><li>Fig. 6 is a signal waveform diagram showing a plurality of time-series time slot signals;</li><li>Fig. 7 is a schematic block diagram showing a detailed configuration of the memory access controller shown in Fig. 4;</li><li>Fig. 8 is a schematic block diagram showing a further detailed configuration of the memory access means shown in Fig. 7;</li><li>_Fig. 9 is a schematic block diagram showing a detailed configuration of the priority selector means shown in Fig. 8;</li><li>Fig. 10 is a table for assistance in explaining the priority order of each processor;</li><li>Fig. 11 is a schematic block diagram showing a detailed configuration of the memory bank enable signal generator shown in Fig. 4;</li><li>Fig. 12 is a schematic block diagram showing a detailed configuration of the memory banks shown in Fig. 4;</li><li>Figs. 13 to 16 are signal waveform diagrams showing signals of each section; and</li><li>Fig. 17 is a diagram showing the data processing procedure implemented in the data processing system in simultaneous parallel processing fashion.</li></ul>

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be describe in further detail with reference to the attached drawings.

As shown in Fig. 1 the data processing system comprises a system bus 1 connected to eight subsystems 10, 11, 9, 12, 6, 8, 7, 5, for sharing the task of a series of data processing steps to be executed in sequence. The system bus 1 is also connected to a shared storage device 2 shared by each subsystem.

The shared storage device 2 includes a board 2A on which a bus and a memory controller (MBC) are mounted and two boards 2B and 2C on each of which a RAM having a memory capacity of 2 mega bytes (referred to as MB hereinafter) is mounted. The bus and the memory controller read and write corresponding data in or from the RAMs on the boards 2B and 2C through a local bus 2_D in response to memory requests outputted from each subsystem through the system bus 1. In the case that the memory requests from each subsystem are concurrent, the bus and the memory controller (MBC) arbitrate this concurrent relationship so that the data can be processed simultaneously in parallel fashion. That is, the bus and the memory controller (MBC) include a function which is responsive to all the requests of the subsystems in a short time.

The system bus 1 is connected to each subsystem's CPU, P₀ to P₇, and is shared by all the processors P₀ to P₇ for transferring signals and data between each processor (CPU) P₀ to P₇ and the bus 1 and the memory controller (MBC) in the shared storage device 2.

In a first subsystem, a file storage device (STS) 5 is allocated and a processor P₀ having a data processing speed of 2 MB/sec is connected to the system bus 1. Being mounted on a board 5A, the processor P₀ can store or read file data in or from a DRAW (direct read after write device) 5B and a HDD (hard disk device) 5C which configure a storage device for filing data in the data processor. In this embodiment, an interface (DRAW I/F) for the DRAW 5B is disposed on the board 5A. Further, a board 5D on which an interface (HDD I/F) for the HDD 5C is mounted is connected to the processor P_o through a local bus 5E.

Therefore, the processor P_o writes data stored in the shared storage device 2 into the HDD 5C or the DRAW 5B through the system bus 1 and transfers data stored in the HDD 5 or the DRAW 5B to the shared storage device 2 through the system bus 1.

Further, in a second subsystem, a data transfer system (NTS) 6 is allocated and a processor P, having a data processing speed of 2 MB/sec is connected to the system bus 1. The processor P₁ is mounted on a board 6A together with a transmission controller (Ethernet controller) and can send out data from the system bus to a transmission path 6C of a coaxial cable through a transmission unit 6B and can receive data coming through a transmission path 6C to the system bus 1.

Therefore, the processor P₁ sends out data stored in the shared storage device 2 to the transmission unit 6B through the system bus 1 and receives data coming from the outside via the transmission unit 6B in the shared storage device 2 through the system bus 1. As a result, it is possible to configure a further larger scale data processor system by connecting this data processor to outside devices or units.

In a third subsystem, an image reader and printer (IDS) 7 is allocated and a processor P₂ having a data processing speed of 2 MB/sec is connected to the system bus 1. The processor P₂ is mounted on a board 7A together with an image input/output controller. Under the control of this image input/output controller, the processor P₂ is connected to an image printer (IP) 7E through a local bus 7B and an image printer interface (IP I/F) board 7C and further connected to an image reader (IR) 7F through the local bus 7B and an image printer interface (IR I/F) board 7D. The processor P₂ sends image data read through the image reader 7F in the shared storage device 2 through the system bus 1 and prints out data in the shared storage device 2 in an image printer 7E through the system bus 1.

In a fourth subsystem, an image information compressor/decompressor system (CDS) 8 is allocated, and a processor P₃ having a data processing speed of 2 MB/sec is connected to the system bus 1. The processor P₃ is mounted on a board 8A together with a compress/decompress controller, and reads data in the shared storage device 2 through the system bus 1, transfers this data to a compress processing circuit (COMP) board 8C or to a decompress processing circuit (_DECOMP) board 8D through a local bus 8B, and further sends this compressed or decompressed, processed data to the shared storage device 2 through the system bus 1. The image information compressing/decompressing system 8 increases the amount of data to be stored by previously compress-processing data to be stored in the H_DD 5C or DRAW 5B of the file storage device 5 in accordance with a modified Huffman method or a modified READ method and by decompress-processing the compressed data read from the HDD 5C or the DRAW 5B, the compressed or decompressed data being processed for transmission, display, printing, etc.

In a fifth subsystem, an operation display system (DPS) 9 is allocated and a processor P₄ having a data processing speed of 2.5 MB/sec is connected to the system bus 1. On the board 9A, on which a processor P₄ is mounted, there are mounted ROMs and RAMs for storing processing programs and data used in converting image data read by the processor P₄ into image display signals.

Further, an operation display system 9 has operating input means such as a keyboard 9B and a mouse 9C. Data from the keyboard 9B and the mouse 9C are inputted to or outputted from the processor P₄ through a serial input/output circuit (S I/O) mounted on the board 9A.

Here, data inputted through the keyboard 9B and the mouse 9C are those coded into predetermined formats, and the processor P₄ transfers these input data (e.g. character data or command data composed of characters, symbols, etc.) to the shared storage device 2 through the system bus 1.

In contrast with this, in the case where image data (such as images, characters or data indicative of a combination of images and characters) are displayed, the processor P₄ gives these data to a bit map controller BMC on a board 9E as commands and data through a local bus 9D. Here, the processor P₄ transfers only the coded character data to the bit map controller (BMC) as commands to convert them into font data corresponding thereto, and then transfers them to two boards 9G and 9H of video memory (VRAM) through a local bus 9F in order to develop them on a two-dimentional picture memory.

On the other hand, since image data generated by an image reader 7F are uncoded data directly representing black and white picture elements as they actually are, the processor P₄ develop these data without converting them in the method as executed for coded character data.

Image data thus developed on the VRAM are read through a local bus 9F by a timing circuit (TIM) mounted on a board 91 and then displayed on displays 9J or 9K such as a cathode ray tube (CRT), for instance.

In addition to the above-mentioned functions, the processor P4 reads image data from the shared storage device 2 through the system bus 1 and assembles or edits these into a piece of picture. Further, the processor P₄ has a function for inserting characters inputted from the keyboard 9B onto the picture. The processor P₄ displays data being processed in the above assembly edition process on the CRTs 9J and 9K and transfers the assembled edited data to the shared storage device 2 through the system bus 1.

As described above, the operation display unit 9 assembles and edits a piece of picture on the basis of image data read from the file storage device 5 to the shared storage unit 2 and in response to the operations of the keyboard 9B and the mouse 9C serving as operation input means and displays the picture on the display units 9J and 9K, further the edited picture data are transferred to the shared storage unit 2 through the system bus 1. These data are stored in the file storage device 5, printed by an image printer 7E provided in an image read printer 7 or transferred to the outside through a data transmitter 6B.

In a sixth subsystem, a main controller system (PCS) 10 is allocated and a processor P₅ having a data processing speed of 2.5 MB/sec is connected to the system bus 1. To a board 10A on which the processor P₅ is mounted, a RAM on a board 10C and an input unit I/O on a board 10D are connected through a local bus 10B. Each subsystem and the shared storage device 2 connected to the system bus 1 are controlled as a whole in accordance with a system operation program (operating system, application program, etc.) written from a floppy disk drive (FDD) in the local memory RAM through the input/output device I/O. Interrupt signals and attention signals required for the above-mentioned control are transferred between the main controller 10 and the total subsystems through a control signal line 3.

Further, the processor P₅ executes the assembly processing of image data to be printed by the image printer 7E in accordance with a program inputted to the RAM on the board 10C.

Seventh and eighth subsystems, preliminary units 11 and 12 (their processors are designated by P₆ and P₇)_' have bus space allocated for them so as to allow other new possible functions to be added.

In the system configuration as shown in Fig. 1, the operator can enter commands for designating modes and character data such as characters and symbols by the use of the keyboard 9B and the mouse 9C in the operation display system 9 and further image data including pictures and characters by the use of the image reader 7F of the image read printer 7. Here, data inputted from the keyboard 9B and the mouse 9C are those having predetermined codes so as to be easily transferred and processed, so that the character data can be inputted in dependence upon a relatively small amount of data. In contrast with this, image data inputted from the image reader 7 of the image read printer 9 are extraordinally great in the amount of data, because the image data represents the black or white of each picture element on the basis of binary code.

The data inputted through the keyboard 9B or the mouse 9C are written once from the processor P₄ of the operation display system 9 to the shared storage device 2 through the system bus 1 and thereafter transferred to the image compressor/decompressor system 8 again through the system bus 1 in order to execute data compression processing. The data thus processed are transferred to the shared storage device 2 again through the system bus 1. Thereafter, the data are transferred to the file storage device 5 again through the system bus 1 and are stored in the HDD 5C or the DRAW 5B serving as the external storage device.

Similarly, image data inputted from the image read printer 7 are once stored in the shared storage device 2 through the system bus 1, and then transferred to the image information compressor/decompressor system 8, again through the system bus 1, for data compression. The compressed data are transferred to the shared storage device 2 through the system bus 1 and then transferred to the file storage device 5 through the system bus 1 so as to be stored in the HDD 5C or the DRAW 5B.

As described above, data compressed by the image information compressor/decompressor system 8 are stored in the HDD 5C and the DRAW 5B, and these stored data are outputted to the display units 9J and 9K in the operation display unit 9 or the image printer 7E in the image read printer 7. In this case, data in the HDD 5C and the DRAW 5B are transferred to the shared storage device 2 through the system bus 1 on the basis of the data from the keyboard 9B or the mouse 9C in the operation display system 9, and then transferred to the image information compressor/decompressor system 8 through the system bus 1 in order to decompress the transferred data. The resultant data are transferred to the shared storage device 2 through the system bus 1 and then displayed or printed by the display units 9J and 9K in the operation display system 9 or by the image printer 7E in the image read/printer 7. At this moment, the assembly of the picture with respect to image signals supplied to the display units 9J and 9K is executed by the processor P₄ in the operation display system 9, while the assembly of a picture with respect to image signals supplied to the printer 7E is executed by the processor P5 in the main controller 10.

Further, in such a mode that data stored in the file storage device 5 are re-edited or that characters are newly inserted in a picture inputted through the keyboard 9B or the image reader 7F, after having once been transferred to the shared storage device 2 respective data are edited by the processor P₄ in the same way.

As described above, the data processor shown in Fig. 1 processes data under the control of the main controller 10 in each operation mode in accordance with an operation program (that s operating system or application program) inputted from the floppy disk drive FDD to the local memory RAM on the board 10C in the main controller 10. In executing the above data processing, each subsystem makes an access to the shared storage device 2 while sharing the system bus 1. At this moment, it is necessary to occupy the shared storage device 2 and the subsystems until data processing on the basis of a memory request has been completed in response to a corresponding memory request outputted from one subsystem. However, if the above occupation time is excessively long, it would be necessary in a prior art system to wait for a long time in order to process data on the basis of another memory request outputted from another subsystem. In order to solve the above problem, the shared storage device 2 is so configured as to have an arbitration function such that the bus and the memory controller (MBC) can process the supply of data from each processor in each subsystem simultaneously in parallel fashion. Therefore, it is possible to markedly reduce data processing time as compared when a series of sequential data are processed in time-series fashion, as described below.

Further, signals and data having a bar code are represented on the basis of negative logic.

Now, for example, in the case where image data (having been compressed) stored in the HDD 5C and the DRAW 5 in the file storage device serving as an external storage device are retrieved and displayed on the display units 9J and 9K in the operation display device 9, a series of data as shown in Fig. 2 are processed in sequence.

That is, at the data processing step PRO of No. 0, under the control of the main controller 10, image data to be read out from the HDD 5C or the DRAW 5B in the file storage device 5 are retrieved logically.

At the succeeding data processing step PR1 of No. 1, the data retrieved from the file storage device 5 are read out and transferred to the shared storage device 2. At the succeeding data processing step PR2 of No. 2, the data transferred to the shared storage device 2 are read out by the processor P₃ in the image information compressor/decompressor system 8 for decompression processing and then written again in the shared storage device 2. At the succeeding data processing step PR3 of No. 3, the data written again into the shared storage device 2 are read out by the processor P₄ in the operation display system 9 for the edition/assembly processing of a picture and for the insertion processing of characters and then stored again in the shared storage device 2. At the succeeding data processing step PR₄ of No. 4, the data stored again in the shared storage device 2 are read by the operation display system 9 and then displayed on the display units 9J and 9K through the bit map controller 9E and the VRAMs 9G and 9H.

In a series of these data processing steps, the steps in which the data are transferred through the system bus 1 are the data processing steps PR₁ to PR₄ of No. 1 to No. 4, the sum total of each processing time T₁ to T₄ being determined according to the data processing speed of each processor for processing data in each step and to the amount of data to be processed in each processor.

That is to say, in the data processing step PR1, the data read out from the HDD 5C or the DRAW 5B in the file storage-device 5 are transferred to the shared storage device 2 during time T₁ at the data processing speed 2 MB/sec of the processor P_O. In the data processing step PR₂ of No. 2, the processor P₃ in the image information compressor/decompressor system 8 reads the data stored in the shared storage device 2 at the data processing speed 2 MB/sec, and further the processor P₃ stores again the decompression processed data into the shared storage device 2 at the data processing speed of 2 MB/sec, thus a data processing time T₂ being required. Also, in the data processing step PR₃ of No. 3, the processor P₄ in the operation display system 9 reads out the data from the shared storage device 2 at the data processing speed of 2.5 MB/sec, and then executes the edition processing such as picture assembly or character insertion, etc. Thereafter, the processor P₄ stores the edited data in the shared stored device 2 at the data processing speed 2.5 MB/sec thus a data processing time T₃ being required. Further, at the data processing step PR₄ of No. 4. the processor P₄ in the operation display unit 9 reads out the data from the shared storage device 2 at the data processing speed of 2.5 MB/sec and displays the read data on the display units 9J and 9K, thus a data processing time T₄ being required.

Therefore, in the data processing system configured as shown in Fig. 1, if a series of data processing steps as shown in Fig. 2 are executed in sequence in time-series fashion, the sum total TSM 1 of times required for processing and storing data over the system bus, is as follows:<maths id="math0001"><img file="EP0187518A2_D0001.tif" /></maths>

According to the theory of the present invention, however, the task of processing and storing the amount of data thus explained over the system bus is divided into a predetermined divisional data (for instance, about 16 kB or 8 kB (kB: kilobyte)) and the data processing is executed one divisional data by one divisional data simultaneously in parallel fashion by the use of a plurality of processors.

In more detail, the data to be processed in a series of data processing steps PR, to PR₄, res^pec- tively, as shown in Fig. 2 are divided into a plurality of divisions (seven divisions in this embodiment) as shown in Fig. 3, and the processings of each divisional data are executed in sequence simultaneously in parallel fashion for each divisional data processing execution time TU₁ to TU₁₀

In Fig. 3(A), the data corresponding to one sector or one track are read from the file storage device 5 by the processor P_o as a first divisional data to be processed, corresponding to the data processing step PR₁ in Fig. 2, and are transferred to the shared storage device 2, all during the processing step PR₁₁ of processing execution time TU,. This first divisional data as shown in Fig. 3(B) is next processed in the processing step PR₂₁ during the succeeding processing execution time TU₂, corresponding to the data processing step PR₂ shown in Fig. 2. That is, the data are read from the shared storage device 2 by the processor P₃ in the image information compressor/decompressor system 8 for decompression processing, and are then stored again in the shared storage device 2.

This first re-stored divisional data, as shown in Fig. 3(C), is next processed in the processing step PR₃₁ during the processing execution time TU₃, corresponding to the data processing step PR₃ shown in Fig. 2. That is, the processor P₄ reads the divisional data in the shared storage device 2 for edition processing and thereafter the data is re-stored in the shared storage device 2. This first re-stored divisional data, as shown in Fig. 3(D), is thereafter processed in the data processing step PR₄₁ during the processing execution time TU₄, corresponding to the data processing step PR₄ shown in Fig. 2. The first divisional data in the shared storage device 2 are thus read out by the processor P₄ and displayed on the display units 9J and 9K.

As described above, the first divisional data is processed sequentially in the order of the data processing steps PR₁₁, PR₂₁, PR31, and PR41 during the processing execution times TU₁, TU₂, TU₃, and TU₄, respectively.

After the elapse of time TU₁, in the second processing execution time TU₂ the processor P₀ in the file storage device 5 reads the second divisional data from the external storage device in the data processing step PR₁₂ and stores it in the shared storage device 2. In the same way as in the first divisional data, this second divisional data is sequentially processed in the data processing steps PR₂₂, PR₃₂, and PR₄₂ which are time shifted in sequence with respect to the processing execution times TU₃, TU₄ and TU₅; as a result, the second divisional data are displayed on the display units 9J and 9K during the processing execution time TU₅.

In the same way, the third, fourth, ..., etc. divisional data are read from the file storage device 5 in sequence during the processing execution times TU₃, TU₄ ..., etc. and are processed and displayed on the display units 9J and 9K in sequence in the processing steps (PR23, ^PR_33'^PR₄₃)_' (^PR_24' PR_34' PR₄₄), ..., etc. as these third, fourth ..., etc. divisional data are shifted in sequence to the succeeding processing execution times (TU4, TU₅, TU₆), (TU₅, TU₆, TU₇) ..., etc.

As described above, the data to be processed in the data processing steps PR₁, PR₂, PR₃ and PR₄ shown in Fig. 2 are processed in sequence one divisional data by one divisional data for each succeeding divisional data processing execution time, and further the sequential processings are executed in concurrent parallel fashion (referred to as pipe line processing). As a result, each processor to which each task in each processing step is allocated operates in concurrent parallel fashion in the divisional data processing execution time. Therefore, it is possible to enhance the processing capability as a whole when a plurality of processors is seen as a single processor, thus the total data processing time being shortened.

The reason why the above-mentioned good results can be obtained is that: in the case where the data processing steps PR₁ to PR₄ are executed in sequence in time-series fashion as shown above in Fig. 2, while one processor to which a task for one data processing step is allocated is operating for data processing, other processors are in a stand-by condition only awaiting commands without processing data, and therefore the data processing time is elongated because of the existence of such wasteful time. However, according to the method shown in Fig. 3, it is possible to markedly reduce the above-mentioned wasteful time.

When the data processing method according to the present invention as shown in Fig. 3 is executed, the total processing time TSM₂ required for processing the total data is an addition of a time interval TZ_O during which the data processing steps executed by all the processors P_o to P₄ are overlapped with each other and time intervals TZ₁ and TZ₂ during which the above steps are not overlapped on both the sides of the time TZ_O. Therefore, when the tasks for each processor are allocated so that the above non-overlapped time may become short, it is possible to further shorten the total data processing time markedly as compared with the case shown in Fig. 2.

For instance, as shown in Figs. 3(A) to 3(D), when each divisional data processing execution time in each processing step is determined so as to be equal to each other, the total data processing time TSM₂ can be expressed as<maths id="math0002"><img file="EP0187518A2_D0002.tif" /></maths>where K denotes the number of divisional data in each divisional data processing step, DSP denotes the number of programs executed simultaneously (the number of processing steps PR₁ to PR₄ in Fig. 2), and TU denotes the divisional data processing execution time, respectively.

Therefore, in the system configuration as shown in Fig. 1, even if versatile microprocessors of relatively slow processor speed are incorporated, it is possible to realize a data processor provided with a operationally sufficient throughput suitable for processing the markedly great amount of image data from the standpoint of the total data processing time.

Further, the concurrent parallel processings of divisional data in the system configuration shown in Fig. 1 can be achieved when the arbitrator provided for the bus and the memory controller (MBC) in the shared storage device 2 processes the concurrence of processors in the subsystems connected to the system bus 1 in concurrent parallel fashion.

Shared Storage Device

As shown in Fig. 4, the shared storage device 2 is connected to each processor P₀, P₁, P₂ ... P₇ (referred to as P_i, i = 0, 1, 2 ... 7) in the six subsystems 5 to 10 and two preliminary units 11 and 12 through the system bus 1. The system bus 1 is determined so as to be exclusively used for a processor of a subsystem by controlling the system bus 1 and the memory unit 15 made up of the RAMs 2B and 2C (Fig. 1) in dependence upon the arbitrator 16.

In this embodiment, the system bus 1 is composed of an address data line ADDRESS of 20 bits, a read data line RDATA of 16 bits, a write data line WDATA of 16 bits, and a bus of bits 3 for transferring a read-write command R/W and high-order bite or low order bite selection signals LDS and UDS, the system bus 1 being terminated at the terminal 17.

The memory 15 is divided into eight memory banks _MB_O, _MB1 ... MB, (referred to as MB_j, j = 0, 1, 2 ... 7) having a memory capacity of 250 kilowords. Each system bus 1 is connected, to each memory bank MB_a to MB₇, so that each processor P_o to P₇ can access each memory bank separately. In the configuration as described above, while one memory bank is operating to read/write data (referred to as memory cycle), the other memory banks can be accessed. The system bus 1 is connected to the arbitrator 16. When mutually concurrent memory requests are outputted from the processors P₀ to P₇ in the eight subsystems to the memory section 15 through the system bus 1, the system configuration shown in Figs. 5 to 7 arbitrates the concurrence in order to execute the data processing in concurrent parallel fashion in response to all the memory requests. Here, the contents of the memory requests sent out from each processor are either the writing of data in the shared storage device 2 or the reading of data stored in the shared storage device 2.

The arbitrator 16 executes two arbitration tasks. The first task is to allocate memory banks MB_j (j = 0, 1, 2 ... 7) to which an occupation is acknowledged in response to the memory request when plural memory requests are outputted simultaneously from the eight processors P_i (i = 0, 1, 2 ... 7) to each memory section 15.

The second task of the arbitrator 16 is to arbitrate which processor P_i should be acknowledged to be occupied when the same memory request is outputted from plural processors P_i to the same memory bank M_Bj.

The arbitrator 16 has a time slot allocator 16A (_Fig. 5) for executing the first task. As shown in Figs. 6(A) to (H), this time slot allocator 16A generates eight time slot signals TS₀ to TS₇ (referred to as TS_j, j = 1, 2 ... 7) corresponding to the memory banks MB_O to MB₇ in sequence circulatively, and the fall time intervals (referred to as time slot) of each time slot signal TS_O to TS₇ are allocated in sequence to the processors P₀ to P₇ in the subsystems.

Here, the time slot intervals of each time slot signal TS₀ to TS₇ are selected to correspond to the processing time for unit data (for instance, 1 word) which are actually and sequentially processed. Therefore, the repetitive period of each time slot is determined to be sufficiently short as compared with the processing execution times TU₁ to TU₁₀ (Fig. 3) required for processing the divisional data. As described above, in practice, the divisional data are processed unit data by unit data.

Thus, in the case where memory requests <o>RQ</o>_<o>0</o>, <o>RQ,</o><o>RQ</o>_<o>2</o> ... <o>RQ</o>_<o>7</o> (referred to as <o>RQ</o>_<o>j</o>, j = 0, 1, 2, ... 7) are outputted from each corresponding processor P₀, P₁, P₂, ... P₇ during the time slot intervals of the time slot signals TS₀, TS₁, ... TS₇, enable signals <o>EN</o>_<o>0</o>, <o>EN</o>_<o>1</o>, <o>EN</o>_<o>2</o> ... <o>FN</o>_<o>7</o> (referred to as <o>EN</o>_<o>j</o>, j = 0, 1, 2, ... 7) are generated, respectively, which indicate that each processor P₀, P₁, P₂ ... P₇, respectively, of each subsystem outputting a memory request is acknowledged to occupy the memory banks MB₁, MB₂ ... MB₇ through the system bus 1 during the corresponding time slot interval. Here, when the memory requests of each processor P₀ to P₇ do not concur, the arbitrator 16 has the function (referred to as time slot allocation function) such that the memory request is processed by unconditionally using the time slot corresponding to the memory bank when a memory request to one of the memory banks MB_O to MB₇ is outputted.

Additionally, when no corresponding memory request is generated in each time slot of the time slot signal TS_j (j ⁼ 0, 1, ... 7), the arbitrator 16 has the function (referred to as time slot utilization function) such that the time slots having no corresponding memory requests can be utilized in order to process the memory requests to the memory banks allocated to the other time slots.

The above relationship can be expressed as follows:<maths id="math0003"><img file="EP0187518A2_D0003.tif" /></maths><maths id="math0004"><img file="EP0187518A2_D0004.tif" /></maths>where TS_j denotes the time slot signal allocated to the j-th memory bank MB_i (j = 0, 1, ... 7); <o>RQ</o>_<o>j</o> denotes the j-th request signal to the memory bank MB_j; and EN_j denotes an enable signal indicative of acknowledgement of the j-th memory bank MB_j to be occupied.

Here, the formula (3) indicates that the time slot signal TS_j (j = 0 to 7) generates continuonsly the time slots in sequence circulatively. In contrast with this, the formula (4) indicates that the enable signal EN_i to the j-th memory bank MB_j is generated at the timing of the time slot of the time slot signal TS_j allocated to the corresponding j-th memory bank MB_j (the first term TS_j) and that the request signal RQ_j-1 is not generated at the time slot corresponding to the (j-1)-th memory bank MB(j-1) and further the memory bank MB(j-1) corresponding to the corresponding time slot is at the no-use timing (the second term RQ_j-1. EN_j-1). As described above, the memory request is outputted to the j-th memory bank MB_j. When no memory request is outputted to the memory bank MB(j-1) corresponding to the (j-1)-th time slot, the request to the j-th memory bank MB_j can be processed by the preceding time slot.

This indicates that when there are no memory requests to the preceding time slots (that is; the (j-2)-th, (j-3)-th), the j-th memory bank MB_i can be accessed by the use of the time slots allocated to the (j-2)th, (j-3)th ... memory banks MB(j-2), MB(j-3) .... (referred to as previous dependence effect).

The above relationship of formula (4) can be expressed as enable signals EN₁ to EN₇ to each memory bank MB₀ to MB₇ as follows:<maths id="math0005"><img file="EP0187518A2_D0005.tif" /></maths><maths id="math0006"><img file="EP0187518A2_D0006.tif" /></maths><maths id="math0007"><img file="EP0187518A2_D0007.tif" /></maths><maths id="math0008"><img file="EP0187518A2_D0008.tif" /></maths><maths id="math0009"><img file="EP0187518A2_D0009.tif" /></maths><maths id="math0010"><img file="EP0187518A2_D0010.tif" /></maths><maths id="math0011"><img file="EP0187518A2_D0011.tif" /></maths><maths id="math0012"><img file="EP0187518A2_D0012.tif" /></maths>

In the formulas from (5) to (12), the term EN_j-1 in the second term expression RQ_j-1.EN_j-1 can be obtained by substituting the preceding expression, and the resultant expansion expressions indicates that an enable signal EN_j for acknowledging data in the j-th memory bank to be processed by the use of an empty slot when the empty slot is present in the other j-th or less time slots can be obtained, thus the previous dependence effect being obtained.

The arbitrator 16 further includes a memory access controller 16B (Fig. 4). This memory access controller 16B has decode means 16B11 to 16B17 (referred to as 16B1_i, i=0,1,...7) corresponding to the processors P_o to P₇ as shown in Fig. 7, which receive the memory request signals P_iMRQ (i=0,1,...7) indicative of the fact that memory request is outputted from each processor P_i (i=0,1,..7) and memory bank number data <o>P</o>_<o>i</o><o>RA1, P</o>_<o>i</o><o>RA2</o>, <o>P</o>_<o>i</o><o>RA3</o> (i=0,1,...7) indicating the numbers of the designated memory banks as a three bit signal. Therefore, a four bit signal, indicative of the memory bank to which the memory request is outputted from the corresponding processor P_i, is inputted to the decode means 16 B1_i.

In response to this input signal, the decode means 16 B1_i generates a memory bank designation signal to <o>PRQ</o>_<o>i0</o> to <o>PRQ</o>_<o>i7</o>, (i=0,1,...7) indicative of a designated memory bank. In these memory bank designation signals <o>PRQ</o>_<o>i0</o> to <o>PRQ</o>_<o>i7</o>, the subscript indicates that a memory request is outputted from the i-th processor to the 0-th to 7-th memory banks MB₀ to MB₇. These signals are distributed to memory access means 16B20 to 16B27 (referred to as 16B2_j, j=₀,₂,...₇) provided in correspondence to the memory bank MB_O to MB₇.

That is to say, memory bank signals <o>PRQ</o>_<o>00</o> to <o>PRQ</o>_<o>70</o> for designating the 0-th memory bank MB₀ are collected to the 0-th memory access means 16B20 from among the memory bank designation signals generated from the decode means 16B11 to 16B17; and so on; memory bank signals <o>PRQ</o>_<o>07</o> to _<o>PRQ77</o> for designating the 7-th memory bank MB₇ are collected to the 7-th memory access means 16B27 from among the memory bank designation signals generated from the decode means 16B11 to 16B17.

To express the above in general, the memory bank designation signals <o>PRQ</o>_<o>oj</o> to <o>PRQ</o>_<o>7j</o> (referred to as <o>PRQ</o>_<o>ij</o><o>,</o> i=0,1,...7, j=0,1,...7) for designating the j-th memory bank MB_j are collected to the j-th memory access means (16B2_j (j=0,1,...7) from among the memory bank designation signals generated from the decode means 16B11 to 16B17.

As shown in Fig. 8, the memory access means 16B2_j latches the memory bank designation signal PRQ_ij by a latch circuit 25 in dependence upon a clock signal φ. This clock φ is used for acknowledging the arbitrator 16 to be operated in synchronization with the memory banks MB_O to MB₇ and the processors P_o to P₇, and is generated in synchronization with the bus clock BCLK.

The memory request latched by the latch circuit 25 is inputted to a two-input NAND gate 27 through a NOR gate 26. To this NAND gate 27, a busy signal <o>BUSY</o>_<o>j</o> supplied from the memory bank MB_j allocated to the corresponding memory access means 16B2_j is given as the second condition input. This busy signal <o>BUSY</o>_<o>j</o> is generated when the j-th memory bank MB_j is not in memory cycle operation. Therefore, at the output terminal of the NAND gate 27, when a memory request is outputted from any of the processors, a request signal RQ_j can be obtained under the condition that the corresponding j-th memory bank MB. is not in memory cycle operation. This request signal <o>RQ</o>_<o>j</o> is supplied to the time slot allocator 16A as already described with reference to Fig. 5.

Therefore, although the time slot allocator 16A generates an enable signal <o>EN</o>_<o>j</o> at the timing of the time slot TS_j indicative of the formula (4) with respect to the request signal RQ_j, this enable signal <o>EN</o>_j is returned to one input of a 2-input NAND gate 28 in the memory access means 1682_j. To the other input of this 2-input NAND gate 28, the request signal <o>RQ</o>_j is inputted, so that an output enable signal EN_O is outputted at the timing of the time slot to which this request signal <o>RQ</o>_j is allocated after the request signal RQ. has been generated. This output enable signal EN_O is latched by a latch circuit 29 in dependence upon the clock φ and the latch output is outputted as a latch enable signal <o>φSEN</o>_j to an output latch circuit 30.

The latch output <o>φSPRQ</o>_ij of the latch circuit 25 is given to a priority selector 31 for selecting a memory bank designation signal of the highest priority level from among a plurality of memory bank designation signals coming thereto simultaneously. The selected memory bank designation signal is then applied to the output latch circuit 30. As described above, the output latch circuit 30 latches the memory bank designation signal <o>φPRO</o>_ij selected by the priority selector 31, and outputs this signal as occupation acknowledgement signal P_OACK to P₇ACK, (referred to as <o>P</o>_<o>i</o><o>ACK</o> i=0,1,...7). This occupation acknowledgement signal <o>P</o>_<o>i</o><o>ACK</o> is a signal which acknowledges that the i-th processor p_i outputting a memory request to the corresponding j-th memory bank MB. can occupy the system bus 1.

Therefore, the signals to the same processor P_i are collected from among the occupation acknowledgement signals P_iACK outputted from the memory access means 16B2_j (j=0,1,...7) (Fig. 7), and outputted as an output 21 of the memory access controller 16B.

As described above, the occupation acknowledgement signal <o>P</o>_<o>i</o><o>ACK</o> obtained by the memory access controller 16B is returned from the arbitrator 16 to the processor P_i from which a memory request has been outputted as an operation enable signal; as a result, the processor P_i begins to operate in order to send data to the system bus 1.

The priority selector means 31 receives the latch output <o>φPRQ</o>_0j to <o>φPRQ</o>_<o>7j</o> (referred to as <o>φPRQ</o>_ij, i=0,1,...7; j=0,1,...7) of the latch circuit 25, as shown in Fig. 9, and outputs a priority selection output signal <o>φPRQ</o>_<o>0j</o> to <o>φPRQ</o>_<o>7j</o> (referred to as <o>φPRQ</o>_<o>ij</o>, i=₀,₁,...7; j=0,1,...7) beginning from the one having the higher priority level, when these memory bank designation signals have come thereto simultaneously.

In the case of this embodiment, the priority level has previously been determined as shown in Fig. 10. As already described with reference to Fig. 4, the pro- ^cessors P₀, P₁, P₂, P₃, P₄, P₅, P₆ and P₇ are allocated in sequence to the file storage device (SPS) 5, the data transmitter (NTS) 6, the image read printer (IDS) 7, the image information compressor/decompressor system (CDS) 8, the operation display system (DPS) 9, the main controller (PCS) 10, the preliminary unit 11, and the preliminary unit 12. The priority level is so determined as to become higher in this order. The priority level is determined in such a way that a higher level is allocated to a subsystem including a device to which the necessity of real time processing is high when the memory request is generated, for instance, such as the HDD 5C provided in the file storage device as an external storage device.

As described above, the priority selection output signal <o>PRO</o>_<o>0j</o>, <o>PRO</o>_<o>1j</o> ... <o>PRO</o>_<o>7i</o> includes the contents of the memory bank designation signal <o>PRQ</o>_<o>0j</o>, <o>PRQ</o>_<o>1j</o> ... <o>PRQ</o>_<o>7j</o> coming on the basis of the memory request outputted from the processor P₀, P₁ ... P₇; the output latch circuit 30 latches the priority selection output <o>φPRO</o>_<o>0j</o>, <o>φPRO</o>_<o>1j</o> ··· <o>φPRO</o>_7j, respectively; and the priority acknowledgement signal <o>P</o>_<o>O</o><o>ACK, P</o>_<o>1</o><o>ACK</o> ... <o>P</o>_<o>7</o><o>ACK</o> are outputted.

As described above, in the case where the i-th memory bank MB_j is desiqnated by a plurality of processors simultaneously, one priority selection output signal corresponding to the highest priority memory bank designation signal is latched by the output latch circuit 30, the occupation acknowledgement signal <o>P</o>_<o>i</o><o>ACK</o> is given to the processor P_i corresponding to this one priority selection output signal, so that only the corresponding processor P_i can occupy the system bus 1.

In this embodiment, a lock means 32 is provided in the priority selector means 31 (Fig. 8), so that in the processor P_i to which the occupation acknowledgement signal P_iACK is given on the basis of the priority selection output signal <o>ØPRO</o>_<o>ij</o> obtained and selected by the priority selector means 31, the memory requests from the other processors are refused until a predetermined data processing has been completed, that is, the data processing with respect to the j-th memory bank MB_i is maintained.

The function of the lock means 32 as described above is executed on the basis of the program stored in the local memory 10c (Fig. 1) in the main controller 10. Therefore, in the present embodiment, once a memory bank designation signal is selected as the highest priority from among those coming simultaneously at a point of time, even if thereafter another memory bank designation signal of a higher priority comes before the processor corresponding to the selected memory bank designation signal will have completed a series of the data processings, the signal of higher priority is neglected and, the j-th memory bank is kept occupied by the previously selected processor.

Further, with respect to specified memory areas in the memory areas of the j-th memory bank, the lock means 32 locks in such a way that the data are allowed to be updated only when the memory bank designation signal based on the memory request from a predetermined processor is selected by the priority selector means 31, so that data stored in a predetermined memory bank can be saved.

Further, the arbitrator 16 includes a memory bank enable signal generator 16c (Fig. 4). This memory bank enable signal generator I6c, as shown in Fig. 11, has a latch circuit 41 for receiving enable signals EN outputted from the time slot allocator 16A (Fig. 5). This latch circuit 41 latches the enable signals EN in dependence upon the clock ø, and outputs the latch outputs as bank enable signals <o>BENB</o>_j respectively.

This bank enable signal BENB_jis given to the j-th memory bank as an operation enable signal, so that the j-th memory bank MB_j begins the operation such that data are received from the system bus 1 or data stored therein are sent to the system bus 1 (a series of the above operation is called memory cycle).

In this memory cycle operation status, the j-th memory bank MB_j does not output the busy signal <o>HUSY</o>_<o>j</o> to the arbitrator 16, so that the present memory cycle operation is known to the arbitrator 16.

As described above, during the operation of the memory banks MH₀ to MB_7' the bus clock BCLK is supplied from the arbitrator 16 to each memory bank in order to operate the memory bank in synchronization with the processors P_o to P₇via the arbitrator 16.

As shown in Fig. 12, the memory bank MB configuring the memory section 15 (see Fig. 4) is made up of memory areas 45 composed of dynamic RAMs, for instance, and a controller 46. The address data AD coming through the address data line ADDRESS in the system bus 1 are latched by the address latch circuit 47 in response to the leading edge of the bus clock BCLK, for instance. The latch output is separated into row data and column data in an address multiplexer 48 to designate a row address and a column address of a memory location to be processed in the memory area 45.

On the other hand, write data WD coming through the write data line WDATA in the system bus 1 is latched by a write data latch circuit 49, and the latch output is inputted to the memory area 45. Further, memory data MD read from the memory area 45 is latched by a read data latch circuit 50 and the latch output RD is sent out to the read data line RDATA in the system bus 1 in response to an output timing signal generated by a memory control logic 52.

Further, the memory controller 46 includes an arbitrate logic 51, and receives the selection signal supplied from a high level bite selection line LDS and a low level bit selection line UDS in the system bus 1, a write/read command signal R/W, and a bank enable signal BENB_j supplied from the arbitrator 16, in order to drive and control the memory bank MB_j on the basis of these signals. That is, by applying a drive signal at a predetermined timing to the row and column of the memory area 45 through the memory control logic 52, data is stored at a memory location having a row and a column designated by an address multiplexer 48, or the data is read at this memory position.

Further, under the control of an arbitration logic 51, a refresh address counter 54 is driven by a refresh control logic 53, in order to refresh each memory cell in the memory area 45 in sequence at predetermined time intervals, of, for instance, 14 sec, for saving the stored data.

Operation of the Embodiment

In the configuration as described above, the data processors execute data processing in synchronization with the bus clock BCLK shown in Fiq. 13(A). In this embodiment, the period of the bus clock BCLK is selected to be shorter than a cycle time required when each memory bank M_BO to M_B7 in the memory section 15 operates once to read write data (in the case of dynamic RAMs, a cycle time of 230 nsec is required for precharge and refresh operations), for instance, such as one-third; that is, the period TCK is 76.7 nsec. Each system unit is operated in synchronization with the leading or trailing edges of this bus clock BC_LK.

The time slot allocator 16A in the arbitrator 16 generates the time slot signals TS_O to TS₇ (Fig. 6) having a time slot corresponding to one period (time segment TCK) on the basis of this bus clock BCLK, and allocates the time slots to the 0-th to 7-th memory banks MB_O to MB₇ for each succeeding one period time segment of the bus clock BCLK, so that the system is accessed to read and write data from and to the memory banks MB₀ to MB₇ for each time slot.

Assume, for the sake of example, that at the time point t₁ in Fig. 13, a memory request is outputted from the i-th processor P_i to the j-th memory bank MB_j. At this time, a memory request signal <o>P</o>_<o>i</o><o>MRQ </o>(Fig. 13(B)) representative of the presence of memory request and a memory bank number signal P_iRA1 to <o>P</o>_<o>i</o><o>RA3 </o>(Fig. 13(C)) representative of that the memory position in the j-th memory bank MB_j is accessed are given from the processor P_i to the arbitrator 16B. These signals are supplied to the i-th decode means 16B1_i of the memory access controller 16B (Fig. 7), being decoded into a memory bank designation signal PRQ_ij (Fig. 13(E)), and then supplied to the j-th memory access means 16B2_j.

The memory access means 16B2_j (Fig. 8) receives this memory bank designation signal PRQ_ij by the latch circuit 25 and this signal is latched in response to the clock 0 synchronized with the bus clock BCLK. As a result, after the memory bank designation signal <o>PRQ</o>_<o>ij</o> has been generated, the latch circuit 25 generates a latch output <o>ØPRQ</o>_<o>ij</o> (Fig. 13(F)) at the time point t₂ when the bus clock BCLK rises first.

Where the j-th memory bank MB_j to which the memory request is outputted from the processor P_i is not in memory cycle operation at the time point t₂ at which the latch output <o>ØPRQ</o>_<o>ij</o> is generated, a busy signal <o>BUSY</o>_<o>i</o> is given from the memory bank MB_j to the arbitrator 16 (Fig. 13(G)). Therefore, when the latch output <o>ØPRQ</o>_<o>ij</o> the logic level of which is reversed through the NOR circuit 26 is given to the NAND gate 27 in the memory access means 16B2_j (Fig. 8), a request signal R_Qj (Fig. 13(H)), the logic level of which falls, can be obtained at the output terminal and applied to the time slot allocator 16A (Fig. 5).

As described with reference to formula (4), the time slot allocator 16A generates an enable signal <o>EN</o>_<o>j</o> (Fig. 13(1)) at the timing of the time slot allocated to the j-th memory bank MB_j from which a memory request is outputted, and returns this signal to the NAND gate 28 in the memory access means 16B2_j. Since a request signal RQ_j is given to this NAND gate 28, the output ENO is latched by the latch circuit 29 at the timing of the succeeding clock Ø, so that at this timing t₃, a latch output enable signal <o>ØEN</o>_j(Fig. 13(J)) is outputted.

When the latch output <o>ØPRQ</o>_<o>ij</o> (Fig. 13(F)) is given to the priority selector means 31 in the memory access means 16B2_j, this priority selector means 31 operates for priority selection. Here, if the memory request is not competitive to the j-th memory bank HB_j, the priority selector means 31 gives a priority selection output <o>ØPRO</o>_<o>ij</o> (Fig. 13(K)) corresponding to the latch output <o>ØPRQ</o>_<o>ij</o> to the output latch circuit 30. Therefore, the output latch circuit 30 begins the latch operation in response to the clock 0 when the latch output <o>ØEN</o>_j(Fig. 13(J)) of the latch circuit 29 is generated on the basis of the clock 0, and outputs an occupation acknowledgement signal <o>P</o>_<o>i</o><o>ACK</o> (Fig. 13(_M)) to the i-th processor P_i.

The processor P_i which receives this occupation acknowledgement signal P_iACK restores the output of the memory bank designation signal PRQ_ij (Fig. 13(E)), and then outputs an address data AD (Fig. 13(0)) to the address data line ADDRESS in the system bus 1. At the same time, when the processor P_i writes data in the memory bank MB_j which has outputted the memory request, the processor P_i outputs the data WD to be written to the data line WDATA, and lowers a write/read instruction R/W (Fig. 13(D)) to a write-mode level.

As described above, it is possible to realize the state where the i-th processor P_i occupies the system bus 1.

In this state, since a bank enable signal <o>BENB</o>_<o>j</o> (Fiq. 13(L)) synchronizing with the bus clock BCLK is given from the arbitrator 16 to the j-th memory bank MB_j, the address data AD (Fig. 13(0)) and the write data WD (Fig. 13(P)) in the address bus ADDRESS are latched by the address latch circuit 47 and the write data latch circuit 49 in the memory bank MB_j (Fig. 12) at the time point of the first leading edge of the bus clock BCLK.

Once this latch state is obtained, the memory control logic 52 in the memory bank B_i generates a row address signal RAS (Fig. 13(R)) and a column address signal CAS (Fig. 13(S)) to the memory area 45 and simultaneously lowers a write/read control signal WE (Fig. 13(T)) to the write-mode level. Therefore, the write data WD latched by the write data latch circuit 49 is written at the memory location designated by the address data latched by the address latch circuit 47 in the memory area 45 of the memory bank M_Bj.

As described above, it is possible to transfer and write data in the shared storage device 2 through the system bus 1 on the basis of the memory request <o>P</o>_<o>i</o><o>MRQ</o> (_Fig. 13(_B)) outputted from the i-th processor P_i.

In Fig. 13, the operation has been described for the case where data is written from the i-th processor P_i to the j-th memory bank MB., that is, of the write mode. However, when the i-th processor P_i reads data stored in the j-th memory bank MB in the so-called read mode, the data is read under the control of the arbitrator 16, as shown in Fig. 14.

In Fig. 14 which corresponds to Fig. 13, when a memory request <o>P</o>_<o>i</o><o>MRQ</o> (Fig. 14(B)) is generated from the i-th processor P_i at the time point t₁, similarly to the case of Fig. 13(A) to (N), the arbitrator 16 receives a request signal <o>RQ</o>_<o>j</o> on the basis of the memory request in the memory access means 16B2_j (Fig. 8), and generates an enable signal <o>EN</o>_<o>j</o> (Fig. 14(1)) at the time slot corresponding to the j-th memory bank MB. in the time slot allocator 16A (Fig. 5). On the basis of this enable signal <o>EN</o>_<o>j</o>, the memory access means 16B2_j gives an occupation acknowledgement signal <o>P</o>_<o>i</o><o>ACK</o> to the i-th processor P_i (Fig. I4(M)), and further the memory bank enable signal generator 16C (Fig. 11) generates a bank enable signal <o>BENB</o>_<o>j</o> (Fig. 14(L)) to the j-th memory bank MB_j.

As a result, the processor P_i outputs an address data AD to the address line ADDRESS (Fig. 14(O)). At this time, a memory bank designation data signal <o>P</o>_<o>i</o><o>RA1</o> to P_iRA3 is supplied from the processor P_i to the arbitrator 16 together with the memory request <o>P</o>_<o>i</o><o>MRQ</o> (Fig. 14(B)). Simultaneously, since a read/write instruction R/W (Fig. 14(D)) is given to the system bus 1, a bank enable signal B<o>ENB</o>_<o>j</o> of the memory bank MB_j is given to the arbitration logic 51 to maintain the write/read control signal WE of the memory control logic 52 at the read signal level (Fig. 14(T)) and also gives row and column drive signals RAS and CAS to the memory area 45. Therefore, in the memory area 45, the data MD stored at the memory location designated by the address data AD latched by the address latch circuit 47 is latched by the read data latch circuit 50.

The read data latched by the read latch circuit 50 is outputted as read data RD (Fig. 14(Q)) to the read data line RDATA in the system bus 1 at the timing of the trailing edge of a read data output signal RDEN (Fig. 14(_D)).generated by the memory controller 50 separately.

Therefore, it is possible to obtain the state where the data is read from the j-th memory bank MB_j while occupying the system bus 1 on the basis of the data read request of the i-th processor P_i. In this state, the arbitrator 16 sends a strobe signal <o>P</o>_<o>i</o><o>RSTB</o> (Fig. 14(N)) to the processor P_i to indicate that the requested data is outputted to the system bus 1.

At this moment, the processor P_i receives the data MD outputted to the system bus 1 since the strobe signal <o>P</o>_<o>i</o><o>RSTB</o> rises at the time point T₆ when the bus clock BCLK rises.

As described above, after a memory request has been outputted from the processor P_i and when a time corresponding to about four periods of the bus clock BCLK has elapsed, the data read from the memory block MB_i is received into the processor P_i.

As shown in Figs. 13 and 14, where only a single processor outputs a memory request to a given memory bank MB. at one point in time, since there exists no competitive relationship, whenever the processor P_i generates a memory request to the memory bank MB_j, the arbitrator 16 generates an enable signal <o>EN</o>_<o>j</o> at the time slot allocated to the corresponding memory bank MB_j, so that data is written or read in or from the memory location the address of which is designated according to the contents of the memory request. As described above, when non-competitive memory requests are generated to all the memory banks MB₀ to MB₇, basically the data processing is executed according to the contents of the memory request by the use of the time slot allocated to each memory bank.

In contrast with this, in a competitive state where a plurality of memory requests are outputted from a plurality of processors simultaneously to one memory bank MB_j and further where there exist memory banks MB₀ to MB₇ outputting no memory request, the arbitrator 16 processes the memory requests beginning from a memory request having the highest priority in sequence, and the data processing is executed by the use of the time slots allocated to the memory banks from which no memory request is outputted.

For instance, as shown in Fig. 5, the case will be considered such that: after a memory request P_iMRQ (Fig. 15(B)) having the contents of writing data from the i-th processor P_i to the j-th memory bank MB_j at the time point t_11i, at the time point t_11n at which the data processing to this memory request is not completed, a memory request <o>P</o>_<o>n</o><o>MRQ</o> (Fig. 15 (Bx)) having the contents of writing data from the n-th processor P_n to the j-th memory bank MB_j. In this case, since no processor outputs a memory request to the (j+3)-th memory bank MB(j+3), the time slot corresponding to that memory bank is empty.

At this state, the memory request <o>P</o>_<o>i</o><o>MPQ</o> qenerated at time point t_11i and the memory request <o>P</o>_<o>n</o><o>MRQ</o> generated at time point t_11n are both given to the arbitrator 16 in sequence, and the memory bank designation signals <o>PRQ</o>_<o>ij</o> and PRQ_nj are given to the memory access means 16B2_j (Fig. 8) corresponding to the j-th memory bank MB_j through the decode means 16B1_i and 16B1_n provided for the i-th and the n-th processors P_i and P_n.

First, at the time point t_11i, when a memory request having the contents of writing data is outputted from the i-th processor P_i to the j-th memory bank MB_i, in the same way as described with reference to Fig. 13, the time slot allocator 16A in the arbitrator 16 generates an enable signal <o>EN</o>_<o>j</o> during the time slot TS_i allocated to the j-th memory bank MB_j (Fig. 15° (I)), an occupation acknowledgement signal <o>P</o>_<o>i</o><o>ACK</o> is given from the memory access means 16B2_j (Fig. 8) to the i-th processor P_i on the basis of this enable signal EN_j. At the same time, the memory bank enable signal generator 16c generates a bank enable signal <o>BENB</o>_<o>j</o> corresponding to the j-th memory bank MB_j on the basis of the enable signal <o>EN</o>_<o>j</o> during the period of the bus clock next to the time slot TS_i (Fig. 15(L)).

Therefore, the processor P_i outputs an address data AD_i (Fig. 15 (O)) and a write data WD_i (Fig. 15(P)) to the system bus 1, and in the memory bank _MBi these data are latched at the time point t_l4 by the address latch circuit 47 and the write data latch 49 (Fig. 12).

When a memory request P_nMRQ (Fig. 15(Bx)) having the contents of writing data is outputted at the time point t_11n from the processor P_n to the memory bank MB_j before the above-mentioned cycle during which data is written from the processor P_i to the memory bank MB_j is not completed, a latch output <o>ØPRQ</o>_<o>nj</o> corresponding thereto is supplied from the latch circuit 25 in the memory access means 16B2. (Fiq. 8) to the priority selector 31. However, at this time point t_11n, since the latch output <o>ØPRQ</o>_<o>ij</o> (Fig. 15(F)) has already been given from the latch circuit 25 on the basis of the memory request from the processor P_i, the priority selector means 31 is already in a state where the latch output <o>PRQ</o>_<o>ij</o> is selected with priority and outputs an occupation acknowledgement signal P_iACK corresponding thereto. Since this state is not changed even if the latch output <o>ØPRO</o>_<o>nj</o> is given to the priority selector means 31 at the time point t_11n, the present state is maintained provided that the memory request P_iMRQ (Fig. 15(B)) from the processor P_i does not disappear and therefore no latch output <o>ØPRQ</o>_<o>ij</o> is supplied to the priority selector 31. As a result, the data processing on the basis of the memory request PMRQ (Fig. 15(Bx)) from the processor P_n is kept waiting until the data processing on the basis of the memory request P_iMRQ from the processor P_i has been completed.

As already explained, in the priority selector means 31 (Figs. 9 and 10), the above relationship is applied as it is even if the priority level of the n-th processor P_n is higher than that of the i-th processor P_i. This is because it is necessary to execute data processing securely by maintaining the data processing cycle of data previously selected on the basis of priority level until the data processing has been completed even if the memory request is outputted from the processors of low priority level.

The above-mentioned stand-by state is maintained until the data _ADi and _WDi latched by the memory bank MB_j have been written at the time point t₁₅ on the basis of the row and column designation signals RAS (Fig. 15(R)) and CAS (Fig. 15(S)) and the write/read control signal WE (Fig. 15(T)) to the memory area 45. When data writing has been completed at the time point t₁₅, the memory bank MB_i reverses the busy signal 3USY_i (Fig. 15(G)) and informs the arbitrator 16 that the memory cycle of the memory bank MB_j has been completed.

At this moment, the memory access means 16B2_j (Fig. 8) in the arbitrator 16 lowers the logic level of the request signal <o>RQ</o>_<o>j</o> (Fig. 15(H)) by the NAND gate 27 according to the change of the busy signal <o>BGSY</o>_<o>j</o>. Here, the latch output <o>ØPRQ</o>_<o>ij</o> (Fig. 15(F)) of the processor P_i in which the processing has already been completed is not obtained in the latch circuit 25; however, the latch output <o>ØPRQ</o>_<o>nj</o> (Fig. 15(FX)) of the processor P_n is still obtained, so that the request signal <o>RQ</o>_<o>j</o> immediately responds to the change of busy signal <o>BUSY</o>_<o>j</o>.

Therefore, the request signal <o>RQ</o>_<o>j</o> is generated during the time slot TS_n allocated to the (j+3)-th memory bank MB (j+3), the time slot allocator 16A (Fig. 5) determines that the time slot allocated to the (j+3)-th memory bank MB (j+3) is empty and, as stated with reference to the formula (4), outputs an enable signal <o>EN</o>_<o>j</o> (Fia. 5(I)) for the j-th memory bank MB_j at the timing of the empty time slot TS_n.

Therefore, the output latch 30 in the memory access means 16B2_j latches a priority selection output <o>ØPRO</o>_<o>nj</o> outputted from the priority selector means 31 and outputs a priority acknowledgement signal P_nACK corresponding thereto to the n-th processor P_n. At the same time, since the enable signal EN_j is obtained again, a bank enable signal <o>BENB</o>_<o>j</o> is outputted from the memory bank enable signal generator 16c (Fig. 11) at the succeeding period of the bus clock BCLK (Fig. 15(L)).

Therefore, the processor P_n outputs the address data AD_n (Fig. 15(O)) and the write data WD_n (Fig. 15(P)) to the system bus 1, and writes these data on the basis of the signals PAS, CAS, and WE, after the memory bank MB_j (Fig. 12) latches these data in the address data latch circuit 47 and the write data latch circuit 49.

When the above write operation has been completed. the memory bank MB_i reverses the busy signal <o>BUSY</o>_<o>j</o> to inform the arbitrator 16 that the corresponding memory cycle has been completed, being returned to the original state.

As described above, when the memory requests from a plurality of processors are generated in sequence to the same memory bank, the arbitrator 16 arbitrates the competition in such a way as to sequentially acknowledge the occupation of the system bus 1 and the designated memory bank to each processor in accordance with the order of occurrence. And in executing the data processing to a plurality of memory request in sequence, if some time slot is empty other than the time slot allocated to the j-th memory bank MB to which the memory request is made, the data processing is executed by the use of this empty time slot. Further, in Fig. 15, there has been described the case where the competitive relationship can be arbitrated when a plurality of memory requests are generated sequentially with some time difference. However, in the case where a plurality of memory requests are generated simultaneously without time difference, the competition of the memory requests can be arbitrated in the same way as described above, except that the priority selector means 31 selects a processor of higher priority level (Fig. 10) from among the ones which generates a memory request and generates occupation acknowledqement signals sequentially.

With reference to Fig. 15, the case has been described where the contents of two competitive memory requests require that data are written in the memory bank. However, in the case where the contents require that data stored in the memory bank are read, the arbitrator 16 operates as shown in Fig. 16. The difference between the case described with reference to _Fig. 16 and the case described with reference to Fiq. 15 is that the read time required to read data from the memory bank is longer than that required to write data therein, but.the operation of the arbitrator 16 is otherwise the same as in Fig. 15.

That is, in this case, the memory bank enable signal <o>BENB</o>_<o>j</o> (Fig. 16(L)) outputs the address data AD (_Fig. 16(O)) to the system bus 1 on the basis of the enable signal <o>EN</o>_<o>j</o> generated during the time slot TS_i, and the data is latched by the address latch circuit 47 in the memory bank MB_j. This latch output designates the memory location on the basis of the row and column drive signal RAS and CAS and the write/read control signal WE having a read mode level, so that the stored data is read from the memory area 45 and latched.

This latch output is outputted to the system bus 1 in response to the read data output signal RDEN (Fig. 16(U)) generated during the succeeding one period of the bus clock BCLK, so that it is possible to obtain the state where the read data RD_i (Fig. 16(Q)) corresponding to the memory request is outputted from the i-th processor P_i to the system bus 1. When the memory bank MB_i outputs data to the bus 1 as described above, at the time point t₁₅ the signal level of the busy signal <o>BUSY</o>_<o>j</o> (Fig. 16(G)) is reversed to inform the arbitrator 16 that the memory cycle has been completed. Therefore, the arbitrator 16 gives the strobe signal P_iRSTB (Fig. 16(N)) to the processor P_i, so that the processor P_i receives the data RED_i outputted to the system bus 1 at the timing of the leading edge of the strobe signal P_iRSTB at the time point t₁₆. As described above, it is possible to read the data from the memory bank MB_j to the processor P_i during the four periods of the bus clock BCLK from the time point t_11j at which the memory request <o>P</o>_<o>i</o><o>MRQ</o> is generated from the processor P_i. The time required to read the data is fairly long as compared with the case in Fig. 15 where two periods are required to write data. However, although the time required for the whole reading operation is long as shown in Fig. 16, since the time required to occupy the bus system 1 successively is one cycle of the bus clock BCLK, it is possible to effectively avoid the problem of obstruction that exists when the processor P_n, standing-by the processing of data due to competition, occupies the system bus 1.

That is, in the case of Fig. 16, the busy signal <o>BUSY</o>_<o>j</o> indicative that data processing has been completed by the processor P_i changes at the time point t₁₅ in the same way as in Fig. 15. Therefore, in the case of Fig. 16, in order to process the data in the processor P , it is possible to generate the enable signal EN_j (Fig. 16(I)) during the time slot allocated to the (j+3)th memory bank MB (J+3). This enable signal <o>EN</o>_<o>j</o> is generated by the arbitrator 16. On the basis of this enable signal EN_j, an address data AD_n on the basis of the memory request of the processor P_n is outputted to the system bus 1 during the succeeding period of the bus clock BCLK, and latched by the address latch circuit 47 in the memory bank MB_i at the end time point t₁₀ of this period.

However, when the data on the basis of the memory request of the processor P_n is outputted to the system bus 1 as described above, since the data RD_i read from the memory bank MB_j on the basis of the memory request of the processor P_i have already been received by the processor P_i at the time point t₁₆, it is possible to avert the situation that two data are outputted to the system bus 1 simultaneously.

As described above, after the data stored at the memory position designated by the address data AD_n, outputted to the system bus 1, has been latched in the read data latch circuit 50, the latch output RDEN (Fig. 16 (U)) is outputted to the system bus 1 and the data is received in the processor P_n at the timing of the leading edge of the strobe signal <o>P</o>_<o>n</o><o>RSTB</o> (Fig. 16 (NX)) generated in the arbitrator 16.

In the case where the data read time is long in the memory bank MB_j, it is possible to simultaneously start the data processing successively on the side of the arbitrator 16 while the reading cycle is being executed in the memory bank MB_j. Therefore, in sequentially processing these two data, it is possible to compress the time during which each data occupies the system bus 1 to the time corresponding to one period of the bus clock BCLK.

Further, also in the case of Fig. 16, the data is processed in such a way that the occupation of the system bus 1 is acknowledged in sequence beginning from the one having a higher priority level on the basis of the priority level (Fig. 10) allocated to each processor by the priority selector means 31 in the memory access means 16B2_j when two memory requests are generated simultaneously without time difference.

As must be clearly understood from Fig. 13 or Fig. 16, the enable signal <o>EN</o>_<o>j</o> is generated during the time slot allocated to the j-th bank, and the bank enable signal <o>BENB</o>_<o>j</o> is generated during the succeeding time slot. Further, when a time period of about 1.5 times the period of the time slot has elapsed after the enable signal <o>EN</o>_<o>j</o> has been generated, the address data AD is outputted to the address data line ADDRESS, or the write data WD is outputted to the write data line WDATA if in write mode.

In contrast with this, when a time period of about 2 times the period of the time slot has elapsed after the enable signal EN. has been generated, the memory bank MB_i begins to operate data writing and data reading (that is, the memory cycle begins). In the data read mode, when a time period of about 2.5 times the period of the time slot has elapsed after the enable signal <o>EN</o>_<o>j</o> has been generated, the data RD read from the memory bank MB_j is outputted to the read data line RDATA. As a result, when a time period of about 3 times the period of the time slot has elapsed after the enable signal <o>EN</o>_<o>j</o> has been generated, the processor P_i can receive data stored in the memory bank MB..

The above operation is repeated whenever the enable signals EN_O to EN₇ are generated to the memory banks MB₀ to MB₇, and the enable signals EN_O to EN₇ are generated in sequence during the time slots allocated to the respective memory banks MB₀ to MB₇. Therefore, the times at which the data corresponding to the memory bus MB₀ to MB₇ is outputted to the address data line ADDRESS, the write data line WDATA, and the read data line RDATA are different from each other, that is, the sequence of the allocated time slots. Therefore, even when memory requests are generated at a timing mutually competitive to a plurality of memory banks MB₀ to _MB₇, the system bus 1 can securely write or read data in or from the shared storage device 2 in dependence upon the arbitration and without disorder.

Fiq. 17 shows the arbitration operation when four memory requests are outputted in the same way as described above with reference to Fig. 3. In this case, as shown in Fig. 17(A), a write request is outputted from i-th processor P_i to the j-th memory bank MB_j: a read request is outputted from n-th processor P to the k-th memory bank MB_k; a write request is outputted from the m-th processor P_m to the x-th memory bank MB_x; and a read request is outputted from the r-th processor P to the y-th memory bank MB_v, these requests being generated at the same time at the time point t₂₀.

Here if time slots TS_j, TS_k, TS_x, and TS_y are allocated in sequence to t₂₁ to t₂₂₁ t₂₂ to ^t_23'^t₂₃ to t₂₄ and t₂₄ to t25, as shown in Fig. 17(B), an enable signal <o>EN</o>_<o>j</o> corresponding to the j-th memory bank MB_j is generated in the time slot TS_j; an enable signal <o>EN</o>_<o>k</o> corresponding to the k-th memory bank MB_k is generated in the succeeding time slot TS_k; an enable signal EN_x corresponding to the x-th memory bank MB_x is generated in the succeeding time slot TS_x; and an enable signal _ENy corresponding to the y-th memory bank MB_y is generated in the succeeding time slot TS_y. As described above, when the enable signals EN_j, <o>EN</o>_<o>k</o>'<o>EN</o>_<o>x</o> and <o>EN</o>_<o>y</o> are generated in sequence in the time slots TS_j, TS_k, TS_x, and TS_y with a time difference of one time slot, according to these signals, the bank enables signals <o>RENB</o>_<o>j</o>, <o>BETZB</o>_<o>k</o>, BENB_x and <o>HENB</o>_<o>y</o> corresponding to each memory bank are similarly generated with a time delay of one time slot (Fig. 17(C)). Further, as shown in Fig. 17(D), addresses AD_i, SD_n, AD_m and AD corresponding to the memory banks MB_j, MB_k, MB and MB are outputted in sequence to the address data line ADDRESS with a time delay corresponding to one time slot.

As described above, address locations designated by the processors P_i, P_n, P_m and P_r in the memory banks MB_j, MB_K, MB_X and MB_y are designated in sequence without disorder, so that the memory banks MB_j, MB_k, MB and MB enter into the write or read memory cycle at the time points delayed one time slot by one time slot (Fig. 17(F)). When entering the memory cycle as described above, the processors P_i and P_m, which output a write request to the memory bank, output write data WD_i and WD to the write line WDATA at the timing at which the address data AD_i and AD are outputted to the address data line ADDRESS. Therefore, in the memory cycle of the memory banks MB_j and MB_x, the write data WD_i and WD are written respectively to the address locations corresponding to the address data AD_i and AD_m, so that the operation with respect to the memory requests of the processors P_i and P_m has been completed.

In contrast with this, in the processors P_n and P_r which output a read request to the memory bank, stored data is read in sequence to the read data line RDATA (Fig. 17(G)) from the address locations corresponding to the address data AD_n and AD_r in the memory banks MB_k and MB_y, and outputted in sequence to the read data line RDATA. The above times at which the read data RDATA is outputted to the read data line RDATA are different from each other, because the memory banks MB_k and MB_y begin to start the memory cycle on the basis of the allocated time slots at time points different from each other. Therefore, the processors P_n and P_r outputting read requests can receive the data read from the memory bus banks and MB_y without disorder through the read data line RDATA.

In spite of the fact that each memory cycle of the memory banks MB_j, MB_k, MB_x and MBy itself is longer than the time slot, the timing at which data is received from the system bus and the timing at which read data is outputted to the system bus 1 are executed in sequence at one time slot timing, so that the access to the system bus 1 corresponds to one time slot time in practice.

In the same way, in the processors P_i, P_n, P_m and P_r, the timing at which a data is sent out to the system bus 1 and the timing at which a data is received from the system bus 1 are both within one time slot time. Therefore, even if a time longer than one time-slot time is required in sending out data to the system bus 1 and if a device is used which requires a time longer than one time-slot time in processing the received data, since the processor functions in relation to the system bus 1 only during one time slot, even if the data processing time in the processors P_i, P_n, P_m and P_r is much longer than one time-slot period, the processor functions as a device which can operate during one time-slot time to the system bus 1.

Therefore, even if a dynamic memory of a long memory cycle is applied as the memory banks and further microprocessors of low processing speed are used as the processors, the device can function to the system bus 1 as a device behaviorable and operable to the continuous time slots. Therefore, it is possible to extend the memory and the processor throughput in the whole of the time slots by that amount corresponding to the number of memory banks configuring the memory units and the number of microprocessors configuring the processors, thereby obtaining a data processor having sufficient data processing functions for practical use.

Further, although there exists a time interval during which a write data is sent from another processor to the system bus 1 at the timing when data is read from the shared memory device 2 to the system bus 1 (for instance, at the time point t₂₅ in Fig. 17), since the read data is sent to the read data line RDATA and the write data is sent to a different write data line WDATA, no disorder will be produced.

Other Embodiments will be described hereinbelow: <ul id="ul0002" list-style="none"><li>(1) In the above embodiment, the time slots are allocated to all the memory banks MB_a to MB₇. However, it is also possible to provide time slots to which no memory bank is allocated. In such a case as described above, the time slot allocator 16A (Fig. 5) in the arbitrator 16 determines the time slot to which no memory bank is allocated to be an empty channel on the basis of the previous dependence function based on the above-mentioned formula (4) and executes the data processing for the request to the memory bank to which the time slot is allocated. This method can hasten the processing of a memory request to the memory bank allocated to a time slot next to one to which no memory bank is allocated.</li><li>(2) In the case of the above-mentioned embodiment, as understood with reference to Fig. 1, the devices 5 to 12 allocated to each subsystem are so constructed as to perform each different allotted task. However, it is also possible to provide two or more subsystems for performing the same task. In this way, in the case where there exists a processing step in which an extremely complicated task is included among a series of data processing steps PR_O to PR₄ (Fiq. 2), it is possible to divide the task in the processing step into two or more subsystems. Therefore, in this case, since it is possible to make the data processing time at each processing step approximately equal to a constant time, it is possible to reduce the time during which a subsystem having completed the data processing earlier waits for another subsystem which has not yet completed the data processing, when each subsystem executes the processing of each divisional data simultaneously in parallel. Thus it is possible to expand the throughput of the whole processor.</li></ul>

Further, in the case where a processor in a subsystem must continue data processing after another processor in another subsystem has completed data processing because of an extremely large amount of data to be processed, it is possible to share the task to the processors in the subsystems in which the task has already been completed.

In this method, it is possible to effectively utilize the processor, stopping the operation after the processing of data allocated to itself has been completed, thus it being possible to shorten the data processing time required for the processor having a large task.

As described above, according to the present invention, a task is shared to a plurality of processors connected to a system bus respectively; a shared storage device provided in common for these processors is made up of a plurality of memory banks connected to the system bus respectively; data to be sent and received between the processors and the memory banks are divided into a predetermined amount of divisional data: the data processing is executed for each divisional data simultaneously in parallel fashion; and each memory bank can be occupied simultaneously in parallel fashion to each memory request outputted from each processor. Therefore, even if versatile devices of relatively slow data processing speed are used as the processor or the shared storage device, it is possible to realize a data processor of sufficiently large throughput as a whole. As a result, it is possible to construct a data processing system suitable to means for processing image data having an extraordinary large amount of data to be processed, without providing special specifications, in dependence upon versatile devices.

It will be understood by those skilled in the art that the foregoing description is in terms of a preferred embodiment of the present invention wherein various changes and modifications may be made without departing from the spirit and scope of the invention, as set forth in the appended claims.