Chip to pin interconnect method.

0001This invention relates to an integrated circuit package in accordance with claim 1 and a method of its manufacture.

0002Packaging of semiconductor devices have followed two separate and distinct paths. One utilizes the connection of the chip to rigid substrate structures such as is shown in U.S. Patent 3,871,0₁5 to Paul T. C. Lin et al. The other utilizes sets of leads fabricated on the surface of a flexible insulative tape with the chip beam bonded thereto by means of wire leads with the entire unit encapsulated in a plastic member. Such a structure is shown in U.S. Patent 4,157,611.

0003Attempts to improve this latter structure and avoid this wire bonding of leads has also been attempted as typified by U.S. Patent 3,868,724 wherein the leads mounted on the insulatlve tape have been provided with contact nodes that penetrate the tape through holes formed therein. These holes are in a predetermined pattern so that the contact nodes are formed in the holes and extend there through to provide an ohmic contact between the conductors and integrated circuit chips aligned with the contact nodes and bonded thereto. Ultimately, an encapsulation is formed around the entire chip and selected portions of the tape for completely housing the chip.

0004This technique requires careful and critical alignment of the semiconductor chip to the contact nodes and when the contacts on the chip are asymmetrical inaccurate bonding could result

0005It is therefore the object of the present invention to provide an improved integrated circuit package of the aforementioned kind and a method for its manufacture. This object is achieved by the invention as described in claims 1 and 3; embodiments of the invention are characterized in the subclaims.

0006The novel connecting structure for semiconductor devices uses an insulating film having conductive leads formed on a first surface thereof. A plurality of sets of holes are formed, in a predetermined pattern, in the film so as to expose the tips of the underlying conductors which are exposed so that an ohmic connection can be made to each of the conductors when a semiconductor chip having a plurality of surface input/output contacts such as solder balls thereon is aligned with the hole pattern provided in the insulating layer and subsequently bonded thereto. An encapsulation is then formed around the chip and adjacent portions of the insulating film for completely housing the chip therein while still providing external conductors extending beyond the encapsulation for connection to external circuitry.

0007This present invention has a number of advantages over the prior art in that superior electrical and thermal performance relative to wire bonding is achieved. Furthermore, this invention provides a package with a low profile structure and can be extended to high density stackable, two-sided tapes and assemblies. Also the present invention needs but a simplified bonding technique and is a very low cost product. Finally the invention assures that the chip is always properly aligned.

0008These and other advantages of the present invention will become apparent from the detailed description of the following preferred embodiment when taken with the following figure wherein; <ul id="ul0001" list-style="none"><li>Fig. 1 is a partial isometric view of an insulated lead frame made in accordance with the present invention, and</li><li>Fig. 2 shows a partial cross-sectional view of the insulated packaging strip of the invention taken generally along the lines 2-2 of Fig. 1 and with a semiconductor device bonded thereto.</li></ul>

0009Shown in Figs. 1 and 2 are partial sectional views of a sprocket driven semiconductor packaging lead frame 10 made in accordance with the present invention.

0010Generally the lead frame ₁0 comprises a lamination composed of an insulating film 11 affixed to a formed metal pattern 12. The metal pattern 12 is formed from a solid copper or copper alloy 88,9 µm (0.0035 inch) thick strip having an insulating film 11 formed thereon. The insulating film 11 generally consists of a 12,7 to 45,7 p_M (0.0005 to 0.0018 inch) thick film of polyimide.

0011Other suitable insulating materials, besides the described polyimide, can be used provided they can be treated in accordance with the invention as set forth below arid exhibit the proper durability, flexibility and compatibility with the semiconductor processing procedures to be used.

0012The preferred method of creating this lead frame 10 is as follows. A strip of copper, having parallel planar sides from 152,5 to 254 pm (0.006 to 0.010 inches) in thickness, of suitable width and having sprocket hole 15 formed therein is selected and its center portion is thinned, by any suitable technique, such as rolling, etching or stamping, down to 33 pm (0.0013 inches) in thickness. As shown in the figures, only the upper surface of the strip is thinned and the tower surface remains in its initial plane.

0013Once the strip is thinned a film of polyimide is formed on its bottom untreated surface, i.e. the bottom planar surface of the copper strip. This polyimide film is preferably from 12,7 to 45,7 pm (0.0005 to 0.0018 inches) in thickness and may be formed in situ by any suitable method such as casting, flowing on a liquid polyimide or the like.

0014Once the film of polyimide is laid down on the copper strip the copper strip is photolithographically etched to form the selected metallic pattern 12.

0015Specifically the formed metallic pattern 12 is composed of a plurality of metallic fingers or leads ₁3 joined to parallel selvage strips 14. Each finger or lead 13 is formed of a relatively thick portion 13a about 152,4 to 254 µm (.006 inches to .010 inches) in thickness and substantially thinner section 13b about 33 pm (0.0013 inches) in thickness. As shown the thinned portions 13b overlie the polyimide film 11 and are formed from the previously thinned central section of the copper strip.

0016It should be noted that the polyimide film 11 must be of sufficient width and length so as to extend beyond all edges of the chip to be placed thereon. This film not only insulates the chip electrically but also serves to protect the chip from radiation such as alpha particles.

0017It should also be noted that the thinned sections 13b of each lead provides easier bonding to the chip as well as stress relief.

0018The plurality of equispaced sprocket holes 15 in each selvage strip 14 are employed for indexing the lead frame 10 through the various stages of fabrication and process steps required both for forming the lead frame of the present invention and for bonding integrated circuit chips to the lead frame 10.

0019Once the desired pattern 12 has been formed on the insulating film 11, a series of holes, in accordance with the present invention are etched in the polyimide film ₁₁. A suitable process for etching these holes is described in U.S. Patent 4,353,778 to J. P. Fineman et ai, incorporated herein by reference. These openings as shown in Fig. 2 are formed in a pattern over the tip of each thinned lead 13b. This pattern is made to match the input/output contacts set out on the pattern of the chip to be joined to the unit. This input/output pattern, also known as the chip footprint, can be derived directly from the design criteria used for creating the chip surface connection on the chip itself.

0020Once these openings are suitably formed in the polyimide, the chip can be joined to the lead frame 10. If desired a thin coating of tin can be deposited in the holes in the pofyimide and on the exposed tips of the leads 13b to assure a better, lower temperature bond to the input/output connections on the chip. Of course it must be understood that if such a tin layer is used that it cannot be of any appreciable thickness and must be thin enough such the formed holes in the polyimide retain a depth sufficient to permit the holes to continue to serve to align the input/output connections of the chip placed thereon.

0021In the preferred embodiment, a semiconductor chip 16 previously dimensioned and provided with a plurality of electrical input/output contacts 17, such as solder balls, arranged in a desired pattern or footprint, is placed on the lead frame such that the contacts 17 are seated in the holes formed in the polyimide and contact the underlying leads 13b.

0022The contacts or solder balls 17 which are formed on the semiconductor chip 16 are well known in the art and typified in U.S. Patent 3,392,442 to J. Napier et al. These contacts 17 typically comprise a body of lead-tin alloy mounted on suitable electrical nodes formed on the surface of the semiconductor chip 16 which contacts 17 serve as input or output connections to the underlying electrical devices formed in the chip 16.

0023Once the integrated chip having contacts 17 arranged in a pattern or footprint corresponding to the openings in the polyimide film is positioned over and matched to the footprint previously opened or formed in the polyimide layer. The integrated circuit chip is self aligned to the underlying leads 13b and is then bonded to the exposed tips of the leads 13b by any suitable bonding technique, such as a heating element, for example a thermode brought into contact with the lead frame or by placing the entire unit in a suitable furnace or other heating medium. Once the solder balls on the chip are suitably bonded to the lead frame an encapsulation structure is formed around the circuit Such encapsulation structures can be of plastic as in the well known dual inline package (DIP) or can be formed of glass or ceramic. Finally, the encapsulated circuit chips and the extended fingers 13 are cut away from the selvage 14 and tested.

0024There has been described an integrated circuit package including a flexible insulated lead frame and a flip chip having a plurality of input/output solder balls in predetermined positions thereon. The lead frame is provided with a plurality of flexible metallic leads on an insulation coating. A plurality of openings is etched in the insulating coating over the ends of the leads to be connected to the contacts on the chip. These openings in the insulation are in the same pattern as the balls on the chip and act to assure that the chip is property positioned on the lead frame and that the solder balls are contained in a restricted area and provide significant electrical contact to the exposed lead frames.

0025It should now be obvious to those skilled in the art that various modifications can be made to the present invention. For example, the fingers 13 could be of sufficient length such they extend beyond the encapsulation and act as external leads or alternately could be joined for example by welding, to external leads.