Pre-processing of bi-level image data.

Field of the Invention

The invention relates to a method and an apparatus for processing bi-level image data which are supplied from an image data supply means, such as an image scanner, before the supply of the bi-level image data to a data compressor.

Prior Art

NIKKEI ELECTRONICS November 3, 1975, pp. 30-34 describes a pre-process of image data which is adaptable to a run-length coding. In the article, black image data and white image data of a reference line and a coding line (current PEL or scan line) are so re-arranged that the black image data, i.e. black bits, are grouped into a left half of a new line and the white image data, i.e. white bits, are grouped into a right half of the new line. The left half is called an Al sequence and the right half is called the A2 sequence. And, a new, unconventional coding scheme for adapting the Al and A2 sequences is further required.

Although the article relates to a pre-processing of bi-level image data, the detail of the process for the re-arrangement of the image data of the article differs from that of the present invention.

Problem solved by the Invention

The prior pre-process has required a complicated re-arrangement of the image data, as described in the above article. The present pre-process of the image data, which adapts said data to the conventional two-dimensional coding scheme and improves the compression ratio, was not disclosed therein.

Summary of the Invention

The bi-level image data supplied from an image supply means, such as an image scanner, are pre-processed by the method and/or apparatus of the present invention, and the pre-processed image data are then supplied to a compression means, which compresses the image data under the customary two-dimensional coding scheme, such as CCITT Recommendation T.4.

The method of the invention includes steps of: <ul id="ul0001" list-style="none"><li>detecting a changing element in a first scan line and a changing element in a second scan line,</li><li>determining whether the distance in the direction of scanning between said changing element in said first scan line and said changing element in said second scan line falls within a predetermined range,</li><li>arranging said image data such as to decrease said distance to a predetermined distance when said distance was falling within said predetermined range, and</li><li>supplying said arranged image data to a means for performing compression.</li></ul>

In one embodiment, the method of the invention includes the following steps: <ul id="ul0002" list-style="none"><li>detecting a changing element in a first scan line, a changing element in a second scan line and a changing element in a third scan line,</li><li>detecting a first distance between said changing element in said first scan line and said changing element in said second scan line and a second distance between said changing element in said second scan line and said changing element in said third scan line,</li><li>re-arranging said image data such as to selectively decrease said first or said second distance to a predetermined distance in accordance with conditions of said first distance and said second distance, and</li><li>supplying said re-arranged image data to a compression means for performing compression thereof.</li></ul>

Brief Description of the Drawings

<ul id="ul0003" list-style="none"><li>FIG. 1 shows an operational flow chart of the pre-process in accordance with an embodiment of the present invention.</li><li>FIG. 2 shows an example of the two-dimensional coding scheme.</li><li>FIGS. 3A-B, 4A-D, 5A-D, 6A-D show patterns which are pre-processed in accordance with the present invention, and</li><li>FIG. 7 shows a circuit block diagram for performing the pre-process in accordance with the present invention.</li><li>FIG. 8 shows an example of an original image used for the description of a second embodiment of the present invention.</li><li>FIG. 9 shows patterns which are pre-processed in the second embodiment of the present invention, and</li><li>FIG. 10 shows the pre-process operation in the second embodiment of the present invention.</li></ul>

Description of First Embodiment

The invention performs a pre-process of bi-level image data to reduce the amount of compressed data, which are compressed under a conventional two-dimensional coding scheme, such as provided by the CCITT Recommendation T.4.

Before describing the first embodiment of the present invention, the two-dimensional coding scheme of the CCITT Recommendation T.4, as a typical coding scheme, is described hereinafter.

The following Table 1 shows the two-dimensional code table of the CCITT Recommendation T.4. <tables id="tabl0001" num="0001"><img file="EP0179291A2_D0001.tif" /></tables>

Referring to FIG. 2, an exemplary pattern is shown for describing the coding scheme wherein the pel (picture element) "a₀" represents the reference or starting element on the coding line, the "a_l" represents the next changing element to the right of a₀on the coding line, and the "b₁" represents the first changing element on the reference line to the right of a₀and of opposite colour to a₀. As apparent from Table 1, the code words for |a₁b₁| ≤ 3 are of relatively short length.

Describing the basic concept of a first embodiment of the present invention with reference to FIGS. 3A through 6D, the invention detects a changing element C₁in a first scan line, a changing element C₂ in a second scan line and a changing element C₃ in a third scan line.

It is noted that: <ul id="ul0004" list-style="none"><li>- in the case that the first and second scan lines in the FIGS. 3A, 4A, 4C, 5A, 5C, 6A and 6C correspond to the reference and coding lines in FIG. 2, respectively, the changing elements C₁ and C₂ correspond to "b₁" and "a₁", respectively, and</li><li>- in the case that the second and third scan lines in the FIGS. 3A, 4A, 4C, 5A, 5C, 6A and 6C correspond to the reference and coding lines in FIG. 2, respectively, the changing elements C₂ and C₃ correspond to "b_l" and "a₁", respectively.</li></ul>

Next, e.g. referring to FIG. 3A, the invention detects a first distance Δ₁₂ between the changing element C₁ in the first scan line and the changing element C₂ in the second scan line, and also a second distance Δ₂₃ between the changing element C₂ in the second scan line and the changing element C₃ in the third scan line. The above operation is shown in blocks 1 through 5 in FIG. 1. The operation starts at block 1. Block 2 stores three scan lines into a three line buffer not shown. Block 3 detects the boundary 31 between the changing element C₁ and the next white element. Block 4 detects the boundary 32 between the changing element C₂ and the next white element. The boundary 31 relates to the boundary 32. Also, block 4 detects the distance Δ₁₂. Block 5 detects the boundary 33 which is related to the boundary 32. Also, block 5 detects the distance Δ₂₃'

The operation proceeds to block 6. The block 6 determines whether the formula 3 ^&lt; |Δ₁₂| ^&lt; x AND 3 ^&lt; |Δ₂₃| &lt; x is satisfied, or not. If |Δ₁₂| ≤ 3 or |Δ₂₃|≤ 3, as is the case in the FIGS. 4A, 4C, 5A, 5C, 6A and 6C, the answer of the block 6 is NO and the operation proceeds to block 8.

The distance |Δ₁₂| as well as |Δ₂₃| in the FIGS. 4A, 4C, 5A, 5C, 6A and 6C corresponds to one of the cases |a₁b₁|=1, |a₁b₁| ^{= 2}and |a₁b₁| ^{= 3} shown in the Table 1. If the distance |Δ₁₂| or |Δ₂₃| corresponds to one of the three cases, the invention, at block 8, re-arranges or converts the original bit patterns or image data shown in the FIGS. 4A, 4C, 5A, 5C, 6A and 6C to the bit patterns shown in FIGS. 4B, 4D, 5B, 5D, 6B and 6D, respectively.

The next Table 2 shows the bit conversion performed in block 8.

<tables id="tabl0002" num="0002"><img file="EP0179291A2_D0002.tif" /></tables>The reasons for performing the above conversions are: <ul id="ul0005" list-style="none"><li>(a) The number of bits of the code words for the cases a₁b₁ = 0 and a₁b_{1 =} 1 are "one bit" and "three bits", respectively, as shown in Table 1, while the number of bits of code words for the cases a₁b₁ 2 and a₁b_{1 =} 3 are "six bits" and "seven bits"; and</li><li>(b) The above conversion of the distance in accordance with the invention does not adversely affect the image fidelity of the original image data with a fine resolution, e.g., of 8 pels/mm. In other words, the original image is maintained even if the distance is converted.</li></ul>

The FIGS. 4A through 6D will be described in more detail later on.

If the formula 3 ^&lt; |Δ₁₂| ^&lt; x AND 3 ^&lt; |Δ₂₃| ^&lt; x is satisfied, the operation proceeds to block 7 via the YES path. The value of x is selected in advance, in accordance with the image fidelity which one desires. In other words, the value x is the upper limit for doing the pre-process, i.e. for not necessarily keeping the original image information within the converted image data. In the exemplary case, the value of x is selected to be "6". FIG. 3A shows one case producing a YES from block 6, wherein the value of A₁₂ is "4" and the value of Δ₂₃ is "5". Then, block 7 determines if |Δ₁₂| is larger than |Δ₂₃|. For the exemplary bit pattern shown in FIG. 3A, the block 7 produces a NO output, and the operation proceeds to block 10. Then, the original image data of FIG. 3A is re-arranged to reduce the distance Δ₁₂ to the value "3". The re-arranged image data is shown in FIG. 3B. It is noted that the total length of Δ₁₂ and A₂₃ in the original image data is maintained after the conversion, as it should be to keep the image fidelity of the original image data.

When |Δ₁₂| is larger than |Δ₂₃|, the YES output is produced, and the operation proceeds to block 9. No example for the process including block 9 is shown in the figures. In block 9, |Δ₂₃| of the original bi-level image data is reduced to "3", but the total length of |Δ₁₂| and |Δ₂₃| in the original image data is maintained in the re-arranged image data.

As apparent from the above, the blocks 8, 9 and 10 re-arrange the original image data to selectively decrease the distance 412 and/or A ₂₃ to one of a number of predetermined distances in accordance with the result of the test blocks 6 and 7.

The re-arranged image data, i.e. the pre-processed image data, in accordance with the present invention, are supplied to the compression means which compresses the data under the two-dimensional coding scheme of Table 1, for example, as shown in block 11, and the operation terminates at block 12.

Now describing the FIGS. 4A through 6D, the FIGS. 4A and 4C, FIGS. 5A and 5C and the FIGS. 6A and 6C show the original image data, which is the bi-level image data from a CCD (charge-coupled devices) sensor array of the document or image scanning apparatus.

The FIGS. ⁴A and ^4C show the case of Δ₁₂ = ¹ and ^A₂₃^{= 1,} the FIGS. 5A and 5C show the case of Δ₁₂ = 2 and Δ₂₃ = 2, and the FIGS. 6A and 6C show the case of Δ₁₂= 3 and ^A_{23 =} 3. The image data or bit pattern of FIG. 4A is converted to that shown in FIG. 4B by the aforementioned operation of block 8, and similarly the conversion from FIG. 4C to FIG. 4D, from FIG. 5A to FIG. 5B, from FIG. 5C to FIG. 5D, from FIG. 6A to FIG. 6B and from FIG. 6C to FIG. 6D are performed by said block 8.

FIG. 7 shows a circuit block diagram of an apparatus according to the invention for performing the operations shown in FIG. 1 and described with respect to the examples of FIGS. 3A through 6D.

The 3 pel x 3 pel window 71 samples or picks up each 3 x 3 square array of image bits in a document image. The exemplary resolution is 8 pels/mm in the horizontal direction and 8 scan lines/mm in the vertical direction.

The bit conversion or the pre-process of the original image data in accordance with the present invention, as shown in the FIGS. 3A through 6D, is performed by a conversion table 73. The bit pattern for each 3 x 3 window is applied as an address to the conversion table storage means 73 through a pattern register 72 to fetch a desired output bit pattern on an output line 74 or a control signal "Pattern Save" on a control line 77. The pattern register 72 stores the bit pattern of a single 3 x 3 window 71 or the bit patterns of plural 3 x 3 windows 71 in response to the Pattern Save signal from the conversion table 73.

Examples of the addresses and the stored bit patterns in the conversion table 73 are shown in the following Table 3. <tables id="tabl0003" num="0003"><img file="EP0179291A2_D0003.tif" /></tables>

For example, let it be assumed that the 3 x 3 window 71 samples the bit pattern shown in FIG. 4A. The bit pattern "100" of the first scan line, "110" of the second scan line and "100" of the third scan line are concatenated, or serially connected to "100110100", and this concatenated bit pattern is stored in the pattern register 72, and then supplied to the conversion table means 73. Referring to Table 3, at exemplary entry No. 1, the conversion table 73 has the above address and generates the output pattern "100100100". The output pattern "100100100" is supplied to the 3 line buffer 76 through an output line 74 and a gate 75. The gate 75 operates to assemble the serial output bit pattern "100100100" to the three line pattern shown in FIG. 4B. Thus, the input bit pattern of

FIG. 4A has been converted to the bit pattern of FIG. 4B.

The remaining entries 2 through 7 of Table 3 show the addresses and output bit patterns for FIGS. 4C through 6D and FIGS. 3A and 3B.

It is noted that in the cases of FIGS. 4C, 5A, 5C, 6A and 6C, the bit pattern enclosed by two windows 71 is used as a single address, and in the case of FIG. 3A, the bit pattern enclosed by four windows 71 is used as a single address. The reasons for the use of plural windows for forming a single address, will now be described. First referring to FIG. 4A, its bit pattern has all "0" bits in the third column, in other words, the boundaries from black to white for all scan lines are found in this single window. In contradistinction, the first 3 x 3 window of FIG. 4C does not include the black to white boundaries for all scan lines within it, so it can not be determined whether the black pels or elements continue into the subsequent window, or not. Accordingly, the second window is joined to the first window. The second window contains all "0" bits in the third column, whereby the black to white boundaries for all lines exist within the first and second windows.

To control the joinder of the subsequent window to the preceding window(s), the conversion table 73 generates the control signal "Pattern Save" on the control line 77 when a pattern, which does not include black to white boundaries for all lines, is applied to the table 73. The Pattern Save signal has a unique pattern, e.g. "111111111", which can be distinguished from all other output bit patterns, as shown in the entries n-6 through n in Table 3. For the case of FIG. 4C, the generation of the Pattern Save output is shown in entry n-6 of Table 3.

As a further example, in the process of the bit pattern of FIG. 3A, the supply of the bit pattern of the first 3 x 3 window to the conversion table 73 produces the Pattern Save output "111111111" causing a signal on the control line 77, as indicated in the entry n-2, and no output pattern is supplied to the output line 74. The Pattern Save signal applied to the pattern register 72 causes the bit pattern of the second window to be subsequently stored, concatenated to the bit pattern of the first window, in the pattern register 72. Now, the combined bit pattern of the first and second window is applied to the conversion table 73 as a single address, as indicated in the entry n-1, and a Pattern Save signal is produced on the line 77 again. In response to the Pattern Save signal, the pattern register 72 stores the bit pattern of the third window along with the first and second bit patterns. The combined bit pattern is supplied to the conversion table 73, which generates the Pattern Save signal on the line 77, as shown in the entry n of Table 3. Then, the pattern register 72 stores the bit pattern of the fourth window also, and the combined bit pattern of the first through fourth windows is applied to the conversion table 73, as indicated in the entry 7 of Table 3, which produces the bit pattern corresponding to that of FIG. 3B on the output line 74. Thus, the output bit pattern stored in the 3-line buffer 76 through the gate 75 represents the bit pattern of FIG. 3B.

The bit pattern in the 3-line buffer 76, which has been pre-processed in accordance with the present invention, is supplied to the conventional compression device 78, in FIG. 7, which compresses the bit pattern from the 3-line buffer 76 in accordance with the two-dimensional coding scheme of the CCITT Recommendation T.4, for example.

Description of a Second Embodiment

The FIGS. 8 through 10 show a second embodiment of the present invention. In this embodiment, the 2 pel x 4 pel window 81 shown in FIG. 8 samples or picks up each array of 2 x 4 image bits in the document image 82. The start position of the 2 x 4 pel window is at the upper left comer of the document image 82, i.e. pels L₁C₁- L₁C₄ and L₂C₁ - L₂C₄. The 2 ^{x 4 pel} window 81 progressively moves or shifts towards the right-most pel position C_n.

When the 2 x 4 window 81 after having started from the upper left-most pel positions, i.e. the said L₁C₁- L₁C₄ and L₂C₁- L₂C₄, reaches the right edge of the scan lines L₁ and L₂, the 2 x 4 window 81 returns to the next start position L₂C₁- L₂C₄and L₃C₁- L₃C₄, and scans this next couple of scan lines L₂ and L₃. As the 2 x 4 pel window 81 scans the document image 82, the pel conversion shown in FIG. 9 is performed. One example of the conversion is shown in FIGS. 8 and 10. Figure 10(A) shows a first step in which the bi-level image data of scan lines L₁ and L₂ are fetched into an input buffer, not shown. Then, the 2 x 4 pel window is sequentially moved from the first pel C₁ to the last pel C_n. During each shift of the sequential movement, 8 pels within the 2 x 4 pel window 81 are inspected as to whether the 8 pels match with one of the patterns 1 through 4 of FIG. 9. If Yes, the 8 pels are replaced by one of the patterns 11 through 14. If No, the conversion or replacement is not made, that is, the original pels are not changed. The fetch of the 2 x 4 pels and the comparison of the 2 x 4 pels with the patterns 1-4 in FIG. 9 could be performed by a similar circuit arrangement as the pattern register 72 and the conversion table means 73 in FIG. 7.

A match to the pattern 1 is found for the ^pels L₁C₃ - L₁C₆ and L₂C₃ L₂C₆, and these eight pels are replaced by the pattern 11. This replaced pattern 11 is shown by the solid line 101 in FIG. 10(B). The next match is found at ^pels L₁C₉- L₁C₁₂ and L₂C₉- L₂C₁₂, since these eight pels match with the pattern 3 in FIG. 9. Thus, the eight pels are replaced by the pattern 13 in FIG. 9. This replacement is shown by solid line 102. Thereby, the pre-process of the scan lines L_I and L₂ has been completed, as shown in FIG. 10(B), and the first scan line L₁' is stored in the first line L₁' of an output buffer, as shown in FIG. 10(E). In the next step, shown in FIG. 10(C), the second line L2' of FIG. 10(B) and the third scan line L₃ of the original image data of FIG. 8 are combined and loaded into the input buffer. The 2 x 4 pel window moves again from the left end C₁ to the last pel on the right C . When the 2×4 pel window 81 reaches the eight ^pels L₂'C₉ - L₂'C₁₂ and L₃C₉ L₃C₁₂' these eight pels match with the pattern 4 of FIG. 9, and therefore these eight pels are replaced by the pattern 14 of FIG. 9. This conversion is shown by solid line 103 in FIG. 10(D). Thereby, the pre-process of the scan lines L₂' and L₃ in FIG. 10(C) has been completed, and the scan line L₂" of FIG. 10(D) is stored in the scan line L₂" of the output buffer as shown in FIG. 10(E).

The next step loads the scan line L₃' of FIG. 10(D) and the scan line L₄ of FIG. 8 into the input buffer.

Again, the 2 x 8 pel group is sequentially shifted and compared with the patterns 1 through 4, and if a match is found, the eight pel group is replaced by one of the patterns 11 through 14, and the resulting scan line L₃" is stored into the output buffer, as shown in FIG. 10(E).

The bit pattern in the output buffer is supplied to the compression device which compresses the bit pattern of the output buffer, in accordance with the two-dimensional coding scheme of the CCITT Recommendation T.4, for example.

In the preceding specification, the pre-process in the horizontal direction was described. But, the pre-process in accordance with the present invention could be used just as well to pre-process bi-level image data in the vertical direction. In the pre-process operation in the vertical direction, a changing element in each column in the vertical direction is detected, and the step is performed which determines whether a distance between the changing element in a first column and a changing element in a second column is falling within a predetermined range. Further, similar operational steps as the steps in the described embodiments are performed to pre-process the bi-level image data in the vertical direction.

The embodiments were directed to pre-process the black pels in the data. But, the invention could also be used to pre-process image patterns which are reversed patterns of the patterns shown in FIGS. 4A, 4C, 5A, 5C, 6A, 6C and the patterns 1-4 in FIG. 9. In this case, the white pels are treated as the foreground pels and the black pels are treated as background pels.

It has been described that the invention provides for pre-processing of image data, which improves the efficiency of subsequent data compression. In other words, the invention reduces the data amount of the compressed data.