Multiple output switching power supply.
Abstract
A compact multiple output switching power supply having a series connection of a D.C. input power supply (E), a switching device (0) and a primary winding (np) of a transformer (T1) which supplies currents to loads during an on period of the switching device, and supplies constant output voltages Vi (i = 1, 2, ..., m) from m (m ≧ 2) secondary windings ni (i = 1, 2, ..., m) of the transformer by turning on and off the switching device, includes means (T2) for storing a magnetic energy during the on period of the switching device and discharging the stored energy to the loads during on off period, connected in series with the primary winding of the transformer. The output voltage V, (j = 2, 3, ..., m) is represented by where kj is a voltage drop in the circuit.

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6 claims: 1 independent, 5 dependent
- 1A multiple output switching power supply including a series connection of a D.C. input power supply (E), a switching device (Q) and a primary winding (n ) of a transformer (T 1 ) for supplying currents to loads during an on period of said switching device, so that m constant output voltages V i (i = 1, 2, ..., m, m ≧ 2) are supplied to said loads from m secondary windings n i of said transformer by on-off switching of said switching device;characterized by that means (T 2 ) for storing a magnetic energy during the on period of said switching device and discharging the stored energy to the loads during an off period is connected in series with the primary winding of said transformer, and the output voltage V j (j = 2, 3, ..., m) is represented by where k . is a voltage drop in the circuit.
- 2A multiple output switching power supply according to Claim 1 wherein said means for storing the magnetic energy during the on period of said switching device and discharging the stored energy to the loads during the off period is a transformer (T 2 ) having a primary winding thereof connected in series with the primary winding of said transformer (T l ) and having m secondary windings n Si (i = 1, 2, ..., m), said output voltage V j is represented by n Sj in the same manner as said formula, said secondary winding n i and said secondary winding n Si are connected in parallel to each other through a diode (D 1 , D 2 ), and a capacitor (C 1 , C 2 ) is connected thereacross to supply voltages to the loads.
- 3A multiple output switching power supply according to Claim 2 wherein said output voltage V . is a sum of the voltage represented by said formula and V 1 .
- 4A multiple output switching power supply according to Claim 3 wherein said switching device is controlled to keep the output voltage V 1 constant.
- 5A multiple output"switching power supply according to Claim 1 wherein said output voltage V . is a sum of the voltage represented by said formula and V 1 .
- 6A multiple output switching power supply according to Claim 5 wherein said switching device is controlled to keep the output voltage V 1 constant.
Independent claims6
47 paragraphs in 4 sections, as filed
BACKGROUND OF THE INVENTION
0001The present invention relates to a multiple output switching power supply, and more particularly to a current type multiple output switching power supply suitable to supply a power to an OA or FA equipment which requires a high precision of output voltage.
0002A current type switching power supply is disclosed in Japanese Unexamined Patent Publication No. 55-120369 which discloses that a recovery current of a flywheel diode inserted in a secondary circuit of a transformer does not flow into a switching device in a primary circuit of the transformer and flow of an excessive current in an input circuit is suppressed even if the transformer is saturated by a surge voltage from the input circuit. However, it does not recognize a problem encountered in the multiple output switching power supply.
0003Japanese Unexamined Patent Publication No. 55-144775 discloses a technique to operate a switching device to stabilize one of the outputs so that the multiple outputs are stabilized. In the disclosed technique, a choke coil inserted in a secondary circuit of a transformer has a plurality of magnetically coupled windings. In the disclosed technique, it is not possible to determine the output voltages by turn ratios of a plurality of secondary windings wound on a transformer but turn ratios of the windings wound on the choke coil should also be taken into consideration. As a result, the more the number of outputs is, the more difficult to design the power supply. Further, since one output is stabilized by the operation of the switching device, variations of other output voltages due to a variation of the one output voltage, that is, voltage variations due to so called cross-regulation increase. Causes of the cross-regulation are leakage inductances and winding resistances of the transformer. In the disclosed technique, the leakage inductances and the winding resistances which cause the cross-regulation during an on period of the switching device affect to the transformer as well as leakage inductances and resistances of the windings of the choke coil and make it difficult to precisely control all of the output voltages.
0004In a technique disclosed in Japanese Unexamined Patent Publication No. 56-19119, an inductor is connected to an A.C. input. As a result, a ripple of a current flowing through the inductor is large, a current capacity of a rectifying/filtering circuit in a secondary circuit of a transformer is large and a maximum current flowing through a leakage inductor and a resistor of the transformer is large. As a result, outputs are affected by voltage drops thereacross and precision of the output voltages is lowered.
SUMMARY OF THE INVENTION
0005It is an object of the present invention to provide a multiple output switching power supply which is easy to design, suppresses variations of the output voltages due to a cross-regulation and can supply the multiple output voltages to loads with a high precision.
0006In the present invention, it was noticed that the prior art multiple output switching power supply having a plurality of windings in a choke coil inserted in a secondary circuit of a transformer increases the cross-regulation by a combination of leakage inductances and winding resistances of both the transformer and the choke coil, and the choke coil is inserted in a primary circuit of the transformer in order to suppress an influence by the choke coil. In the present arrangement, therefore, the leakage inductances and the winding resistances of the transformer and the choke coil which cause the cross-regulation are not combined and hence the precise output voltages are produced. Since the choke coil is inserted in the primary circuit of the transformer, the voltages developed across the windings of the transformer during an on period of the switching device are substantially equal to the respective output voltages, and the voltages induced across the windings of the choke coil during an off period of the switching device are also substantially equal to the respective output voltages. Accordingly, the respective output voltages are determined by the turn ratios of the secondary windings of the transformer and the choke coil and the design of the multiple output switching power supply is simplified.
BRIEF DESCRIPTION OF THE DRAWINGS
0007<ul id="ul0001" list-style="none"><li>Fig. 1 shows one embodiment of the present invention.</li><li>Fig. 2 is an equivalent circuit of the present invention during an on period of a transistor Q.</li><li>Fig. 3 shows a circuit configuration of a prior art multiple output siwtching power supply having a plurality of windings on a choke coil.</li><li>Fig. 4 is an equivalent circuit of Fig. 3.</li><li>Fig. 5 shows energy discharge means of Fig. 1.</li><li>Fig. 6 is an equivalent circuit during an off period of the transistor Q, for illustrating an operation of the energy discharge circuit.</li><li>Figs. 7 to 9 show other embodiments of the present invention.</li></ul>
DESCRIPTION OF THE PREFERRED EMBODIMENTS
0008One embodiment of the present invention is explained with reference to Fig. 1. E denotes a D.C. input power supply. A current I<sub>c </sub>flows, during an on period of a transistor Q which is a switching device, from a positive terminal of E through a reactor T<sub>2</sub> which stores a magnetic energy, a primary winding n<sub>p</sub> of a transformer T<sub>1</sub> to a negative terminal of E. Thus, voltages are developed across the primary winding n<sub>p</sub> and secondary windings n<sub>1</sub> and n<sub>2</sub> of the transformer T<sub>1 </sub>with doted ends being positive, and currents are supplied to loads from n<sub>1</sub> and n<sub>2</sub> through- diodes D1 and D<sub>2</sub>, respectively. A capacitor C<sub>1</sub> smoothens the voltage supplied to the load connected to an output terminal 1 and it is charged with a voltage V<sub>l</sub>. A capacitor C<sub>2 </sub>also functions in a similar manner to C<sub>1</sub> and it is charged with a voltage V<sub>2</sub> which is supplied to the load connected to an output terminal 2. Numeral 10 denotes means which discharges, during an off period of the transistor Q, the magnetic energy stored in the reactor T<sub>2</sub> during the on period of the transistor Q.
0009The operation of the present embodiment is explained with reference to Fig. 2 which shows an equivalent circuit during the on period of the transistor Q. L<sub>2</sub> denotes an inductance of the reactor T<sub>2</sub>, Z<sub>1</sub> denotes an impedance including a leakage inductance, a winding resistance and a circuit resistance of the winding n<sub>l</sub>, and Z<sub>2</sub> denotes an impednace including a leakage inductance, a winding resistance and a circuit resistance of the winding n<sub>2</sub>. The current flowing through the inductance L<sub>2</sub> shunts to the output terminals 1 and 2 with currents I<sub>1</sub> and I<sub>2</sub>, respectively. The currents I<sub>1</sub> and I<sub>2</sub> meet the following relationship.<maths id="math0001" num=""><img file="EP0176783A2_D0001.tif" /></maths> where V<sub>Dl</sub> and V<sub>D2</sub> are voltage drops across the diodes D<sub>1</sub> and D<sub>2</sub>, respectively. From the formula (1), the volage V<sub>2</sub> at the output terminal 2 is expressed by<maths id="math0002" num=""><img file="EP0176783A2_D0002.tif" /></maths>From the formula (2), it is seen that the voltage V<sub>2</sub> is represented by the voltage V<sub>1</sub> at the output terminal 1 and the circuit impedance.
0010Reffering to Fig. 1, the voltages induced across the windings of the transformer T<sub>1</sub> during the on period of the transistor Q is considered. The voltage induced across the winding n<sub>1 </sub>with the dotted end being positive is equal to V<sub>1</sub> + V<sub>D1</sub>, as seen from Fig. 1. Because of the voltage drop I<sub>1</sub> Z<sub>1</sub>due to the winding resistance and the circuit resistance of the transformer, the voltage V<sub>p</sub> shown by the following formula must be developed across the primary winding np of T<sub>1</sub> with the dotted end being positive.<maths id="math0003" num=""><img file="EP0176783A2_D0003.tif" /></maths>
0011If Vp is given, a voltage V<sub>n2</sub> induced across the winding n<sub>2</sub> with the dotted end being positive is expressed by
0012<maths id="math0004" num=""><img file="EP0176783A2_D0004.tif" /></maths>From the formula (4), the voltage V<sub>2</sub> at the output terminal 2 is expressed by<maths id="math0005" num=""><img file="EP0176783A2_D0005.tif" /></maths>
0013The voltage drop I<sub>1</sub>·Z<sub>1</sub>, + V<sub>D1</sub> at the output terminal 1 is given by k<sub>1</sub> and the voltage drop I<sub>2</sub>·Z<sub>2</sub> + V<sub>D2</sub> at the output terminal 2 is given by k<sub>2</sub>. Thus, from the formula (5), the voltage V<sub>2</sub> is expressed by<maths id="math0006" num=""><img file="EP0176783A2_D0006.tif" /></maths>
0014From the above, it is seen that the voltage V<sub>2</sub> at the output terminal 2 is defined by the turn ratio of the secondary windings n<sub>1</sub> and n<sub>2</sub> of the transformer T<sub>l</sub>, and the function of the voltage V<sub>1</sub> at the output terminal 1 and the voltage drops in the circuit. Since k<sub>1</sub> and k<sub>2</sub> are generally smaller than V<sub>1</sub>, V<sub>2</sub> can be expressed as follows without a large error.<maths id="math0007" num=""><img file="EP0176783A2_D0007.tif" /></maths>
0015Thus, the turn ratios of the transformer T<sub>1</sub> can be substantially determined by the ratios of the output voltages and the circuit design is facilitated.
0016In the above embodiment, the multiple output switching power supply having two outputs was shown. When m outputs are included, the operation is similar and the output voltage V. (j = 2, ..., m) is expressed by<maths id="math0008" num=""><img file="EP0176783A2_D0008.tif" /></maths>
0017Accordingly, the design of the multiple output switching power supply is facilitated.
0018The embodiment of the present invention shown in Fig. 1 is compared with a prior art power supply having a plurality of magnetically coupled windings on a choke coil inserted in a secondary circuit of a transformer. Fig. 3 shows a configuration of the prior art power supply. T denotes a transformer, E denotes a D.C. input power supply, <sub>L</sub> denotes a choke coil having magnetically coupled windings n<sub>L1</sub> and nL2, and V<sub>I</sub> and V<sub>2</sub> denote voltages at output terminals 1 and 2, respectively. Voltages are induced, during an on period of the transistor Q, across the windings of the transformer T and the choke coils L, with dotted ends being positive.
0019From Fig. 3, it is seen that the following relationships must be met during the on period of the transistor Q.<maths id="math0009" num=""><img file="EP0176783A2_D0009.tif" /></maths><maths id="math0010" num=""><img file="EP0176783A2_D0010.tif" /></maths> where <sup>V</sup><sub>nLl</sub> and V<sub>nL2</sub> are voltages induced across the windings n<sub>Ll</sub> and n<sub>L2</sub> of the choke coil L, respectively. In the formulas (9) and (10), the affects by the leakage inductances and winding resistances of the transformer T and the choke coil L, and diode voltage drops are omitted for the purpose of simplification.
0020The voltage <sub>VnL2</sub> of the formula (10) is expressed as follows.<maths id="math0011" num=""><img file="EP0176783A2_D0011.tif" /></maths>
0021From the formulas (9), (10) and (11),<maths id="math0012" num=""><img file="EP0176783A2_D0012.tif" /></maths>
0022From the formula (12), the voltage V<sub>2</sub> at the output terminal 2 is expressed by
0023<maths id="math0013" num=""><img file="EP0176783A2_D0013.tif" /></maths>Since the impednaces of the transformer T and the choke coil and the diode voltage drops are omitted in the formula (13) as described above, the formula (13) corresponds to the formula (7) which represents the voltage V<sub>2</sub> in the embodiment of Fig. 1. As seen from the comparison of the formulas (7) and (13), the output voltage V<sub>2</sub> of the embodiment of Fig. 1 is essentially determined by the turn ratio of the secondary windings n<sub>1</sub> and n<sub>2</sub> of the transformer T<sub>1</sub> while the voltage V<sub>2</sub> in the prior art of Fig. 3 cannot be defined without taking the voltage V<sub>Ll</sub> induced across the winding of the choke coil and the turn ratio of the choke coil L into consideration, and hence proper design of the power supply is difficult to attain.
0024Referring to an equivalent circuit shown in Fig. 4, the operation of the prior art power supply of Fig. 3 is explained in detail. Fig. 4 shows the equivalent circuit during the on period of the transistor Q. E denotes the D.C. input power supply, I<sub>1</sub> and I<sub>2</sub> denote the currents supplied to loads connected to output terminals 1 and 2, respectively, Z<sub>1</sub> and Z<sub>2</sub> denote the impedances including the leakage inductances, winding resistances and circuit resistances of the transformer T, and Z<sub>L1</sub> and Z<sub>L2</sub> denote the impedances including the leakage inductances, winding resistances and winding resistances of the windings N<sub>L1</sub> and n<sub>L2</sub> of the choke coil L. As seen from Fig. 4, the currents I<sub>1</sub> and I<sub>2</sub> flowing through the output terminals 1 and 2 meet the following relationship.<maths id="math0014" num=""><img file="EP0176783A2_D0014.tif" /></maths>
0025From the formula (14), the voltage V<sub>2</sub> at the output terminal 2 is expressed by
0026<maths id="math0015" num=""><img file="EP0176783A2_D0015.tif" /></maths>From the formula (15), it is seen that when the output currents I<sub>1</sub> and I<sub>2</sub> change, voltage variations which are proportional to (Z <sub>1 </sub>+ Z<sub>Z1</sub>) and (Z<sub>2 </sub>+ ZL2), respectively, take place in <sup>V</sup><sub>2</sub>.
0027On the other hand, in the present embodiment, it is seen from the formula (2) that the variation of V<sub>2</sub> when <sub>I1</sub> and <sub>I2</sub> change is proportional to Z<sub>1</sub> and Z<sub>2'</sub> As a result, the voltage variation due to the change of the load current is smaller in the embodiment of Fig. 1 and the precision of the output is higher.
0028As described above, the embodiment of Fig. 1 and the prior art of Fig. 3 are different from each other in their concepts and effects.
0029Fig. 5 shows a circuit configuration of the energy discharge means 10 shown in Fig. 1. The energy discharge means 10 comprises windings n<sub>S1</sub> and n<sub>S2</sub> magnetically coupled to the primary winding n<sub>S</sub> of the reactor T<sub>2</sub> and diodes D<sub>3</sub> and D<sub>4</sub> connected to ends of the windings n<sub>S1</sub> and n<sub>S2</sub>, respectively. The winding n<sub>sl</sub> is connected through the diode D<sub>3</sub> in parallel to the secondary winding n<sub>1</sub> of the transformer T<sub>1</sub> and the winding n<sub>s2</sub> is connected through the diode D<sub>4</sub> in parallel to the winding n<sub>2</sub>. During the on period of the transistor Q, voltages are induced across the windings of T<sub>2</sub> with the dotted ends being positive. Accordingly, the voltages induced across the windings n<sub>S1</sub> and n<sub>S2</sub> during the on period of the transistor Q are blocked by the diodes D<sub>3</sub> and D<sub>4</sub> and no current flows. The current flowing through the winding n<sub>S</sub> is an exciting current of T<sub>2</sub> and a magnetic energy is stored by the exciting current. When the transistor Q is turned off, the current flowing through the winding n<sub>S</sub> is cut off and voltages are developed across the windings of T<sub>2</sub> with the opposite ends to the dotted ends being positive, by the magnetic energy stored in T<sub>2</sub>. As a result, currents flow out of the windings n<sub>S1</sub> and n<sub>S2</sub> into the loads connected to the output terminals 1 and 2, respectively.
0030The operation of the energy discharge means is explained in detail with reference to an equivalent circuit of Fig. 6 during the off period of the transistor Q. L<sub>2</sub> denote an inductance of the reactor T<sub>2</sub>, and Z<sub>1</sub>' and Z<sub>2</sub>' denote impedances including the leakage inductances, winding resistances and circuit resistances of the windings n<sub>sl</sub> and n<sub>S2</sub>, respectively. As seen from the equivalent circuit, the voltage V<sub>2</sub> at the output terminal 2 is expressed by
0031<maths id="math0016" num=""><img file="EP0176783A2_D0016.tif" /></maths>The voltages induced across the windings of T<sub>2</sub> during the off period of the transistor Q is expressed by the formula (4) as seen from Fig. 5, and the voltage V<sub>ns2</sub> across the winding n<sub>s2</sub> is expressed by<maths id="math0017" num=""><img file="EP0176783A2_D0017.tif" /></maths>
0032From the equation (17), the voltage V<sub>2</sub> at the output terminal 2 is expressed by<maths id="math0018" num=""><img file="EP0176783A2_D0018.tif" /></maths>
0033In the formulas (16) - (18), V<sub>D3</sub> and V<sub>D4</sub> are voltage drops across the respective diodes D<sub>3</sub> and D<sub>4'</sub>
0034The voltage drop I<sub>1</sub>·Z<sub>2</sub>' + V<sub>D3</sub> at the output terminal 1 is expressed by k<sub>l</sub>, and the voltage drop I<sub>2</sub>·Z<sub>2</sub>' + V<sub>D4</sub> at the output terminal 2 is expressed by k<sub>2</sub>. Thus, from the formula (18), V<sub>2</sub> is expressed by
0035<maths id="math0019" num=""><img file="EP0176783A2_D0019.tif" /></maths>It is seen from the above that the voltage V<sub>2</sub> at the output terminal 2 during the off period of the transistor Q is defined by a function similar to that shown in the formula (6) .
0036The same is applicable to the multiple output switching power supply having m outputs. The output voltage <sup>V</sup>. (j = <sup>2,</sup> 3, ..., m) is expressed by
0037<maths id="math0020" num=""><img file="EP0176783A2_D0020.tif" /></maths>Accordingly, the output voltage V. is essentially defined by the turn ratio of the secondary windings n<sub>1</sub> and n<sub>j </sub>of the reactor T<sub>2 </sub>as is done for the transformer T<sub>1</sub> and the design of the power supply is facilitated. Further, in the present embodiment, since the magnetic energy stored in the reactor T<sub>2</sub> is supplied to the loads by the energy discharge means 10, the efficiency of the multiple output switching power supply is improved.
0038Fig. 7 shows another embodiment. In the present embodiment, a voltage V<sub>1</sub> at an output terminal 2 is a sum of a voltage V<sub>1 </sub>developed across a winding n<sub>1</sub> and a voltage developed across a winding n<sub>2</sub>. Windings n<sub>S1</sub> and n<sub>s2</sub> are similarly configured to develop a voltage V<sub>2</sub> at an output terminal 2.
0039In the embodiment of Fig. 1, the turn ratio of the windings n<sub>1</sub> and n<sub>2</sub> is essentially same as the ratio of the output voltages V<sub>1</sub> and V<sub>2</sub>, as shown in the formula (7). The same is true for the turn ratio of the windings n<sub>S1</sub> and n<sub>s2</sub>. On the other hand, it is seen from the formulas (5) and (8) that the smaller the ratios n<sub>2</sub>/n<sub>l</sub> and n<sub>s2</sub>/n<sub>sl</sub> are, more the variation of the voltage V<sub>2</sub> due to the change of the output current I<sub>1 </sub>is suppressed. Thus, in the present embodiment, the numbers of turns of the windings n<sub>2</sub> and n<sub>s2</sub> are reduced to suppress the variation of the voltage V<sub>2</sub> and improve the output precision.
0040In the circuit configuration of Fig. 7, the numbers of turns of the windings n<sub>2</sub> and n<sub>s2</sub> are selected such that the voltage V<sub>2</sub> at the output terminal 2 is a sum of the voltage V<sub>1</sub> at the output terminal 1 and the voltages developed across the windings n<sub>2</sub> and n<sub>s2</sub>. Thus, the turn ratios of the windings n<sub>2</sub> and n<sub>s2</sub> are selected as follows.<maths id="math0021" num=""><img file="EP0176783A2_D0021.tif" /></maths><maths id="math0022" num=""><img file="EP0176783A2_D0022.tif" /></maths>
0041Accordingly, the turn ratios n<sub>2</sub>/n<sub>l</sub> and nS<sub>2</sub>/n<sub>S1</sub> are smaller than those of the embodiment of Fig. 1, and hence the variation of the voltage V<sub>2</sub> at the output terminal 2 is suppressed and the precision of the output is improved.
0042Fig. 8 shows another embodiment. In the present embodiment, a control circuit 11 is provided to control the switching of the transistor Q to keep the voltage V<sub>1</sub> at the output terminal 1 constant. It is seen from the formulas (6) and (19) that if the voltage V<sub>1</sub> at the output terminal 1 is constant, the voltage at the output terminal 2 can be stabilized within a variation of a voltage drop across an impedance in the circuit.
0043In the present embodiment, since the voltage V<sub>1 </sub>at the output terminal 1 is kept constant, the voltage V<sub>2</sub> at the output terminal 2 need not take the change of V<sub>l</sub> into consideration as shown in the formulas (6) and (19), and the output precision of the voltage V<sub>2</sub> is further improved. Alternatively, the control circuit 11 of the present embodiment may be provided in the embodiment of Fig. 1 to control the switching of the transistor Q in order to keep the voltage V<sub>1</sub> of the output terminal 1 constant.
0044Fig. 9 shows another embodiment. In the present embodiment, m outputs are supplied to the loads in the embodiment of Fig. 8. By controlling the switching of the transistor Q by the control circuit 11 to keep the voltage V<sub>1</sub> at the output terminal 1 constant, m stable voltages can be supplied to the loads.
0045Alternatively, the control circuit 11 may be provided in the embodiment of Fig. 1 to control the switching of the transistor Q in order to keep the voltage V<sub>1 </sub>at the output terminal 1 constant, so that stable outputs are supplied from m secondary windings wound on the transfermer T<sub>1</sub> and the reactor T<sub>2'</sub>
0046The control circuit 11 shown in Figs. 8 and 9 may be Hitachi switching power supply control IC HA17524 or Texas Instruments TL 494. The configuration and operation of those IC's are well known and they are not explained here.
0047In accordance with the present invention, the output voltages of the multiple output switching power supply can be defined by the turn ratios of the secondary windings of the transformer and the windings of the energy discharge circuit of the reactor, and the design of the power supply is facilitated. When the control circuit is used to control the switching device such that one of the output voltages is kept constant, the voltage variations of other outputs can be less than ±5%. Thus, the multiple output switching power supply used for the OA and FA equipments are simplified and the size and cost thereof can be reduced.
Contents4
30 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| AU2008216994B2 | Cited by | Australia | Search report |
| EP2066014A1 | Cited by | European Patent Office (EPO) | Search report |
| AU2008216966B2 | Cited by | Australia | Search report |
| US3569818A | Cites | United States of America | Search report |
4 priority claims, no other members on record
Priority claims4
| Document | Office | Kind | Date |
|---|---|---|---|
| 18420484 | Japan | A | |
| 18420484 | Japan | – | |
| JP19840184204 | – | – | – |
| 18420484 | – | – | – |
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Numbers
- Publication
- 0176783
- Publication, DOCDB
- 0176783
- Publication, EPODOC
- EP0176783
- Application
- 85111029
- Application, DOCDB
- 85111029
- Application, EPODOC
- EP19850111029
Titles6
- German
- Schaltnetzteil mit mehreren Ausgängen.
- English
- Multiple output switching power supply.
- French
- Alimentation de puissance à commutation à plusieurs sorties.
- German
- Schaltnetzteil mit mehreren Ausgängen
- English
- Multiple output switching power supply
- French
- Alimentation de puissance à commutation à plusieurs sorties
Classification
- CPC, 2
- H02M3/33538
- H02M3/33561
- IPC, 2
- H02M3 28
- H02M3 335
Designated states2
- Contracting states, 2
- Germany
- France