Digital conference circuit.

0001The invention relates to a digital conference call according to the preamble of patent claim 1.

0002Digital conference calls for digital messaging systems are known. They work either according to the summation method (US Pat. No. 4,416,007 DD Huizinga et al) or according to the "loudest speaker" principle (US Pat. No. 3,699,264; SGPitroda et al).

0003The summation method requires a large number of adders and subtractors.

0004In the "loudest speaker" principle, a digital threshold detector is used to determine the loudest speaker in each case (US patent application 427,970; DBSchuh). The loudest speaker is connected to all other conference participants, while at the same time the loudest speaker's signal cannot reach him. The main difficulty is in operating the threshold detector. The conference circuit works satisfactorily when the background noise on all lines of the conference participants is low and the levels are the same. However, if the noise level of one or more lines rises, one line can "suppress" the other lines, especially if one of the lines is at a low level. In addition, the threshold detector can switch over and over again. Furthermore, the total number of conference calls possible at the same time is limited

0005The technical object according to the invention is to minimize or eliminate these disadvantages.

0006This object is achieved according to the technical teaching specified in claim 1.

0007Further advantageous developments of the subject matter of the invention can be found in the subclaims.

0008An exemplary embodiment of the present invention is described on the basis of a digital time multiple communication system which has 24 voice channels (North America and Japan standard).

0009This has a 125 µsec time frame with an 8 KHz sampling rate and a 1.544 mbit / s data rate. Each 125 µsec time frame contains 193 bits, 24 x 8-bit words each (one sample of each channel) and a 193-th bit a frame separating bit

0010Voice channel groups, each with 24 voice channels, are connected to an 8-bit PCM system bus SB with 193 time slots.

0011Each group frame consists of the original 2₄ times 8-bit signals, each occupying an 8-bit time slot of the PCM system bus SB

0012As shown in the single figure, conference participants assigned PCM time slots, which arrive via a 193 by 8 bit PCM system bus SB, are stored in a 193 by 8 bit time slot buffer M2 with random access - also called RAM M2 in the following - during a time frame. At the same time, the resulting conference information, which comes from the time frame of the two time frames before the now arriving time frame, is read from RAM M2 into the outgoing PCM time slots. The incoming channels are accumulated during one time frame and processed during the next time frame so that the result is shown again on the PCM system bus SB in the following time frame.

0013The time slot buffer M2 is implemented in the form of two buffers M2A, M2B with random access in order to show and hide information frames and to store processed information for alternating time frames in an interleaved manner in order to generate a continuous "frame to frame" signal. / Fade out mode, RAM M2 is connected to a channel counter CC, as a result of which the time slot position occurs half a time slot period earlier. This is necessary due to the use of conference time signals TS, since these are shifted by a fraction of a time slot period compared to a time slot. Thus, information corresponding to the addresses assigned to the RAM M2 can be faded in or out in its correct position either in or out of a time slot.

0014The conference time signals TS are generated in a timer unit T, which is clocked with a system clock CL.

0015The system clock CL is also routed to the channel counter CC.

0016A channel index memory Mi - hereinafter also referred to as RAM M1 - which is controlled, for example, by a microprocessor, determines whether it is an incoming or an outgoing time slot in which, for example, a control bit of the output signal from RAM M1 is monitored (for example bit 17 and bit 18 of a 20-bit output signal). The channel index memory M₁ contains an output memory. Furthermore, the time slot latches M2A and M2B are addressed either by the channel index memory M1 or the channel counter CC via switches XOA and XOB.

0017During a conference call, the PCM conference signals of the participants involved are processed, ie digitally added, in order to obtain a composite signal which is sent to all participants. However, the composite signal does not contain a portion of the subscriber's signal to which it is being sent, thereby eliminating back-listening.

0018The number of additions required for a conference call corresponds to the number of subscriber lines in the conference call. The number of internal conference time slots per addition corresponds to the number of subscriber lines. The total number of conference time slots required thus results from the square of the number of subscriber lines on the conference circuit.

0019The available number of conferences and the number of subscriber lines per conference is only limited by the number N of internal PCM conference time slots. The length of the internal time frame of the PCM conference time slots corresponds to the length of the time frame of the PCM system bus SB. The total number of possible multiple conversations (conferences) at the same time is determined by the number of time slots per multiple conversation that have to be inserted into the N available time slots. However, these internal time slots do not determine the capacity of the PCM system bus SB.

0020If the number of internal time slots is adapted to the number of time slots of the PCM system bus SB, for example 192 time slots and a frame separating time slot, the maximum number of conferences is as follows

0021<tables id="tabl0001" num="0001"><img file="EP0175147A2_D0001.tif" /></tables>

0022A variety of combinations are possible. For example, a twelve-party conference, a five-party conference and two three-party conferences at the same time.

0023The conversion of the conference signals into and out of a linear form takes place by means of two conversion memories. For this purpose, the information provided by each conference participant line according to the "p-law" standard (ie the signals are in accordance with a natural logarithm function in (x) compressed) working CODEC's incoming 8-bit PCM signals initially from an 8-bit "µ-law" PCM signal, which consists of a 7-bit value and a sign bit converted a linear 12-bit two's complement signal. This conversion takes place in a programmable 256 x 12-bit read-only memory (PROM) M3, by means of a stored converter table.

0024The linear PCM signal is now by a 16-bit adder A to the result of the previous addition, which is in an indexed 64th ^X 16 bit partial sum accumulator memories M4 are stored, added. Since the result contains the value and the sign, addition or subtraction by the adder A can be carried out by simple two's complement calculation. Of the₁6-bit adder A is used to obtain the necessary resolution for the linear 12-bit two's complement representation. The additional bits are used to indicate a positive or negative overflow. The index corresponds to the subscriber line for which an addition is carried out. The capacity of the RAM M4 is limited to 64, since no more than 63 lines can be involved in conferences at the same time (this corresponds to the case: 21 three-way conferences).

0025The addition result of the 16-bit adder A is stored in RAM M₄ stored as a subtotal and simultaneously from 12-bit linear to 8-bit "µ-law", corresponding to one in a 4 kbit ^X 8-bit read-only memory M5 stored converter table, converted. The output signal of the read-only memory M5 is passed through an overflow correction unit OFC, which prevents distortion of cyclically composed signals of large amplitude (high volume).

0026As already said, a negative or positive overflow is indicated by additional bits of the adder A. If, for example, combination options 00 and 11 correspond to the normal conditions of the 14th and 13th bits for positive and negative values, a positive and negative overflow is detected if these bits have the values ​​0₁ or accept 10.

0027If an overflow condition occurs, a maximum value corresponding to the "µ-law" code, with the corresponding sign bit, is used by the overflow correction unit OFC instead of the overflow value for conversion. The overcorrection unit OFC thus avoids excessive distortions if the addition range is exceeded during the summation of many simultaneously occurring high signal amplitudes.

0028The output signal of the overflow correction unit OFC is stored in RAM M2 and fed to the correct time slot, with an overwrite for each addition.

0029The workflow for each conference, which requires an internal conference time slot for the workflow, is described below:<ul id="ul0001" list-style="none"><li>a) An addressed memory location in partial accumulator memory M4 is provided for each line participating in the conference and set to the value zero. This is because the latches L3 and L₄ be set to the value zero so that the value zero is added to each memory location. There are two bits of the output signal of the channel index memory M1, for example bit 19 and bit 20, for resetting the signal memories L3, L.₄ used;</li><li>b) each memory location assigned by an address to a subscriber line now selects all the subscriber lines, with the exception of the own subscriber line, in order to cyclically add and store each subscriber signal to its respective value, the content of the memory locations being renewed with each addition. At the same time, the resulting “μ-law” value is stored in the memory locations of the time slot buffer M2 correspondingly assigned to the subscriber lines.</li></ul>

0030After the procedure described above has been carried out for each memory location at the end of a time frame, the RAM M3 contains the resulting signal coded in "muG-law" for each subscriber, indexed by the channel index memory M1. The resulting signals are inserted into the correct time slots on the PCM system bus SB via the channel index memory M1 during the next time frame.

0031Switches X2A and X2B allow the time slot buffers M2A and M2B to read out unprocessed conference signals from the PCM system bus SB or to receive processed conference signals from the conference circuit.

0032A switch X3 allows reading from RAM M2A or RAM M2B for conference calls.

0033A time frame unit F generates a frame end signal EOF which is used to control the switches XOA, XOB, X2A and X2B and X3 so that signal processing and fading in and fading out of the signals take place simultaneously

0034Further switches X4A and X4B enable the resulting conference signal coming from the time slot buffer stores M2A or M2B to be controlled displayed on the PCM signal bus SB.

0035These shaders X4A and X4B are controlled by a control bit CS of the output signal of the channel index memory M1, for example bit 18, and by the frame end signal EOF.

0036In order to make it easier to increase or decrease the number of subscriber lines during a conference call, the addresses and memory locations in the RAM M4 are assigned on the basis of a request beginning with time slot one and set to zero.

0037The additions are carried out within time slots which lie at the end of the internal conference time slot frame, so that the more participants are added, the faster the assignment of such time slots takes place.

0038The channel index memory M1 enables the assignment by controlling the addressing of the time slot buffer M2.

0039Thus, the size of the conferences can be changed at will and new conferences can be added or removed with different sizes without disturbing the other conferences.

0040A control unit P, for example a microprocessor, is used to control the time slots which are addressed by the channel index memory M1.

0041The control unit P is connected to a system control bus SCB and connected via a data bus DB to the channel index memory M1 and via an address bus AB to a switch X1.

0042The channel index memory M1 is addressed via the switch X1 either by the control unit P or by the channel counter CC. The switch X1 is controlled by the conference time signals TS.

0043Background noise is reduced during the addition of signals from the conference participants by the selection of modified “μ-law” to linear converter tables, which are stored as overlay areas in the read-only memory M3.

0044Various superimpositions in the low-level range of the "µ-law" curve reduce the addition effect of the background noise. Such different overlays are available for different sizes of conference. Thus, noise reduction actuators can be selected for each conference and dynamically adjusted according to the change in the number of participants.

0045Different overlays can be applied to read-only memory M3, one relating to the normal "µ-law" curve and others relating to low level noise reduction values ​​which also minimize the distortion of the resulting signal.

0046For example, if the capacity of the read-only memory M3 is 256 ^X 12 bits to 512 ^X Expanded by 12 bits, four 64-bit low level overlays can be used.

0047The selection is made via an overlay selection unit S, which is controlled by an overlay selection part of the output signal of the channel index memory M1.

0048In accordance with the signal supplied by the time slot buffer memory M2, the output signal of the overlay selection unit S gives the address of the selected overlay area in the read-only memory M3.

0049Two multiplier units MC1 and MC2 are used to adjust the level of low level signals. The levels on these "low level" lines can be increased or decreased by, for example, +12, +6, -6, or - 12DB by using level conversion units.

0050The signal level is individually controlled by control bits of the output signal of the channel index memory M1, as a result of which the amplification can be set as desired. As a result, the levels on line sets can be reduced in accordance with the levels of local exchanges in order to obtain more balanced levels for signals with different loop attenuation.

0051The multipliers MC1, MC2 are used to change the gain of selected individual parts of the conference signals and to change the overall gain of the selected resulting conference signals.

0052The entire arrangement can be modified in a simple manner for processing signals according to the "A-law" code, ie according to a logarithmic characteristic, in which the read-only memories M3, M5 receive corresponding converter tables according to the "A-law" code . Other language coding regulations can be introduced in a corresponding manner.

0053The conference capacity can be increased by increasing the number of internal conference time slots per time frame (eg by using the European time frame standard).

0054Furthermore, by doubling the time slots, here 384 time slotsⁱtze, a nineteen-party conference and two three-party conferences at the same time. The conference capacities can also be increased by other means of accumulation, which should enable all storage locations to be reset at the same time. This would free up those time slots that are used for zeroing.