Process to superpose two positive photoresist layers.

0001The present invention relates to a process for depositing a second positive photoresist layer on a first positive photoresist layer provided on an article, e.g. an electronic chip.

0002Such a process is already known, e.g.from the article "High resolution trilevel resi-st" by H. Namatsu e t al, Journal of Vacuum Science Technology , Vol. 21, No 2, July/August 1982, pp 672-676, published by the "American Institute of Physics".

0003While the superposition of two negative photoresist layers poses no problems, this is not the case with positive photoresist layers. However, such layers are preferred because they have a better photolythographic resolution. This is especially useful when the circuit density is relatively high.

0004In the above known process for depositing a positive resist layer over another positive resist layer, an intermediate layer is used to prevent the two layers from merging into each other. If no intermediate layer is used and if the first resist layer serves for planarizing the surface topography of the chip, the deposition of the second resist layer directly on top of the first one will destroy this planarization effect. Moreover, if the first resist layer is provided with a pattern the latter may be damaged by the deposition of the second resist layer. On the other hand, when portions of the chip are not protected by the first layer due to the latter being provided with a pattern,an intermediate layer, e.g. silicon oxide, coating the whole chip may affect these chip portions. Indeed, this intermediate layer of silicon oxide must be deposited at a low temperature to prevent damaging the first resist layer and will therefore be of poor quality and contain impurities. These impurities are then able to contaminate the chip in the above mentioned portions. Since the intermediate layer has not the same properties as a photoresist layer, a pattern on the second resist layer can only be transmitted to the first resist layer by means of extra processing steps. Furthermore, the first resist layer can only be removed after the intermediate layer. This requires also extra processing steps.

0005An object of the present invention is to provide a process which allows the superposition of two positive photolythographic resist layers without any intarmediate layer being required.

0006According to the invention, this object is achieved due to the fact that said process consists in hardening at least a portion of said first layer prior to depositing said second layer directly on said portion.

0007By hardening the first resist layer, the merging with the second resist layer is prevented. Moreover, a pattern on the second resist layer can be immediately transferred to the first resist layer and the latter can be removed together with the second resist layer without any extra processing step.

0008The invention also relates to a semiconductor device made in accordance with the above process.

0009The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein Figs. 1 to 4 show successive main steps of a part of a process for making a semiconductor device according to the invention, the constituent parts of this device being not drawn at scale.

0010This semiconductor device includes a P-channel and a N-channel MOS transistors represented at the left and right hand sides of the figures respectively.

0011The semiconductor device represented in Fig. 1 is obtained as follows. On a chip constituted by a P substrate 1, i.e. a slightly doped P substrate, a field silicon oxide layer 2 is grown. By means of a mask (not shown) and a classical photolythographic process this layer 2 is removed from the substrate 1 in the windows 3 and 4. Also by means of a photolythographic process, the window 4 is covered by a new mask (not shown) and a thin layer. of a slightly doped N material (phosphorus) is implanted under the unprotected portion of the substrate 1 in window 3. To be noted that during this implantation operation also the unprotected parts of the field silicon oxide layer 2 are used as a mask to ensure that the N material is only implanted under the substrate surface in the window 3 and in the whole surface of this window. After the mask has been removed, the thin layer of N material is driven in the substrate 1 by a diffusion drive-in operation so that a slightly doped so-called N well 5 which extends laterally under the field oxide layer 2 surrounding the window 3 is obtained. A gate silicon oxide 6 is then grown on the upper surface of the substrate 1 especially in the windows 3 and 4. After this operation, a negatively doped (N⁺) layer of polysilicon material 7 is deposited on top of the oxide layers 2 and 6. Finally, by a photolythographic process, so-called gate masks 8 and 9 made of a positive photoresist material are formed on the gate portions 20 and 21 (Fig. 2) of the layer 7 to protect these gate portions during a subsequent etching operation by which the unprotected other portions of the polysilicon layer 7 are removed, as represented in Fig. 2.

0012All the abovasteps of the process will not be described more in detail since they are known from the art and are of less importance for the present invention.

0013The etching operation of the polysilicon layer 7 makes use of a f-uorine containing plasma (not shown) as a consequence of which a fluorine containing coating is formed on the masks 8 and 9. The thus coated gate masks 8 and 9 are then hardened by baking the chip at a temperature of 200 degrees centigrade during 30 minutes. The fluorine containing coating is then removed from the chip since a resist layer used in a subsequent operation cannot adhere to it. The removal of the coating is performed by a so-called flash-strip operation wherein the chip is brought in a 150 Watt oxygen containing plasma during 2 minutes. The flash-strip operation also protects the chip against wetting. Finally, the portions of the gate silicon oxide layer 6 which are not protected by the gate masks 8 and 9 are removed.

0014Reference is now made to Fig. 3 where a P positive photoresist mask 10 is formed on the gate mask 9. The mask 10 is obtained by a classical process which consists of depositing a positive photoresist material on the whole chip and by removing the unwanted portions by means of a photoly- tographic mask. Because of its hardening, the underlying positive photoresist mask 8 is not removed by the above mentioned operations.

0015An ion implantation schematically indicated by the arrows pointing to the windows 11 and 12 is then performed. It produces thin layers of P material under the upper surface of the substrate 1 in these windows. To be noted that during this implantation operation also the field silicon oxide layer 2 is used as a mask to ensure that P material is only implanted under the substrate surface in the windows 11 and 12 and in the whole surface of these windows. This is the reason why the mask 10 should not extend in the lateral direction beyond the layer 2.

0016The photoresist mask 8 and the second photoresist mask 10 are used together to realize the self-alignment and to protect the gate portion 20 against an ion bombardment. Indeed, as it appears clearly from Figs. 2 and 3 the gate mask 8 used for the etching operations of the polysilicon layer 20 and of the gate silicon oxide layer 6 is also used for the P ions implantation so that all these operations are performed in a so-called self-aligned way and in accurately the same windows 11 and 12. Furthermore, the hardened mask 8 provides a better protection of the N polysilicon layer 20 against the P ions (boron) during the implantation operation.

0017The P material implanted in the windows 11 and 12 is then driven in the N well 5 by a diffusion drive-in operation similar to the one described above. As a result, there are obtained two P regions 13 and 14 which extend laterally under both the field 2 and the gate 6 oxide layers. These two regions 13 and 14 constitute the drain and source electrodes of a P-channel MOS transistor whose gate electrode is the N⁺ polysilicon layer 20.

0018After a P-channel MOS transistor has thus been made all the photoresist layers 8, 9 and 1₀ are removed from the chip.

0019Reference is now made to Fig. 4 which shows how a N-channel MOS transistor is made. A N⁺mask 15 is first deposited on the P-channel MOS transistor to protect the latter against N material implantation. This implantation operation of N material (phosphorus) schematically indicated by arrows pointing to the windows 16 and 17 produces thin layers of this material under the upper surface of the substrate 1 in these windows. To be noted that during this implantation operation also the field silicon oxide layer 2 and the polysilicon layer 21 are used as masks to ensure that the N material is only implanted under the substrate surface in the windows 16 and 17 and in the whole surface of these windows. For this reason, the mask 15 should not extend in the lateral direction beyond the layer 2.

0020Since the polysilicon layer 21 was already negatively doped (N⁺), there is no need to protect it against the N material implantation. The only consequence of such an additional bombardment of negative ions onto the polysilicon layer 21 is that its doping will increase. This is schematically indicated by N⁺⁺ in Fig. 4. Because the polysilicon layer 21 constitutes the gate electrode of a N-channel MOS transistor, the degree of doping of this layer, as long as it remains in an acceptable range, is of less importance for the operation of this transistor. The drain and source electrodes of the above mentioned N-channel MOS transistor are the N regions 18 and 19 obtained by a diffusion drive-in operation of the implanted N material in the P substrate 1. This diffusion operation is similar to the one described above.

0021The photoresist layer 15 is then removed and the process for making the two MOS transistors may be completed in a classical way.

0022While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.