Integrated circuits with several aluminium alloy interconnection levels and method of manufacture.

The present invention relates to the field of integrated circuits, and relates more precisely to the fabrication steps in which is carried metal interconnects between the various components (including transistors) formed on the surface or in the volume of a circuit substrate integrated.

It increasingly seeks to achieve several successive interconnection levels so as to increase the complexity of the circuits that can be integrated on a given surface. Thus, a first metal interconnect layer is deposited and etched according to a first pattern of interconnections between circuit elements made previously; Then, an insulating layer is deposited and etched to open timely access window to the first layer; finally, a second metal layer is deposited and etched according to a second interconnection pattern.

1 shows symbolically, in a top view, two line conductors Al and B1 of a first interconnection layer, and two column lines A2 and B2 of a second interconnect layer. Al and A2 conductors intersect and are in contact with each other in a contact region Z1 to the crossing place. For cons, the conductor is insulated A2 B1 driver to where it crosses; similarly, the B2 conductor is insulated Al conductor as the conductor B1 where it crosses.

Between conductors A2, B2 of the second interconnection layer and the Al conductor, B1 of the first layer, there is an insulating layer except it in a window that contains FI Z1 contact area between A1 and A2 conductors .

One can imagine for example that the Al conductor generally based on an IO insulating layer covering the substrate S, except in a FO window where the insulating layer 10 is open and when the Al conductor is in contact with a semiconductor region of the substrate S (source or drain of a transistor for example).

FIG 2 and FIG 3 illustrate in vertical section the structure resulting from the foregoing description. Figure 2 is a section along the line II-II of Figure 1, that is to say along the A2 column conductor; Figure 3 is a section along the line III-III of Figure 1, that is to say along the line conductor Al.

F1 window positioning accuracy reasons at the intersection of Al and A2 drivers, it is necessary to provide that this window has dimensions, width and length, greater than the width of Al and A2 drivers.

This results in manufacturing defects that will be explained hereinafter by exposing the structure manufacturing process described in Figures 1 to 3: having made the semiconductor elements embedded in a substrate S, this substrate is covered with an insulating layer IO, for example of silicon oxide; This layer is etched to open the FO window where we must make contact with an element of the underlying substrate, such as a transistor; depositing a first metal interconnection layer which is etched to form a first desired interconnection pattern Oignes Al and B1); depositing another insulating layer I1 (silicon oxide, for example); it is etched to open FI windows encompassing the desired contact zones Z1, IFs windows being wider than the zones Z1; is then deposited the second metal interconnection layer, which is etched to form a second desired interconnection pattern (A2 and B2 lines).

One problem lies in the choice of interconnect metals. Aluminum is a common metal, easily depositing and etching. But he has a tendency to crystallize after filing and form troublesome surface irregularities ( "hillocks"). In addition, the aluminum combines with the silicon and creating defects in the monocrystalline silicon in particular at the contact points on active regions of source and drain. To avoid these two problems, not depositing pure aluminum but a ternary alloy of aluminum, silicon and a third metal which was mainly until now copper.

Unfortunately, the ternary alloy Al-Si-Cu, it can be properly etched by chemical etching, is poorly adapted to a dry etching (plasma or reactive ion etching) with usual etchants: there remains after etching of copper chlorides residues conductors may cause short circuits. Dry etching is yet far preferable to chemical etching for the definition of interconnection patterns, due to its directivity (vertical anisotropic etching) which allows real dimensional control.

The choice we do here as interconnect metal is a ternary mixture of aluminum, silicon and tantalum, or possibly aluminum, silicon and titanium, which solve the problems mentioned above (no recristaJJisation, low electromigration possibility of dry etching with a chlorinated compound such as carbon tetrachloride CCl₄).

However, if all goes well during the etching of the first alloy interconnect layer ternary Al-Si-Ta, one encounters a problem during etching of the second layer (which also can be alloy binary Al-Si ternary and not) sought to burn the second layer by dry etching; but it is difficult to control the depth of the etching, and the alloy Al-Si-Ta of the first layer anoint Al), laid bare in the F1 window may be partially attacked at the end of the engraving lines A2 , B2 of the second layer. This results from that the width of the IF window is greater than the width A2 of the conductor.

It may actually result in a structure that, instead of that of Figure 3, is instead that of Figure 4 wherein the Al-conductor is partially or completely cut off from either side of the zone contact A2 driver in window F1. A full cut is obviously unacceptable, but even a partial cut is troublesome because it causes a reduction in the flow section of the current jeopardize functioning circuits.

To remedy this drawback, it has been found generally necessary to ensure that the A2 conductor is expanded at the contact Z1 to a dimension greater than that of the IF window, but this causes an increase in the minimum distance of guard to be provided between adjacent row lines of an interconnection pattern, thus reducing the integration density.

The present invention provides a circuit fabrication process integrated with at least two metal interconnect levels among themselves punctual contact areas, which method comprises steps similar to those which have been described with reference to Figures 1 to 4 to know :<ul><li>a) depositing a first interconnection layer formed by a ternary alloy,</li><li>b) selective dry etching of the first layer through an open mask in a desired interconnection pattern,</li><li>c) depositing an insulating layer,</li><li>d) etching said insulating layer to open windows at the location of the desired contact areas, the windows being wider than the contact zones,</li><li>e) deposition of a second interconnect layer of an aluminum alloy,</li><li>f) selectively dry etching, from a chlorinated compound, the second layer, through an open mask according to another desired interconnection pattern.</li></ul>

The method according to the invention further comprises, between steps d) and e), namely after the etching windows of the insulating layer and before the deposition of the second layer of aluminum alloy, the deposition of a thin layer of tantalum. The second layer of aluminum alloy is etched using a chlorine compound; tantalum remaining after this etching is then removed where it is not covered with aluminum alloy, without masking operation (or with the same mask which has just served for the etching of the second layer) by means a selective etchant relative to the aluminum alloy and the material constituting the insulating layer.

By "dry etching" means herein an engraving that is not performed in a chemical bath but in a plasma etching frame or reactive ion etching.

Other characteristics and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the accompanying drawings in which:<ul><li>- Figures 1 to 4 already described, show an interconnect structure with two levels of the prior art,</li><li>- Figures 5 to 9 show a first variant of the manufacturing method according to the invention.</li></ul>

In Figure 5, there is shown a substrate 10 which may be a silicon substrate in which there is provided a number of unrepresented circuitry, including transistors. The top surface of the substrate was shown flat for simplicity, but we must understand that it can be strongly shaped by the underlying circuits.

this surface is covered with an insulating layer 12, for example silicon oxide (SiO or Si0₂) Deposited at low pressure, which subsequently depend on the first interconnect layer.

this insulating layer 12 is etched to open windows 14 where a first metal interconnect layer will come into contact with circuit elements underlying the layer 12 (Figure 5).

Is deposited by sputtering in a frame provided for this purpose, a metallic layer in the form of a three-layer aluminum / tantalum / aluminum, aluminum layer containing silicon, and tantalum may be optionally replaced by another metal such as titanium; the thickness of layer 16 is less than one micron.

The silicon and tantalum aluminum proportions can be as follows: about 1.5% silicon, tantalum about 10%, about 90% aluminum.

this layer of aluminum 16 is etched in a dry etching frame (vertical anisotropic plasma etching or reactive ion etching, from a chlorinated compound such as carbon tetrachloride CCl₄ after masking a little resin attacked by the etchant used. The resin masking defines the interconnection pattern of the first interconnect level of the circuit. It is assumed here that the pattern comprises parallel lines A1 and B1 as shown in Figure 1 and Figure 6a shows a longitudinal section of the system along the line Al, figure 6b showing a cross section intersecting this line.

is then deposited, by chemical decomposition in the vapor phase and at low pressure, an insulating layer 18 (silicon oxide SiO or SiO₂ preferably) that will serve to isolate relative to the other two provided metal interconnect levels.

the insulating layer is etched 18 after masking with a resin, to open windows 20 in which the aluminum alloy layer 16 is exposed where it is desired contact between the two levels of metal interconnect. The width of the windows 20 is higher (at least for some of the contacts provided) to the line width of the metal of the first layer, as well as that of the lines of the second metal layer, as shown in Figure 1 about window F1 and A1 and A2 drivers: these windows bursting all around effective contact areas between rows and columns. Remember that these windows are set wide enough to be sure that despite the position variation between the three successive masks respectively defining the first interconnection pattern, windows 20, and the second inter connection pattern, there is no risk that the final contact area between two conductors is reduced relative to that which allows a perfectly aligned position between the three masks; the resulting structure is shown in Figures 7a and 7b (corresponding to the longitudinal and cross sections of Figures 6a and 6b).

is then deposited by sputtering in a suitable frame, a thin layer 22 of tantalum (0.05 to 0.1 microns, for example), and this deposition is followed immediately in the same frame, the deposition of a second layer 24 aluminum alloy (of the order of one micron thick); the alloy is a binary alloy (Al-Si) or ternary. This second layer is etched, dry vertical anisotropic etching by means of a chlorinated compound (CC1₄ for example) after masking by a resin resistant to this material, the mask defining the interconnection pattern of the second layer (parallel columns A2 and B2 in Figures 8a and 8b are longitudinal and transverse sections corresponding to Figures 7a and 7b ). A2 A1 conductive cutting the conductor within a window 20. In Figure 8b, it is assumed that the cross section is carried out along a column conductor A2.

Tantalum 22 is not attacked during the etching using a chlorine-containing compound, so that it protects against etching the aluminum alloy of the first layer 16 in the window 20.

then one can, while remaining in the same frame with the same mask or no mask at all, remove tantalum wherever it is exposed, that is to say where it is not protected by aluminum of the second interconnect level, by dry etching using a fluorinated compound, for example sulfur hexafluoride SF_Ó.

If the elimination of tantalum is done by dry etching, we can easily stop this etching by detecting the appearance of products from the beginning of Attack of the thick layer of oxide 18.

In the following fabrication steps of the integrated circuit, tantalum remains as the second interconnection layer is combined closely with the compounds of this layer and form a thin layer with a high concentration of tantalum in the main alloy layer aluminum depxième level.

There remains, at the end of these steps, a semi-conductor structure having two levels of interconnections between them punctual contact areas, wherein:<ul><li>- One of the interconnect levels is formed by a ternary alloy of aluminum (16),</li><li>- The contact areas are formed by a superposition of a ternary alloy of aluminum (16), a thin layer with a high concentration of tantalum (22), and a second aluminum alloy (24)</li><li>- The second interconnect level is formed throughout by the superposition of a thin layer (22) with a high concentration of tantalum and a layer of aluminum alloy (24)</li><li>- Course, if the aluminum alloy of the first or second level is an alloy containing tantalum, the tantalum concentration in the lower portion of the second level is higher than the concentration in the rest of the first or second level.</li></ul>

This structure, visible in Figures 9a and 9b, may be again covered with an insulating layer 26 of passivation or insulating layer for separating the second interconnect level of a third level achieved in the same manner as the second.

Are thus produced multi-layer interconnect structures with a particularly simple process not requiring an increase in the spacing between conductive lines.