Frequency synthesizer with functional division having a low phase jitter, and use of this synthesizer.

The invention relates to a frequency synthesizer implementing a fractional division method for generating frequencies of various values ​​with a very fine pitch and a low phase jitter.

A full division digital synthesizer includes a servo oscillator controlled by a voltage supplied by a phase comparator receiving a reference signal and a signal obtained by dividing the frequency of the servo oscillator by a variable rank divider. The rank of this divider is fixed. The value of the synthesized frequency can be adjusted by changing this rank, but this adjustment can only be made in steps equal to the frequency of the reference signal.

The fractional rank division method makes it possible to obtain a synthesized frequency whose value is intermediate between the values ​​corresponding to two whole and consecutive rows of the division by the divider with variable rank, by making this divider work alternately with these two rows. When the synthesized frequency has such a value, the phase comparator provides a non-zero, periodic signal, reflecting the sliding of the phase of the signal of the controlled oscillator relative to the phase of the reference signal. This periodic signal is not suitable for directly controlling the slave oscillator. It is added to a so-called compensation signal, then filtered to obtain an oscillator control signal having a constant value in steady state.

The compensation signal is generated by a digital device, called a phase accumulator, and a digital-analog conversion and correction device. The correction consists in making the compensation signal proportional to the period<maths id="math0001"><img file="EP0147307A2_D0001.tif" /></maths>, as is the signal provided by the phase comparator. In steady state, and in the case of an ideal operation, the control signal of the oscillator has a constant value, the frequency supplied by the controlled oscillator is perfectly stable, and its spectral purity is perfect. In practice, the spectral purity is not perfect since there remain lines of phase jitter due to imperfect compensation.

Such a fractional division synthesizer is described in French patent application No. 81 15808 in the name of the Applicant. It includes a phase comparator providing a current of fixed intensity during a time interval whose duration is proportional to the phase difference and to the period<maths id="math0002"><img file="EP0147307A2_D0002.tif" /></maths>the signal supplied by the slave oscillator; it includes a counter, called phase accumulator, which is incremented, by a constant value, at the frequency F_R of the reference signal, and an output of this counter controls an increase of one unit in the rank of the divider during the periods when the content of this counter passes by its maximum value; this synthesizer further comprises a digital-analog conversion and correction device, consisting of a digital-analog converter controlled by the signal supplied by the slave oscillator, to supply a current I_C1 having an intensity I₁ constant during a determined time interval, and zero intensity the rest of the time.

Intensity I₁ = k_ox C₂ is proportional to a C value₂ supplied by the phase accumulator, k_o being a constant. The duration of the time interval is equal to<maths id="math0003"><img file="EP0147307A2_D0003.tif" /></maths>, where k is a constant, so that it is proportional to the period <maths id="math0004"><img file="EP0147307A2_D0004.tif" /></maths>. This duration does not depend on the content of the phase accumulator.

The currents supplied by the phase comparator and by the conversion and correction device are integrated as a function of time by an integrator. During each period of the reference signal, the compensation is carried out by providing, by the compensation current, an amount of charges neutralizing the amount of charges provided by the current supplied by the phase comparator. When these two currents have become zero again the output voltage of the integrator is sampled, memorized, filtered, and constitutes the control voltage of the slave oscillator.

This device has the drawback that it can only be used in synthesizers where the pitch of variation of the synthesized frequency is relatively large. Indeed, this step is inversely proportional to the modulo M of the phase accumulator, and this modulo determines the number of bits of the digital-analog converter. Current digital-to-analog converter technology currently limits this number of bits to 16 bits in binary code, or to 4 decimal digits coded in binary. These high resolution converters are slow (setup time greater than 5 microseconds) and expensive. If, for example, the modulo of the phase accumulator is equal to M = 10 000 and if the value supplied by the phase accumulator is represented by 4 decimal digits coded in binary, the converter must have 16 input bits, and, if the period of the reference signal is one microsecond, the establishment time must be much less than one microsecond. This performance is not possible in the current state of digital-to-analog converter technology, which leads to increasing the step value or reducing the speed of variation of the synthesized frequency.

Another digital-analog conversion and correction device, not comprising a digital-analog converter, can be constituted by a current source, of intensity 1₂ fixed, in series with a switch controlled by a timer providing a variable duration signal <maths id="math0005"><img file="EP0147307A2_D0005.tif" /></maths>proportional to the value ^VS₂ supplied by the phase accumulator and proportional to the period <maths id="math0006"><img file="EP0147307A2_D0006.tif" /></maths>, k₂ being a constant. This solution is simple and it can be implemented in a synthesizer having a very fine pitch since the value M of the modulo of the phase accumulator can be as large as necessary, without limitation due to the technology of digital-analog converters. However, the duration<maths id="math0007"><img file="EP0147307A2_D0007.tif" /></maths>of the compensation signal I_C2 obtained can go up to M - 1 periods <maths id="math0008"><img file="EP0147307A2_D0008.tif" /></maths>of the timer clock signal, and M being of high value when the step is very fine, this duration becomes too long because it exceeds the duration of the reference period which is particularly short in the case where the synthesizer must allow variations fast frequency. For example, if M = 10,000, and if the timer clock frequency is of the order of 30 MHz, the maximum duration of the compensation signal is 333 microseconds and is incompatible with the period of the reference signal if this ci has a value of the order of 1 microsecond. It is not possible to use an intensity 1₂ high to save time because, for low values ​​of C₂, the duration of current flow must then be so short that it is impossible to carry out a switching. This device therefore does not allow rapid variations in the synthesized frequency.

The object of the invention is a fractional division synthesizer which does not have the drawbacks of the two types of synthesizers mentioned above and which, in particular, includes a digital-analog conversion and correction device providing a compensation signal such as the phase jitter of the synthesized signal is very low, while allowing a high speed of variation and a high resolution of the synthesized frequency. For this, the compensation signal, I_C3, has both an intensity and a duration depending on the value supplied by a phase accumulator.

Another object of the invention consists in the use of a fractional division frequency synthesizer, with low phase jitter, in a radio monitoring receiver.

If, for example, the phase accumulator supplies a decimal value coded in binary by three value words: P₁, P₂, P₃, the compensation current I_C3 consists of the sum of three currents I_C31, I_C32, I_C33, of fixed intensities: I, <maths id="math0009"><img file="EP0147307A2_D0009.tif" /></maths>, <maths id="math0010"><img file="EP0147307A2_D0010.tif" /></maths>, whose durations are respectively equal to <maths id="math0011"><img file="EP0147307A2_D0011.tif" /></maths>, where k₃ is a constant. Current I_C3 thus has a variable intensity during the time interval in which it is supplied to an integrator, and this time interval has a variable duration as a function of the content P₁, P_2' P₃ of the accumulator and according to the synthesized frequency F_S.

Intensities I, <maths id="math0012"><img file="EP0147307A2_D0012.tif" /></maths>, <maths id="math0013"><img file="EP0147307A2_D0013.tif" /></maths>, being fixed there are no production problems encountered with digital-analog converters. On the other hand, when the content of the phase accumulator has a high value, the value of greatest weight, P₃, is not zero, a current of relatively high intensity I, is generated. A large amount of charge is therefore brought by the compensation current to the integrator, in a much shorter time than by the process where the compensation current has an intensity I_C2 fixed, and of low value. The period of the reference signal can therefore be short, and allow rapid variations in the synthesized frequency.

According to the invention, a fractional division frequency synthesizer, with low phase jitter, comprising:<ul id="ul0001" list-style="none"><li>- a controlled oscillator providing a period signal <maths id="math0014"><img file="EP0147307A2_D0014.tif" /></maths>;</li><li>- a first analog adder having an output coupled to a control input of the oscillator;</li><li>- a variable rank frequency divider RV, providing a frequency signal <maths id="math0015"><img file="EP0147307A2_D0015.tif" /></maths>;</li><li>- means for providing a reference signal;</li><li>- a modulo M counter, called phase accumulator, supplying a binary word C whose value, modulo M, increases by a value kM at each period of the reference signal, k being between 0 and 1;</li><li>- a digital-analog conversion and correction device, coupling a first output of the phase accumulator to a first input of the first adder;</li><li>a phase comparator receiving the signal provided by the divider and the reference signal, and supplying a second input of the first adder with an analog signal whose value is proportional to the phase difference between these two signals and proportional to the period <maths id="math0016"><img file="EP0147307A2_D0016.tif" /></maths>;</li></ul>

is characterized in that the digital-analog conversion and correction device comprises:<ul id="ul0002" list-style="none"><li>a plurality of timing devices, each providing a timing of duration proportional to the value of a determined fraction of the binary word C and proportional to the period F; S</li><li>- A plurality of sources each providing an analog signal whose value is constant and corresponds respectively to the weight of one of the fractions of the binary word C;</li><li>- a second analog adder having an output coupled to the first input of the first analog adder;</li><li>- A plurality of analog switches respectively connecting the sources to inputs of the second adder and being controlled respectively by the timing devices.</li></ul>

The invention will be better understood and other details will appear on the basis of the description below and the accompanying figures:<ul id="ul0003" list-style="none"><li>- Figures la and lb represent the graphs of the currents ICI and I_C2 as a function of time, currents which are supplied respectively by the two digital-analog conversion and correction devices of the prior art mentioned above;</li><li>- Figures 2a to 2c represent the graphs, as a function of time, of the currents I_{C31 '} I_C32, I_C33, making up the current I_C3 provided by the digital-analog conversion and correction device of the embodiment of the synthesizer according to the invention mentioned above;</li><li>- Figure 2d represents the graph, as a function of time, of this current ^I_C3^;</li><li>- Figure 3 shows a block diagram of another embodiment of the synthesizer according to the invention;</li><li>- Figures 4 and 5 show more detailed block diagrams of two parts of this other embodiment;</li><li>- Figures 6 to 8 show time diagrams illustrating the operation of this other embodiment;</li><li>- Figure 9 shows a timing diagram illustrating the operation of an alternative embodiment of the synthesizer according to the invention.</li></ul>

The exemplary embodiment shown in FIG. 3 comprises: a controlled oscillator 11, a filter 12, a sampler-blocker 13, an integrator 14, an analog adder 15, a divider 8 with variable rank, a phase comparator 9, a device 10 for digital-analog conversion and correction, an oscillator and a divider 6, a device 7 called phase accumulator, and means 29 for controlling the sampler-blocker 13.

The synthesized frequency has the value: F_S = (N + k) .F_R, where N is an integer, where k is between 0 and 1, and where F_R is the frequency of the reference signal. In this example F_R is equal to 1 MHz. The value N is applied by an input terminal 26 to an input of the divider 8 with variable rank, in the form of two decimal digits coded in binary. A value kM is applied by an input terminal 23 to an input of the phase accumulator 7, in the form of four decimal digits coded in binary. The value kM is therefore an integer value between 0 and M. M is the value of the module of the phase accumulator 7, which is equal to 10,000 in this example.

The setting step of the synthesized frequency only depends on the value of the modulo M of the phase accumulator 7, in this example the finest step corresponds to <maths id="math0017"><img file="EP0147307A2_D0017.tif" /></maths>of the difference between the F values_S of the synthesized frequency corresponding to rank N and to rank N + l. The divider 8 has a variable rank RV which is equal to either N or N + 1, depending on the value of a logic signal D provided by an output of the phase accumulator 7, this logic signal being provided when the content of the phase accumulator reaches or exceeds its maximum value which is M = 10,000.

The controlled oscillator 11 has an output providing a frequency signal F_S, which is the synthesized frequency, on the one hand at an input of the divider 8 and on the other hand at an output terminal 16 of the synthesizer. The F_S divider 8 has two outputs providing two frequency signals RV and _RP respectively, at two inputs of the digital-analog conversion and correction device 10. On the other hand, the signal of fr-F^quence _RV is applied to a first input of the phase comparator 9 and to an input of the control means 29. A thermostatically controlled 20 MHz oscillator and a frequency divider, 6, provide a reference signal, of frequency F_R = 1 MHz, at a second input of the phase comparator 9 and at an input of the phase accumulator 7. The phase accumulator 7 has a multiple output providing a digital value C represented by four decimal digits coded in binary, at an input of the device 10. An output of the phase comparator 9 supplies a current of intensity Ip to an input terminal 27 of the adder 15. An output of the device 10 supplies a current of intensity I_q to an input terminal 28 of the adder 15.

The output of the adder 15 supplies a current to an input of the integrator 14, the latter supplying a voltage of value at its output V. The output of the integrator 14 is connected to an input of the sampler-blocker 13 which is controlled by a sampling signal E generated by the control means 29, from the reference signal. An output of the sampler-blocker 13 is connected to an input of the filter 12 to supply it with a voltage V_ech . An output of the filter 12 is connected to a control input of the asserillated oscillator.

The integrator 14 performs an integration as a function of time, of the charges provided by the intensity currents Ip and I_VS. The integrator 14 also performs a sign change and supplies a voltage V. This voltage is sampled by the sampler-blocker 13 at a frequency equal to the frequency FR, but with a constant delay relative to the reference signal. The voltage supplied by the sampler-blocker '13 is filtered by the filter 12 to be smoothed during transient periods. In steady state, the variations in the quantities of charges provided by the intensity currents I_p and I_q compensate each other and the voltage supplied to the controlled oscillator 11 is constant. The phase comparator 9 supplies a signal which is constituted by a current whose direction is negative when the signal supplied by the divider 8 is late compared to the signal supplied by the oscillator and divider 6, and positive otherwise. The amplitude of this signal is constant, it is an intensity of value Ip.

The phase accumulator 7 accumulates the value kM at the frequency. F_R and supplies the cumulative value to the device 10 which supplies a current of intensity I_q variable as a function of time in such a way that the quantity of charges is proportional to the value C of the content of the phase 7 accumulator and to the value <maths id="math0018"><img file="EP0147307A2_D0018.tif" /></maths>. On the other hand, the phase accumulator 7 supplies the signal D, when its content reaches or exceeds the value 10,000, in order to increase the division rank of the divider 8 by one, this rank is then RV = N + 1.

FIG. 4 represents a block diagram of the divider 8 with variable rank of this exemplary embodiment. It comprises a predivisor 30, a main down-counter 31, an auxiliary down-counter 32, a read-only memory 33, and an adder 34. The predivisor 30 is a counter with two modulo: 5 or 6, having an input receiving the frequency signal F_S supplied by the output of the slave oscillator 11; a 5/6 command input selecting the value 5 or the value 6 for the predivision rank_RP; and an output providing a frequency signal RP.

This signal is supplied to an output of the divider 8 and is applied to a clock input H of the main down counter 31 and to a clock input H. of the auxiliary down counter 32, the latter being validated by a clock validation input. . The main down-counter 31 and the auxiliary down-counter 32 each have an input Da for data to be loaded into these down-counters. The input Da of the main down-counter 31 receives a binary word of five bits representing an integer N. The input Da of the auxiliary down-counter 32 receives a binary word of three bits supplied by the output of the adder 34. The adder 34 receives on a first input a binary word of three bits of value N_at, supplied by an output of the read-only memory 33, and receives on a second input the logic signal D supplied by the phase accumulator 7. An address input of the read-only memory 33 receives the value N in the form of two digits binary coded decimals. The value N and the value of the logic signal D determine the value RV of the rank of the divider 8. When the signal D has the value 1 the adder 34 adds a unit to the value of Na.

An output O of the main down-counter 31 is connected to a loading control input ch of this same down-counter 31, to a loading control input ch of the auxiliary down-counter 32, and to an output of the divider 8. This output provides the signal of frequency F_S RV. An output O of the auxiliary down-counter 32 is connected to the clock validation input of this same down-counter 32, and to the control input 5/6 of the predivisor 30, controlling the value RP of the predivision rank. This output provides the frequency signal<maths id="math0019"><img file="EP0147307A2_D0019.tif" /></maths>.

The predivisor 30 is made in ECL technology while the other elements of the divider 8 are made in TTL FAST (Fairchild Advanced Schottky TTL) technology. During each period of the frequency signal FS, the predivisor 30 operates during a first time interval with a predivision rank RP = 6 then, during a second time interval, with a predivision rank RP = 5. At the start of each of these periods, the down counters 31 and 32 are loaded respectively with the values ​​N_p and N_at+ D, D taking the value 0 or 1. During the first time interval the down counters 31 and 32 count down at the frequency <maths id="math0020"><img file="EP0147307A2_D0020.tif" /></maths>. Since the number N is always greater than the number N, the auxiliary down-counter 32 goes through the value 0 before the main down-counter 31. The output O of the auxiliary down-counter 32 then provides a signal blocking the clock validation input of this same down-counter 32 and controlling the change in the predivision rank so that it takes the value 5. During the second time interval, the main down-counter 31 is the only one to operate. It counts down until its content passes through the value 0, its output O then providing a signal which again causes a loading of the values ​​N and N _at + D respectively in down counters 31 and 32, the cycle then starts again.

During each period the number of pulses, of frequency F_{S '} received by the divider 8, is equal to: RV = 6. (N_at+ D) +5. (N_p-NOT_at-D) = N_at + 5.N_p+ D

To make a synthesizer covering frequencies 100 to 150 MHz, with a reference frequency F_R = 1 MHz, read only memory 33 provides N values_p and N_atwhich are as follows:<tables id="tabl0001" num="0001"><img file="EP0147307A2_D0021.tif" /></tables>

It should be noted that N is always between 0 and 4 inclusive. The first time interval therefore has a duration between 0 and<maths id="math0021"><img file="EP0147307A2_D0022.tif" /></maths>according to the value of F_S to obtain.

In general, if n + 1 and n are the two successive values ​​of the predivision rank RP, then the rank of the divider 8 is:<ul id="ul0004" list-style="none"><li>RV = (n + 1) .N_at+ (N_p-NOT_at) .n, which is still equal to:</li><li>RV = N_at+ nN_p</li></ul>

In order for the variable rank divider to function, it is shown that it is necessary that N_p either greater than or equal to N_at and that n² - n is less than or equal to the minimum value of RV.

FIG. 5 represents a block diagram of the phase comparator 9, of the phase accumulator 7 and of the device 10 for digital-analog conversion and correction. The phase comparator 9 comprises a device 45 for detecting phase advance or delay, two analog switches 46 and 47, two current sources 49 and 50, and an analog adder 48. The phase comparator 9 has two inputs receiving respectively, the reference signal, of frequency FR, and the signal provided by the output of the variable rank divider 8, of frequency <maths id="math0022"><img file="EP0147307A2_D0023.tif" /></maths>, and these inputs are respectively connected to two inputs of the device 45. The device 45 has two outputs respectively supplying two logic signals to the control inputs of the switches 46 and 47. The current sources 49 and 50 each have a first terminal connected to a reference potential and a second terminal connected to an input of the analog adder 48 via switches 46 and 47 respectively. The adder 48 has an output which constitutes the output of the phase comparator 9 and which is connected to the terminal 27.

The device 45 is a digital device which consists of two flip-flops D, of ECL technology, and the production of which is within the reach of those skilled in the art.

When the signal supplied by the output of the variable-rank divider 8 is in phase advance with respect to the reference signal, the device 45 provides a control signal closing the switch 46 so that it transmits the current supplied by the current source 49 , this current being of negative sign and of intensity I_AT. When the signal supplied by the output of the variable-rank divider 8 lags behind the reference signal, the device 45 provides a control signal closing the switch 47 so that it transmits a current supplied by the current source 50, current of positive meaning and intensity I_R. The duration of these signals is equal to the time interval separating a rising edge from the signal supplied by the variable rank divider 8 and the corresponding rising edge from the reference signal. This duration is therefore proportional to the phase difference between these two signals. The output of the analog adder 48 provides a current of intensity Ip which is constituted by one of these two currents.

The phase 7 accumulator consists of four modulo 10 adders: 51, 52, 53, and 54; and four registers: 55, 56, 57, and 58. In this example, the phase accumulator 7 has for modulo M = 10 000 and the value of the increment, applied to its input, is kM expressed by four digits binary coded decimals. The phase accumulator 7 comprises four accumulators respectively receiving the four binary coded decimal digits of the increment kM These four accumulators consist respectively of the adder 51 and of the register 55, of the adder 52 and of the register 56, of the adder 53 and of the register 57, of the adder 54 and of the register 58. These accumulators receive the binary coded digits of increasing weight in this order. Each adder has a carry output connected to a carry input of the following adder in the order 51, 52, 53, 54, and the carry output of the adder 54 constitutes the output of the phase accumulator 7 providing the logic signal D which controls the passage of the rank of the divider 8 from the value N to the value N + 1, when the signal D has the value 1.

Each of the adders 51, 52, 53, 54 has a first entry receiving the four bits of one of the binary coded decimal digits of the increment kM; a second input receiving four bits supplied by the output of the associated register: 55, 56, 57, 58; and an output providing four bits to an entry in the associated register. Each register 55 to 58 has a control input receiving the frequency reference signal F_R. The four bits provided respectively by the output of each of the registers 55 to 58 represent respectively P values₁, P₂, P₃, and P 4 binary decimal digits of the number C supplied to the device 10.

The synthesizer according to the invention is characterized by its digital-analog conversion and correction device 10, which differs from the known devices mentioned above, and overcomes their drawbacks.

The device 10 comprises a control device consisting of a down-counter 36, a logic inverter 39, and two flip-flops of type D: 37 and 38; four timing devices made up of four modulo counters 10: 59, 60, 61, and 62; and consist of four JK type flip-flops: 63, 64, 65, and 66; and has four analog switches: 67, 68, 69, and 70; five current sources: 71, 72, 73, 74, and 75; three current dividers: 76, 77, and 78; and two analog adders 79 and 80.

The counters 59 to 62 are associated respectively with the flip-flops 63 to 66 and they respectively receive the values ​​P₁, P₂, P₃ and P₄ on data load entries. For example, the data loading input of counter 59 is connected to the output of register 55 to receive the value P,; output<o>T</o>_<o>4</o>and an entry <o>ch</o>_<o>4</o> of the counter 59 are connected respectively to an input K3 and to an output Q₃ of the flip-flop 63. Each of the counters 59 to 62 and each of the flip-flops 63 to 66 have a clock input H receiving the frequency signal <maths id="math0023"><img file="EP0147307A2_D0024.tif" /></maths>provided by the output of the predivisor 30 of the divider with variable rank 8. Each of the flip-flops 63 to 66 has an input J connected to an output Q₂ of scale 38.

Each of the flip-flops 63 to 66 has an inverted output Q connected to a control input of one of the switches 67 to 70, respectively. Each of these switches transmits a current supplied by a current source in series with a current divider: the switch 67 transmits a current i_l supplied by the current source 72 and the current divider 76, with a ratio of 1/1000. The switch 68 transmits a current supplied by the current source 73 in series with the current divider 77, with a ratio of 1/100. The switch 69 transmits the current supplied by the current source 74 in series with the current divider 78, with a ratio of 1/10. The switch 70 transmits the current supplied by the current source 75.

The current sources 72 to 75 supply a current of negative direction and of identical intensity I. They have a common terminal connected to a reference potential. The analog adder 79 has an output providing a current of intensity I_VS to a first input of the analog adder 80. A second input of the analog adder 80 receives a current of intensity I_B and in the positive direction, called bias current, supplied by a first terminal of the current source 71. A second terminal of the current source 71 is connected to the reference potential. The output of the adder 80 constitutes the output of the device 10 and is connected to the terminal 28. It supplies the current Iq.

An input of the device 10; receiving the frequency signal<maths id="math0024"><img file="EP0147307A2_D0025.tif" /></maths>provided by the output of the variable-rank divider 8, is connected to a ch-input for controlling the loading of the downcounter 36. The downcounter 36 also has a data loading input permanently receiving the value 6, a clock input H receiving the frequency signal <maths id="math0025"><img file="EP0147307A2_D0026.tif" /></maths>provided by the output of the predivisor 30 of the variable rank divider 8, and an output <o>T</o>_<o>1</o><o></o>providing a logic signal of value 0 when the content of the down-counter 36 goes through the value 0. This output <o>T</o>_<o>1</o> is connected to a validation input of the counter 36 and to a clock input H of the flip-flop 37 via the logic inverter 39.

Flip-flop 37 has an input D₁ permanently receiving a value 1, a reset input <o>VS</o>_<o>1</o><o></o>connected to an output <o>Q</o>_<o>2</o><o></o>of flip-flop 38, and an output Q_I which is connected to an input D₂ of flip-flop 38. Flip-flop 38 also has a clock input H receiving the frequency signal <maths id="math0026"><img file="EP0147307A2_D0027.tif" /></maths>.

Figures 6 and 7 show timing diagrams of the signals used in the exemplary embodiment shown in Figure 5. Figure 6 shows these diagrams for four time intervals T₁, T₂, T₃, and T₄ corresponding to four periods of the frequency signal <maths id="math0027"><img file="EP0147307A2_D0028.tif" /></maths>and at three periods TR₁, T_R2, T_R3 of the reference signal. The pulses of the reference signal, noted F_R, and the pulses of the signal supplied by the output of the variable-rank divider 8, noted <maths id="math0028"><img file="EP0147307A2_D0029.tif" /></maths>, are offset by a variable time respectively equal to T₀ + Δt₁, T₀ + Δt₂, T₀ + Δt_max, and T₀. The T value₀ is a constant which is equal to the time interval between the pulses when the variable division rank RV is equal to an integer value, as it is the case when the value k is zero. The T value₀ corresponds to a constant phase advance which is created by the bias current of intensity I_B supplied by the current source 71. This phase advance makes it possible to operate the phase comparator 9 in an operating zone having better linearity, the operation in the vicinity of a zero phase difference being not very linear, and being able to add the phase jitter at the signal supplied by the oscillator 11.

During the time intervals separating the pulses from the F signals_R and <maths id="math0029"><img file="EP0147307A2_D0030.tif" /></maths>the output of the phase comparator 9 provides a current of negative direction and of intensity Ip = I_AT constant; and provides zero current for the rest of the time. During a transient regime, not shown in FIG. 5, the current of intensity Ip is, constituted either by the positive current I_R supplied by current source 50, i.e. negative current and intensity I_AT supplied by the current source 49. When the speed is established, which corresponds to the case represented in FIG. 5, there is always a phase advance of the signal <maths id="math0030"><img file="EP0147307A2_D0031.tif" /></maths>with respect to signal F_R, in this exemplary embodiment. The intensity Ip is then equal to I_AT.

The digital-analog conversion and correction device 10 generates a current of intensity I_q to compensate, after integration, for variations in the intensity current Ip supplied by the phase comparator 9. It should be noted that the integrator 14 also, by its construction, reverses the sign which must be taken into account when interpreting the variations in the output voltage V of this integrator, represented in FIG. 6. The current of intensity I_VS has a variable duration and a variable amplitude as a function of the content C of the phase accumulator 7 and as a function of the synthesized frequency F_S.

The intensity current I_VS results from the addition, by the analog adder 79, of four currents whose intensities are respectively 1/1000, 1/100, 1/10, and I, transmitted respectively by switches 67 to 70 from the same instant, but with different durations determined by the timing device consisting of counters 59 to 62 and flip-flops 63 to 66. These counters and flip-flops have the clock frequency <maths id="math0031"><img file="EP0147307A2_D0032.tif" /></maths>with RP = 5. This clock signal is supplied by the output of the predivisor 30 of the variable rank divider 8, after a certain time interval which depends on the value of the synthesized frequency F_S, because this time interval is determined by the duration of the countdown of the value N_at by the auxiliary down-counter 32. N a + D being able to take the values ​​0 to 5 the output of the predivisor 30 provides a frequency signal <maths id="math0032"><img file="EP0147307A2_D0033.tif" /></maths> for a period at most equal to <maths id="math0033"><img file="EP0147307A2_D0034.tif" /></maths>. This is why the generation RP of the current of intensity C is delayed by a duration equal to<maths id="math0034"><img file="EP0147307A2_D0035.tif" /></maths>which is given by counting 6 pulses plus the delay of flip-flops 37 and 38.

The use of the predivisor 30 to provide the clock signal of the counters 59 to 62 makes it possible to save an independent divider, but above all has the practical advantage of providing a signal better synchronized with the output signal of the divider 8, which decreases the phase jitter of the synthesized signal.

The production of four well-stabilized current sources and of the corresponding four switches is within the reach of those skilled in the art. It is much easier than the realization of a digital-analog converter of 4 x 4 bits having an establishment time of approximately 0.5 microsecond.

The realization of the timing device, which operates at a clock frequency of the order of 30 MHz, is also within the reach of those skilled in the art. The maximum duration of the compensation is short since it is less than or equal to 9 periods of this clock, that is to say approximately 0.3 microseconds. This makes it possible to choose 1 microsecond for the period of the reference signal, from which it follows the possibility of rapidly changing the value of the synthesized frequency, for applications such as panoramic radio surveillance, frequency hopping transmission, all by obtaining precise compensation and therefore a low phase jitter.

In FIG. 6, let us consider the evolution of the voltage V supplied by the output of the integrator 14, during the time interval Tl. During the duration T₀ + Δt₁ the integrator 14 integrates a current of intensity I_B - I_AT corresponding to the bias current and to the current translating the phase advance detected by the phase comparator 9. The integration of these currents causes an increase in the voltage V because I_AT is greater than I_B. When the current Ip supplied by the output of comparator 9 becomes zero again, only the bias current I_B is integrated. This current being of positive direction, and the integrator 14 realizing a change of sign, the voltage V is then decreasing. After a duration t equal to<maths id="math0035"><img file="EP0147307A2_D0036.tif" /></maths>, counted from the signal pulse <maths id="math0036"><img file="EP0147307A2_D0037.tif" /></maths>, the compensation current I_VS is generated, in a direction antagonistic to that of the bias current, the integration of the current of intensity I_B - I_VS therefore causes a slower decrease in blood pressure _V because I_VS is less than I_B. After the end of the integration of this current I_VS, only the intensity bias current I_B is integrated until the end of the duration interval T ₁

The voltage V is sampled under the control of a pulse signal E of period equal to that of the reference signal F_R, at fixed times, located between the end time of the signal Ip and the start of the signal I_VS by a constant delay provided by the control means 29 triggered by the signal F_R. The voltage sampled in this way therefore corresponds to the phase difference remaining after compensation made by means of the current of intensity I_VS, during the period preceding period T₁.

After this sampling, another period of the compensation process begins. Current I_VS generated during part of the interval T₁ compensates, in the integrator 14, for the charge variation caused by the current Ip, of longer duration, generated at the start of the interval T₂. Once the speed has been established, the compensation is almost perfect, the voltage V takes almost the same value V at the end of each period of the reference signal, T_R1, TR₂, T_R3.

Similarly, the sampled voltage has an almost identical value from one period to the next. Sampling being delayed by a constant delay t_ech relative to the rising edge of signal F_R, and the current applied to the integrator 14 being of constant intensity I_B, there is a constant value difference between the voltage V and the sampled voltage.

During periods T₁, T₂, T₃ phase advance of signal RV with respect to signal F_R growing constantly, but during period T₂ the pulse of the reference signal F_R causes the content of the phase accumulator 7 to pass to its maximum value M = 10000, the adder 54 then supplies the logic signal D, of value 1, with a certain delay. Signal D is applied to the second input of the adder 34 of the variable rank divider 8, where it causes an increase of one unit for the variable rank RV of the divider 8, this variation of the rank being effective when the next loading of the downcounters 31 and 32, i.e. on the next signal pulse <maths id="math0037"><img file="EP0147307A2_D0038.tif" /></maths>. During period T₃ the RV division rank of divider 8 being greater, the phase advance of the signal <maths id="math0038"><img file="EP0147307A2_D0039.tif" /></maths> is reduced. In this example, it is equal to its static value at the start of period T₄. The counting in the phase accumulator 7 continuing at the frequency of the reference signal, the signal D returns to the value 0 during the period T₃.

As the phase advance increases, during periods T₁, T₂, T₃, the quantity of charges provided by the compensation current I_VS decreases in absolute value, because the value C initializing the counters 59 to 62 increases with each period T₁, T₂, T₃. Current I_VS has such a meaning, that the reduction in the quantity of charges which it provides causes a reduction in the voltage V at the end of the periods T₁, T₂, taking into account the inversion of sign carried out by the integrator 14. This reduction in V makes it possible to compensate for the increase V caused at the beginning of the following period, T₂ and T₃ respectively, by increasing the quantity of charges provided by the current Ip, the duration of which increases with the phase advance.

Naturally, when the phase advance returns to its static value, corresponding to the time difference T, the value C supplied by the phase accumulator 7 returns to the value 0, this is what happens during the period T R2. The quantity of charges provided by the compensation current I_VS during the period T 3 is then maximum in absolute value, to cause an increase in the voltage V, which will compensate, at the end of the period TR₃, the decrease in V caused by the decrease in the quantity of charges provided by the current Ip, the duration of which passes through its minimum value T₀ at the end of period T_R3.

The intensity compensation current I_VS is the sum of the currents transmitted by switches 67 to 70 under the action of four logic control signals which are generated in an analogous manner for each fraction of the binary word representing the value kM. These currents differ in their value and in their duration. Switches 67 to 70 respectively transmit currents of intensity 1/1000, 1/100, 1/10, and I. The ratio between two consecutive values ​​of these currents corresponds to the ratio of the weights of two consecutive binary words representing the values ​​P₁, P₂, P₃ and P₄.

In this exemplary embodiment the phase accumulator 7 receives a decimal kM value coded in binary and provides a decimal C value coded in binary, therefore the values ​​P₁, P₂, P₃, and P₄ are each between 0 and 9. In another embodiment where the phase accumulator 7 would receive a value coded in binary on 16 bits, it would provide a value C coded in binary on 16 bits and this one would be divided into four 4-bit binary words. The weight of each of these binary words being 16; the ratio between two successive currents would then be fixed at 1/16.

On the other hand, the currents transmitted by switches 66 to 70 have a different duration, respectively proportional to the values ​​P₁, P₂, P₃, and P₄. In addition, these durations are all proportional to the period<maths id="math0039"><img file="EP0147307A2_D0040.tif" /></maths>because the counters 59 to 62 have the clock frequency F_S RP.

Let us consider, for example, the current il which is transmitted by the switch 67, which has an intensity equal to I / 1000, and which corresponds to the value P₁ of the four least significant bits of the binary word C supplied by the phase accumulator 7. The duration of transmission of the current it is determined by the counter 59 and the flip-flop 63.

The timing diagrams of figure 7 illustrate the generation of the current il during three periods: T '₁, You₂, and T '₃ signal, noted <maths id="math0040"><img file="EP0147307A2_D0041.tif" /></maths>, supplied by the variable rank divider 8. When the signal <maths id="math0041"><img file="EP0147307A2_D0042.tif" /></maths>is at the low level it commands the loading of the value 6 in the downcounter 36. When it goes to the high level it authorizes the counting of the counter 36. The downcounter 36 supplies on its output T₁ a level 0 signal with a <maths id="math0042"><img file="EP0147307A2_D0043.tif" /></maths>delay of 6 periods of duration, compared to the rising edge of the signal<maths id="math0043"><img file="EP0147307A2_D0044.tif" /></maths>. The output of the inverter 39 then provides a level 1 signal at the input of the down-counter 36, to block it until the next loading. On the other hand, the passage to level 1 of this logic signal triggers flip-flop 37.

The flip-flop 37 is a flip-flop of type D, whose entry D₁ receives a value 1 permanently. The Q output₁ then supplies a logic signal of value 1 to the input D2 of the flip-flop 38. The flip-flop 38 is a flip-flop of type D, its output Q₂ therefore goes to level 1 on the next signal pulse <maths id="math0044"><img file="EP0147307A2_D0045.tif" /></maths>which is its clock signal. The logic signal of value 1 provided by output Q₂ is applied to the inputs J of flip-flops 63 to 66, so that the next edge of the signal <maths id="math0045"><img file="EP0147307A2_D0046.tif" /></maths>causes the signal supplied by the Q output of these flip-flops to go to value 1, and in particular the Q output₃ of flip-flop 63, to start the counting determining the duration of each current.

On each of the counters 59 to 62 the loading control input ch, which is an input with inversion, receives a signal of value 1 which therefore makes it possible to start counting simultaneously in each of these counters. Counting, therefore the generation of the compensation current, begins with a constant delay with respect to the rising edge of the signal<maths id="math0046"><img file="EP0147307A2_D0047.tif" /></maths>, and this delay is equal to 8 x RV F_S When the Q output₂ of flip-flop 38 provides a signal of value 1, the output Q₂ provides a value 0 signal which activates the reset input C₁ of flip-flop 37. The reset of flip-flop 37 causes the signal supplied by its output Q to return to 0₁. Entrance D₂ of flip-flop 38 receiving a signal of value 0, the next pulse of the signal <maths id="math0047"><img file="EP0147307A2_D0048.tif" /></maths>causes the reset of flip-flop 38. The signal of value 1 applied to the inputs J of flip-flops 63 to 66 therefore only lasts for the duration of a period of the signal <maths id="math0048"><img file="EP0147307A2_D0049.tif" /></maths>, to put the flip-flop 63 in a state authorizing the counter 59 to count.

After being loaded with the value Plaice counter 59 counts. When its content, noted E₁ in figure 6, reaches the value 9, the output T₄ provides a logic signal of value 0 which is applied to input K₃ of flip-flop 63. The next pulse of the clock signal <maths id="math0049"><img file="EP0147307A2_D0050.tif" /></maths>, is counted by the counter ₅₉ like a 10^th pulse, and by the way it causes a reset of flip-flop 63, the signal provided by the Q output₃ taking the value 0 and causing the P value to be loaded into counter 59_l present at the instant considered on the data loading input of this counter. For greater clarity, return to the value 0 of the signal supplied by the Q output₃ is shown on the penultimate line of the timing diagrams shown in Figure 7.

In this example, the signal provided by the inverting output, <o>Q</o>_<o>3</o><o>, </o>of the flip-flop 63, is used to control the switch 67. The intensity current i₁ transmitted by the switch 67 has a duration corresponding approximately to the duration during which the signal provided by the output Q₃ is set to 1, the switches having a certain delay in closing and opening.

At the end of period T '₁, the value P₁ provided by the output of the phase accumulator has the value 9 in this example. The Q output₃ still providing a signal of value 0, the value 9 is loaded into the counter 59. The value 9 being equal to the maximum value that the content of the counter 59 can take the output <o>T</o>_<o>4</o><o></o>provides a signal of value 0 indicating that the content of counter 59 has its maximum value.

Just before the start of period T '₂, the value 0 of the signal <maths id="math0050"><img file="EP0147307A2_D0051.tif" /></maths>causes the down-counter 36 to be loaded with the value 6. The down-counter 36 supplies on its output T̅₁a signal of value 0 delayed by 6 signal periods <maths id="math0051"><img file="EP0147307A2_D0052.tif" /></maths>. This signal causes the signal supplied by the Q output to change to value 1₁ of flip-flop 37, then the next signal pulse <maths id="math0052"><img file="EP0147307A2_D0053.tif" /></maths>causes the signal supplied by output Q to change to value 1₂ of scale 38.

The next signal pulse <maths id="math0053"><img file="EP0147307A2_D0054.tif" /></maths>causes the Q output to change to value 1₃ of flip-flop 63, the counter 59 being thus authorized to count. The content of the counter 59 already having its maximum value, the output T̅₄ provides a signal of value 0 which is applied to the input K̅3 flip-flop 63, while the input J of this flip-flop receives a value 0 because the output Q₂ of flip-flop 38 has returned to state 0 in the meantime. The flip-flop F 63 then being reset to zero by the next signal pulse<maths id="math0054"><img file="EP0147307A2_D0055.tif" /></maths>, the intensity current i₁ is therefore transmitted for the duration of a single signal period <maths id="math0055"><img file="EP0147307A2_D0056.tif" /></maths>.

During period T 'the operation is analogous to that of the two preceding periods. At the start of this period the P value₁ supplied by the output of the phase accumulator 7 is equal to 7. When the counter 59 is authorized to count it counts three signal pulses <maths id="math0056"><img file="EP0147307A2_D0057.tif" /></maths>. It should be noted that, in this embodiment, the duration of passage of the current of intensity i₁ is equal to the complement to 10 of the value P₁ loaded into counter 59, this duration being counted in number of signal periods <maths id="math0057"><img file="EP0147307A2_D0058.tif" /></maths>: during period T '₁ , P₁ = 4, the duration of the passage of i₁ is equal to six periods; during period T '₂ , P₁ = 9, the duration of the passage of it is equal to a period; during period T '₃, P₁= 7, the duration of the passage from i₁ is equal to three periods. This duration is therefore a decreasing linear function of the value P₁ with a minimum duration equal to a signal period <maths id="math0058"><img file="EP0147307A2_D0059.tif" /></maths>.

The direction of variation is explained by the direction of the current of intensity I_ATand the direction of the currents I, which are identical in this exemplary embodiment. Current I_AT, supplied by the phase comparator when there is a phase advance, and the compensation current I_VS both cause an increase in V (Figure 6). To obtain a compensation effect for the variations of these two currents, it is therefore necessary to reduce the duration of the compensation current I_VS when the phase advance increases.

The minimum duration of compensation, which is equal to a signal period F_S RP in this example, is intended to avoid a linearity problem which would be encountered in the case where the value P₁ is equal to the maximum value, 9, of the content of counter 59; if counter 59 did not count a 10^thimpulse the duration of the current it would be strictly zero which would cause an error of linearity of the variation of duration of the current it compared to the variations of P₁, because in practice the switch 67 and the flip-flop 63 introduce a constant in the duration of transmission of the current it each time this duration is not zero, and this constant would be absent in the cases where the duration would be zero.

FIG. 8 represents a timing diagram of the signal supplied by the output Q₃ of flip-flop 63 and of the corresponding intensity current there. The signal shown in solid lines corresponds to a correction of duration t_CR equal to three signal periods <maths id="math0059"><img file="EP0147307A2_D0060.tif" /></maths>: the intensity current i₁ does not instantly reach its nominal value when the signal supplied by the Q output₃ goes to value 1 and, likewise, it does not instantly go back to value 0 when the value provided by the Q output₃ returns to the value 0. It takes a time t _m to reach its nominal value, and it takes a time t_d to return to zero. The times t_m and t_d correspond to quantities of charges which are not necessarily equal and which, therefore, add a constant to the theoretical duration of current transmission.

In Figure 8 are shown in dotted lines the signal provided by the output Q₃ and the corresponding intensity current, for corrections during a period or two periods of the signal <maths id="math0060"><img file="EP0147307A2_D0061.tif" /></maths>. The constant added by the switch 67 to the duration of the correction is the same whatever the duration of the correction, unless it was zero because in this case the switch 67 would not work at all. This is why, in order to maintain perfect linearity of the duration of the correction as a function of the value supplied by the phase accumulator, it is necessary to add a constant to the duration of the correction to make it longer. at duration t_m. In this exemplary embodiment, the sequence of the signals is such that the counters 59 to 62 count one pulse more than the value of the complement to 9 of that which is loaded at the start of the counting. In another exemplary embodiment, a value constant greater than one period can be systematically added to the duration of each correction by using adders placed between the outputs of the phase accumulator 7 and the inputs of the counters 59 to 62, or else using modulo 15 counters which automatically perform an additional count of six pulses before generating on their output <o>T </o>an end of counting signal.

FIG. 9 represents timing diagrams illustrating the operation of a variant of the embodiment described above. According to this variant, in steady state, the signal noted<maths id="math0061"><img file="EP0147307A2_D0062.tif" /></maths>, provided by the output of the variable rank divider 8, has a phase delay with respect to the reference signal, noted F_R.

During successive periods T '_R1, You_R2, You_R3 of the reference signal, the duration of the time interval separating this reference signal and the signal, noted <maths id="math0062"><img file="EP0147307A2_D0063.tif" /></maths>, supplied by divider 8, has the value T '₀ - Δt '₁, You₀ - Δt_max, and T 'respectively; You being a constant. The phase delay is constantly increasing, but at certain times it is brought back to its maximum value, which is its starting value, by an increase of one unit of rank of division RV of divider 8.,

During the time interval between a rising edge of the signal F_R of the corresponding rising edge of the signal <maths id="math0063"><img file="EP0147307A2_D0064.tif" /></maths>, the output of the phase comparator 9 provides a current of intensity I '_p constituted by the intensity current I '_R corresponding to a phase delay. The current corresponding to a phase delay, in this alternative embodiment, has a negative direction unlike the current of intensity I_R of the previous variant, the intensity current I_p provided by the comparator 9 therefore has the same meaning as in the previous variant.

The integrator 14 receives a current of intensity I_B - I '_R which causes an increase in the integrator output voltage, V ', because I_R is greater than I_B. The bias current has the same direction as in the previous variant and the same intensity I_B.

Compensation for variations in the quantity of charges provided by the intensity current l'p is carried out with a fixed delay t '_d, equal to <maths id="math0064"><img file="EP0147307A2_D0065.tif" /></maths> relative to the rising edge of signal F_S RV, as in the previous variant. On the other hand, the sampling is controlled by a signal E 'generated with a delay t'_ech, with respect to signal F_R, much greater than the delay t_ech of the previous variant, because the compensation and the corresponding sampling are carried out during the same period of the reference signal: thus at the end of the periods T '_R1, You_R2, and T '_R3, the voltage V finds a practically identical value: V '₀. The delay value t '_ech is chosen such that, in all cases, sampling takes place after the end of the compensation, and before the end of the signal period F_R. The start of compensation is delayed by a delay<maths id="math0065"><img file="EP0147307A2_D0066.tif" /></maths>for the same reason as in the previous variant, to wait for the availability of the frequency signal <maths id="math0066"><img file="EP0147307A2_D0067.tif" /></maths>supplied by the output of the predivisor 30 of the variable rank divider 8.

During periods T '_R1 and T'R2 the phase delay decreases, because the variable rank of the divider 8 is equal to N.

During periods T '_RI and you_R2 the time interval between the pulses of the reference signal and the signal <maths id="math0067"><img file="EP0147307A2_D0068.tif" /></maths>, decreases, and passes through a minimum T '₀ - Δt '_max during period T '_R2. During this period the content C of the phase accumulator 7 passes through the value 0, the accumulator 7 supplies a signal D of level 1 which causes the passage from the division rank to the value N + 1 during the period T ''_R2. In this example, changing the division rank brings the phase delay exactly to its maximum value which corresponds to T '.

During the period T'R2 the voltage V 'passes through a maximum lower than that where it passes during the period T'_R1. The intensity compensation current I '_VS, which is the same direction as the intensity current P_R supplied by comparator 9, must pass for a longer time so that the voltage V regains the value V '₀at the end of period T'R2. According to this variant, the duration of the compensation current passage therefore varies in the same direction as the content of the phase accumulator 7. The counters 59 to 62 are replaced by modulo counters 10 in order to count a number of periods, from duration<maths id="math0068"><img file="EP0147307A2_D0069.tif" /></maths>, equal S respectively to P values₁, P₂, P₃, and P₄ supplied by the phase 7 accumulator, plus one unit to avoid a non-linearity error when P₁, or P₂, or P₃, or P₄, is equal to 0. The flip-flops 63 to 66 operate in a similar manner to those of the previous variant.

At the start of period T '_R2 the pulse of signal F_R causes the content of the phase accumulator 7 to pass to its maximum value, the signal D takes the value 1 with a certain delay due to the propagation time of the carry in the adders 51 to 54, and causes the next pulse of the signal <maths id="math0069"><img file="EP0147307A2_D0070.tif" /></maths>a unit increase in RV division rank. This increase in the rank of the divider 8 causes an increase in the phase delay observable at the start of the period T '_R3. The variation in the quantity of charges brought by the current l'p at the start of the period T '_R3 is compensated by a shortening of the duration of the current I '_VS of the compensation carried out during this period T '_R3.

The direction of frequency control of the controlled oscillator 11 must be reversed compared to that of the previous variant.

Compared to this last variant, the previous variant has a first advantage which is that the sampling can be carried out during the duration interval <maths id="math0070"><img file="EP0147307A2_D0071.tif" /></maths>. For both variants, this duration is necessarily chosen greater than (n-1) periods<maths id="math0071"><img file="EP0147307A2_D0072.tif" /></maths>, if n is the smallest modulo of the predivisor 30, to be able to have the clock signal at the frequency <maths id="math0072"><img file="EP0147307A2_D0073.tif" /></maths>to supply the clock inputs of counters 59 to 62. In the previous variant, the time interval entered at the end of the delay t '_d and the end of the period of the reference signal can be entirely used for compensation, while in the last variant this interval is reduced by the time occupied by the sampling. This difference is not negligible when the period of the reference signal is very short to allow rapid variations of the synthesized frequency.

The previous variant has a second advantage which is that the propagation time of the carry signal D in the adders 51 to 54 is not critical, unlike the case of the second variant. The carry signal is triggered by signal F_Rand must reach level 1 before the pulse of signal R of the same reference period, T _R2 or T '_R2, so that the auxiliary down-counter 32 is loaded with the value N_at +1 under the action of this impulse. In the case of the first variant, the time interval available for the passage of signal D to level 1 is much longer.

The synthesizer according to the invention can be used in particular as a local oscillator in radio monitoring receivers, requiring rapid frequency variations, a fine step, and good spectral purity.