Linear power amplifier.

p0001The present invention relates to a power amplifier, linear.

p0002Such an amplifier is particularly apply in the electrical signal generators output stage of a predetermined shape, which can be any, including the peak voltage can reach several hundred volts, and this yield can be higher 90% and very reduced distortion, if necessary in the order of 1%.

p0003It is known to use an amplifier of class B-type strongly against is feedback for a very small distortion of the output signal relative to the input signal, but its performance is poor, about 50%. In addition, the transistors which constitute the active elements of the amplifier must meet their "safe area", that is to say, function in a limited area of ​​their output network I_C- V CE (current collector, collector-emitter voltage) in which the power dissipation (product I_C. V_THIS) Remains below a limit value P_max not to exceed. It follows that the transistors can provide maximum output current with low output voltages of either 20V to 40V maximum. For high power with high output voltages, a conventional class B amplifier can not be used. To provide the desired maximum voltage output voltages could add several amplifiers classic B class performance but remain poor.

p0004Also known (see French patent application No. 80.00169 filed in the name of the Applicant) of electrical signal generators of high power (several kW) and high output voltage, which allow to obtain at output a signal predetermined shape with a good yield. For it is associated a plurality of supply circuits controlled by the signal to be amplified and each supplying a voltage pulse whose duration and polarity depend on the waveform to be amplified; these slots occur in a common output load currents that could cumulatively provide the amplified signal.

p0005This type of amplifier can achieve a very good yield, greater than 90%. The resulting distortion is smaller when the number of power supply circuits is higher. However, to obtain a low distortion, of the order of 1%, the number of power supply circuits would be prohibitive (over 100).

p0006The present invention has for object a- amplifier which provides both a very reduced distortion, and high output with high output voltages.

p0007In the power linear amplifier according to the invention, comprising at least one bipolar transistor class B type provided with a said control electrode to which is applied the signal to be amplified, and two electrodes called transfer, on one of which is obtained the amplified signal, and biasing means of said transistor, said bias means comprises a bias signal generator variable in steps, and control means of the generator, depending on the amplitude of the amplified signal to maintain at any moment the voltage between the transfer electrodes, in absolute value, of one of the transistors which is conducting at that moment, at most equal to a limit value .DELTA.V.

p0008The objects and features of the present invention will appear more clearly on reading the following description of exemplary embodiments, taken in conjunction with the accompanying drawings in which:<ul><li>- Figure 1 is a block diagram of an amplifier according to the invention, of the type comprising a single transistor Class B;</li><li>- Figure 2 shows the shape of the bias voltage and the output voltage of the amplifier shown in Figure 1, for a voltage to be amplified data;</li><li>- Figure 3 is a diagram of a first embodiment of an amplifier according to the invention, of the type comprising two transistors class B;</li><li>- Figure 4 shows the shape of the bias voltages of the two transistors and the output voltage of the amplifier shown in Figure 3, for a given voltage to be amplified;</li><li>- Figure 5 is a diagram of a second embodiment of an amplifier according to the invention, of the type comprising two transistors class B;</li><li>- Figure 6 shows the shape of the bias voltages of the two transistors and the amplifier output voltage shown in Figure 5, for a voltage to be amplified data;</li><li>- Figures 7, 8 and 9 are respectively diagrams of a third, a fourth and a fifth embodiment of an amplifier according to the invention, of the type comprising two transistors class B;</li><li>- Figure 10 is a diagram of a sixth embodiment of the amplifier according to the invention, of the type comprising a single transistor Class B;</li><li>- Figure 11 shows the shape of the bias voltage and the output voltage of the amplifier represented in Figure 10, for a voltage to be amplified data.</li></ul>

p0009In the following description, the expression control electrode of a transistor the base of this transistor, and transfer electrodes the emitter and the collector of this transistor.

p0010The amplifier shown in Figure 1 comprises a bipolar transistor type 1 class B, for example, a transistor NPN. The voltage e (t) to be amplified is applied to the base or control electrode of this transistor via a resistor 2.

p0011A bias voltage E, supplied by biasing means 3 is applied to the collector of this transistor.

p0012This transistor is against receives feedback by a large gain in inverting amplifier 4 whose input is connected to the emitter, or output electrode, of the transistor, and whose output is connected to the base via a resistor 5. The voltage output s (t) is obtained at the emitter of transistor 1. An output load 6 is also connected to the emitter of transistor 1.

p0013The signal to be amplified e (t) is referenced to ground; the biasing means 3 and the output load 6 are also referenced to ground.

p0014The polarization means 3 comprise a generator 7 variable bias voltage in increments of E! .DELTA.V From a fixed value + .DELTA.V, and up to a maximum value + N (.DELTA.V), and means 8 for controlling the generator 7 for a change^±.DELTA.V Of the bias voltage E as a result of a corresponding change in ^± .DELTA.V Of the output voltage s (t), so as to maintain at any moment the difference between the output voltage s (t) and the bias voltage E, and hence the collector-emitter voltage V_THIS of transistor 1, at most equal to .DELTA.V.

p0015The means 8 comprise a set of N-1 comparators 9_not for comparing the output voltage s (t) to each of N-1 n voltages (.DELTA.V) (n varying from 1 to N-1).

p0016Figure 2 shows an example of input voltage to be amplified e (t), a positive sign, and the bias voltage E and the amplified output voltage s (t). Initially the output voltage s (t) is zero, the bias voltage E is equal to the fixed voltage .DELTA.V and the transistor 1 is rendered conductive. After a time interval, depending on the shape of the signal e (t), the output voltage s (t) becomes equal to .DELTA.V. At this time, the output voltage becomes equal to the bias voltage E, the means 8 controls the addition of an AV voltage level at the bias voltage E, carrying the voltage to the collector of transistor 2 .DELTA.V. The output voltage s (t) then being equal to .DELTA.V, the difference voltage V_THIS between collector and emitter of the transistor 1 is at most equal to .DELTA.V. Then the output voltage s (t) increases to 2 and AV at the time the means 8 controls the addition of a new level .DELTA.V to the bias voltage E, bringing the voltage at the collector 3 AV. This process continues until the signal e (t) increases, the maximum possible value for E is N (Δ V). After the maximum, when the voltage decreases, the means 8 are used to subtract the .DELTA.V voltage steps. Thus, we see in Figure 2 that at no time difference between the output voltage s (t) and bias voltage E exceeds .DELTA.V. This therefore guarantees the operation of the transistor in its safe operating area.

p0017The amplifier shown in Figure 3 has two transistors type class B, 10 and 11, the NPN example. The base or control electrode of these two transistors is connected to the output of an amplifier 12 to very high gain whose input receives both the signal to be amplified e (t), via a resistor 13, of secondly a signal against feedback via a resistor 14. The signal to be amplified e (t) in this case may be an AC signal. Against the feedback signal is either the output current i (t) or the voltage v_s(T) obtained at the output of a voltage divider 15 which receives as input the output voltage s (t).

p0018The emitter of transistor 10 and the collector of transistor 11, connected together, constitute the common output electrode of which is obtained the output voltage s (t) and to which is connected an output load 16.

p0019A bias voltage E is applied to the collector of transistor 10. The bias voltage E supplied from a generator 17 varies gradually in steps of ^± .DELTA.V, From a fixed value Δ + V and up to a maximum value (N + 1) (.DELTA.V). The generator 17 comprises for this a DC voltage source E₀Providing a voltage + V Δ, fixedly connected to the collector of transistor 10 and connectable to a set of N voltage sources E₁ to EN, each providing a voltage + V Δ and connectable together in series.

p0020Source E₀ has its positive pole connected to the reference voltage (or ground) and its negative pole connected to the positive pole of the source E₁ which itself has its connectable negative pole to the positive pole of the source E₂By means of a switch C₁, And so on until the source whose negative pole is connectable by means of a switch C_NOT to the bias electrode of the transistor 10.

p0021Moreover a diode D_not is connected in parallel with the source set in switch C_not (N varying from 1 to N), the diode D₁ having its anode connected to the positive pole of the source E₁ and its cathode connected to the positive pole of the source E2, and so on until the DN diode which has its anode connected to the positive pole of the source and its cathode connected to the bias electrode of the transistor 10.

p0022The connection or disconnection of sources E _not is controlled by a set 18 of N comparat ors for comparing the output voltage s (t) N voltages: Δ V 2 (.DELTA.V), ..., N (Δ V) and providing N control signals S₁, S₂, ..., S_NOT which are applied respectively to control inputs of the switches C₁, _C29 ... C_NOT.

p0023Similarly, a bias voltage E is applied to the transistor 11. The emitter bias voltage E ', provided by a generator 19 varies gradually in steps of ^± .DELTA.V, From a fixed value -ΔV and to a value - (N + 1) .DELTA.V. The generator 19 comprises for this a DC voltage source E '₀Providing a voltage -Δ V, fixedly connected to the emitter of the transistor 11 and connectable to a set of N voltage sources E '_l E '_not, Each providing a voltage - .DELTA.V and connectable together in série.- The generator 19 also includes, as generator 17, N switches C 'and N diodes D'_not, And all sources commutating diodes is mounted such in the generator 17, however respecting the polarity change.

p0024The connection or disconnection of sources E '_not is controlled by a set 20 of N comparators for comparing the output voltage s (t) N voltages: - .DELTA.V, -2 (.DELTA.V), ..., - N (.DELTA.V) and providing N control signals S '₁, S '₂..., S '_NOT which are applied to control inputs of the switches C_'1C_'2, .._., C '_NOT.

p0025The switches C and C '_not are realized by means of transistors operating in switching mode (open or closed) whose performance is very close to 1.

p0026Moreover, damped two inductors 21 and 22 are respectively interposed between the output of the generators 17 and 19 and the bias electrode of the transistors 10 and 11, so as to eliminate the instantaneous variations of the bias voltages E and E 'due to the edges straight when connecting or disconnecting the DC voltage sources.

p0027There is shown in Figure 4, by way of example, the shape of the output voltage s (t) and bias voltages E and E 'for a zero input voltage (t) sinusoidal.

p0028-When Positive alternations, the transistor 10 is conductive and transistor 11 is off, the collector-emitter voltage of the transistor 10 always remaining less than or equal to AV whatever the amplitude of the output voltage. The output voltage is limited by the maximum value of the collector-emitter voltage V_CEBmax that can withstand the transistor 11 blocked .. The output voltage s (t) maximum, corresponding to a bias voltage equal to E (N + 1) .DELTA.V is equal to N (.DELTA.V). The same phenomena occur during the negative half-waves by reversing the role of the transistors 10 and 11.

p0029The alternative embodiment shown in Figure 5 differs from that shown in Figure 3 by the embodiment of the bias voltage generator.

p0030The two sets of DC sources, positive: E₁ to E_NOTAnd negative: E '₁ E '_NOT are replaced by a single set 25 of DC voltage source E "₁ E "N each providing a DC voltage absolute value .DELTA.V and connectable together in series, according to two possible polarities. In contrast to Figure 3, the power amplifier is mounted" floating ". The source E₀ providing fixed voltage + .DELTA.V has its positive pole connected to the collector of transistor 10 and the source E '₀ providing the fixed voltage - .DELTA.V has its negative pole connected to the emitter of the transistor 11.

p0031The negative pole of the source E₀ and the positive pole of the source E '₀ are interconnected and this common point is connected firstly to the assembly 25 sources E "_not via a damped inductor 26, on the other hand to one input of an amplifier 12 'for controlling the transistors 10 and 11, for low gain, the other input of the amplifier 12' is connected via an optocoupler 12 " , to the output of the amplifier 12 high gain which receives the input signal e (t).

p0032Each source E " _notcan be connected to the next either by means of two switches C_1n and C_2n if this connection should be determined in a positive polarity or by means of two switches C '_ln and C '_2n if this connection must be of a negative polarity.

p0033Switches C_1n, C '_1nC_2n and C '_2n are mounted in bridge form. The point common to switches C_1n and C '_2n is connected to the common point of switches C '₁,_n-1 and C_{2, n-1}The common point of the switches C₁₁ and C '₂₁ (Corresponding to the value n equal to 1) being connected to the point common to the fixed power source E₀ summer'₀. The point common to switches_C'ln and _C2n is connected to the common point of switches C_{1, n + 1} and C '_{2, n + 1}The common point of the switches C '_1N and C_2N (Corresponding to the value n equal to N) being grounded. Furthermore, the point common to the switches C_1n and C '_ln is connected to the positive pole of the voltage source E "n and the point common to the switches C_2n and C '_2n is connected to the negative pole of the voltage source E "n.

p0034These switches are actuated as follows.

p0035When all switches C_1nand-C '_1nare open, and when all switches C_2n and C '_2n are closed, the voltage supplied by the assembly 25 is zero.

p0036If, starting from this position, switches C is closed₁₁ and C₂₁ (These being controlled by the signal S₁), The voltage supplied by all 25 changes from 0 to + .DELTA.V, and so on up to N + (.DELTA.V) when closing the switches C_1N and C_2N (These being controlled by the signal S_NOT). The process is the same in reverse order to disconnect the voltage sources E "_not and gradually move from N + (Δ) V 0.

p0037The process is also the same to go from 0 to N (Δ V), then ^-NOT(.DELTA.V) To ⁰_, except that it is the switches C '_1n and C '_2n which are then actuated (these switches being controlled by the signal S '_not).

p0038All these switches are in practice realized by means of transistors used in switching mode.

p0039Is shown in Figure 6 the shape of the output voltage s (t) to an input voltage e (t) sinusoidal and the appearance of bias voltages E and E 'of the transistors 10 and 11. In during the positive polarity, the transistor 10 is conductive while the transistor 11 is blocked. When the output voltage s (t) increases, the bias voltage E of the transistor 10 increases in steps of .DELTA.V following the process described above. Each switching a positive supply, the bias voltage E 'of the transistor 11 also increases, with an offset of 2 (.DELTA.V) since the bias electrode of the transistor 11 is connected to the controllable power supplies by the fixed point common to power E₀ summer'₀. It is the same in the negative polarity, the transistor 11 being blocked while the transistor 10 is conductive. According to this embodiment, the collector-emitter voltage of the transistors 10 and 11 is blocked is at most equal to 2 (Δ V).

p0040This arrangement thus provides an output voltage that is not limited by the voltage V_CEBMaxtransistors. Thus, with the number of required AV power supplies, this circuit provides an output voltage as high as desired.

p0041In the variant embodiment shown in Figure 7, there is provided a point mid transformer 30 whose primary winding is connected on one side to the collector of transistor 10, on the other hand to the collector of transistor 11 (the transmitter transistors 10 and 11 being set at a reference voltage, or ground), and whose secondary winding is connected to the output load 16. the middle of the primary winding point is connected via a damped inductor 31 to a generator 32 of bias voltage comprising a single fixed source of supply and a single set of supply voltage sources controllable by a set of comparators 33 which receives the signals obtained at the collector of transistors 10 and 11.

p0042The control amplifier 12 and the output load 16 are referenced to ground and the presence of the transformer provides an output voltage as high as desired. However, this arrangement does not achieve the output signals of asymmetrical or symmetrical shape with an "offset". In addition, the bias voltage of the transistors is limited to half of the maximum collector-emitter voltage thereof (due to the transformer at the midpoint).

p0043The embodiment shown in Figure 8 is similar to that shown in Figure 3, but differs therefrom by the fact that the collector of transistor 10 and to the emitter of transistor 11 are connected only fixed voltage source -E_O summer'₀The two sets 17 and 19 of controllable voltage sources (E, D_notC_not) summer'_not, D ', C'_not) Being arranged at the output of the transistors, two switches C and C '(like switches controlled respectively C₁ and C '₁) Then being provided to connect the diodes D₁ and D'₁ output transistors.

p0044Unlike the embodiments described above, but to get the same effect, namely maintaining the collector-emitter voltage of the transistors 10 and 11 leads, or less .DELTA.V in absolute value, the controllable power supplies + .DELTA.V are then controlled during the positive half of the signal e (t) and the controllable power - .DELTA.V are controlled during negative alternations.

p0045In this arrangement, the power amplifier is controlled from the ground (so no floating point) and the output load is floating. The output voltage is limited to the maximum collector-emitter voltage of the switching transistors C, C ', C₁, C '₁).

p0046Both sets 17 and 19 of controllable voltage sources can be replaced, as in the case of Figure 3, by a single set of voltage sources connectable together along two different polarities. In this case the output voltage is not limited.

p0047As in the case of Figure 7, the assembly of Figure 9 comprises a single set 40 of DC sources and one set 41 of connection control comparators or disconnection of these sources.

p0048This is made posslble by the presence of two transistors 42 and 43 operating in switching mode, one being conductive when the other is blocked, and vice versa for applying the bias voltage E delivered from the assembly 40 sources feed either as such, or reversed, to the power amplifier. The voltage E is applied to the collector of the transistors 42 and 43. The emitter of the transistors 42 and 43 is respectively connected to the collector of the transistors 10 and 11, the emitter of the transistors 10 and 11 being connected to ground.

p0049On the base of the transistors 42 and 43 are respectively applied the signals w and w₂ provided by a comparator 90 which detects the change in direction of current in the output load 16.

p0050The output load 16 is arranged between the collector of transistor 10 and the collector of transistor 11. In series with the output load and in parallel therewith are respectively disposed current sensors, 44, and voltage 45, providing respectively the current-reaction against i_s(T) and the voltage feedback against v_s(T).

p0051In this arrangement, the power amplifier is controlled with respect to ground, the output load is floating, and the output voltage is limited to the maximum collector-emitter voltage of the power amplifier.

p0052Figure 10 shows a further embodiment of the invention applying, for example, to an amplifier with only one transistor 50 of the type class B.

p0053As before, the base or control electrode of this transistor is connected to the output of an amplifier 51 to very high gain whose input receives both the signal to be amplified e (t), via a resistor 52 on the other hand against a signal feedback via a resistor 53. the feedback signal against is either the output current i (t) or the voltage v_s(T) obtained at the terminals of a resistor 54 disposed at the output of the transistor.

p0054The amplifier 51 is powered; the power of this amplifier is at least equal to the maximum voltage so that it is desired and depends on the number of controllable power supplies. This also applies to the speaker drive amplifiers in previous fixtures.

p0055An output load 55 is connected to the transmitter, or output electrode of the transistor 50.

p0056The collector or bias electrode of the transistor 50 is applied a bias voltage E supplied from a generator 56 of variable bias voltage in steps of ^± .DELTA.V From a fixed value Δ V, and up to a maximum value equal in this case to 3N (.DELTA.V), but more generally to MN (.DELTA.V) (with M integer) instead of N ( .DELTA.V) as was the case with the previous arrangements, and this without increase of prohibitively the number of elementary sources voltage .DELTA.V compared with previous arrangements.

p0057For this, the generator 56 includes a first module 56₁ consisting of a DC voltage source E₀ providing a voltage .DELTA.V, connected to the collector of transistor 50 and connectable in series to a set of N-1 voltage sources E₁ to E_N-1 themselves be connected together in series and each providing a voltage level .DELTA.V.

p0058The generator 56 also comprises a second module 56₂ consisting of a DC voltage source connectable in series to the sources E₀ to E_N-1 and providing a voltage level equal to N (.DELTA.V), and a third module 56₃ consisting of a DC voltage source E_{N + 1} connectable in series to the source E₀ to EN and providing a voltage level equal to 2N (.DELTA.V).

p0059Sources E and EN_{N + 1} are connectable via switches C_NOT and C_{N + 1}; D diodes_NOT and D_{N + 1} are planned to bypass these sources when not in use.

p0060As in the previous assemblies, the switches C₁ -C_N-1Allowing commissioning source E₁ to E_N-1 Module 56₁ are controlled by a set of comparators 57₁ to compare the amplified output voltage to N-1 threshold voltages S₁ to S_N-1 initially .DELTA.V respectively equal to, 2 (.DELTA.V), ..., (N-1) .DELTA.V and stored in a memory comparison thresholds 58. The switches C₁ -C_N-1 are also controlled, and the switch C_NOT, By a comparator 57₂ to compare the amplified output voltage s (t) to .the voltage N (.DELTA.V). When the output voltage s (t) becomes equal to N (.DELTA.V), the switch C_NOT is closed and the switches C₁ -C_N-1 are simultaneously opened, bringing the bias voltage to a value (N + 1) .DELTA.V. In addition, the value N (.DELTA.V) is added to the initial values ​​of the comparison thresholds S₁ to S_N-1.

p0061Switches C₁ -C_NOT are also controlled, and the switch C_NOT, By a comparator 57₃ to compare the amplified output voltage s (t) to the voltage (N + I) ΔV.Lorsque the output voltage s (t) becomes equal to (N + 1) .DELTA.V, switch C_{N + 1} is closed, and the switches C₁ -C_NOT are simultaneously opened, bringing the bias voltage to a value (2N + 1) .DELTA.V. In addition, the N value (Δ V) is again added to the comparison thresholds S values₀ to S_N-1.

p006211 illustrates more concretely the operation of the amplifier shown in Figure 10.

p0063As the output signal s (t) of the class B amplifier does not reach an amplitude equal to N (.DELTA.V) (point A), the two power supplies addi- _ment_areas In summer_{N + 1} are disconnected, and the current passes through the diodes.

p0064When the signal s (t) reaches point A, all power E₁ to E_N-1 are connected, the comparator 57₂ closes the switch C_NOT e supply_NOT equal to N (.DELTA.V), disconnect all power E₁ to E_N-1 and adds to the preceding comparison threshold values ​​the value N (.DELTA.V).

p0065When the signal s (t) is (N + 1) .DELTA.V, the comparator of set 57₁ whose threshold is (N + 1) .DELTA.V (previously .DELTA.V) activates a .DELTA.V feeding the assembly 56₁.

p0066The process continues until 2N (.DELTA.V) (point B) where as before the comparator 57₃ performs three functions: closing the power E_{N + 1} equal to 2N (.DELTA.V), disconnect all power E₁ to E_N-1 of the assembly 56₁ and addition of N (.DELTA.V) for comparison threshold values.

p0067When the signal to be amplified decreases, the reverse operations are performed.

p0068As in the embodiment previously described in relation with Figure 8, additional power supplies can be brought into output of the amplifier.