Circuit for preventing flicker.

This invention relates to a circuit for preventing flicker occurring in a television apparatus on conversion of a field signal to a frame signal.

More particularly the invention relates to a circuit of the above kind which improves the response of a feedback - clamping loop and can prevent occurrence of undesirable sagging during the vertical synchronizing period. This invention relates also to a flicker preventive circuit which can reliably prevent appearance of flicker without being adversely affected by the temperature dependencies and secular variations of various parts of the field signal-frame signal --conversion system and without requiring severe adjustments of such parts.

In television, so-called interlaced scanning is employed in which a picture is scanned with horizontal scanning lines skipped at a rate of one or more lines so as to minimize the influence of flicker perceptible to the eye. Most widely employed in this field is 2:1 interlaced scanning in which alternate horizontal scanning lines are skipped during scanning of an even field and an odd field. According to 2:1 interlaced scanning, a rough picture called a field is produced by one vertical scanning, and two fields are superposed to provide a complete picture called a frame. The field repetition rate is 60 fields per second according to, for example, the NTSC standards, and, in this case, the frame repetition rate is 30 frames per second. One frame is completed generally with 525 horizontal scanning lines. The point of beginning of horizontal scanning of an odd field is displaced from that of an even field by 1/2 of one horizontal scanning period or 0.5H.

Figure 1 of the drawings shows a typical example of a composite video signal (a frame signal) representing a frame, and including a field signal 1 representing an odd field in the composite video signal (the frame signal), and a field signal 2 representing an even field in the composite video signal (the frame signal). Reference numerals 3, 4, 5, 6, 7, 8 and 9 designate a vertical blanking period, front equalizing pulses, a vertical synchronizing signal, serrating pulses, back equalizing pulses, a horizontal synchronizing signal, and a video signal, respectively. A portion A in Figure 1 is shown to an enlarged scale in Figure 2 of the drawings, in which reference numerals 10, 11, 12, 13 and 14 designate a horizontal blanking period, a front porch, a back porch, a pedestal level, and a sync tip level, respectively.

In recording a video signal on a magnetic tape, a magnetic disk or any other recording medium, it is customary that a signal of one field is allotted to one track or a signal of one frame is allotted to one track. Also, the one-field/one-track recording method is classified into the so-called one-frame/two track recording method in which an odd field and an even field constituting a frame are sequentially recorded on two adjacent tracks respectively, and the so-called one-field recording method in which only one of an odd field and an even field only is recorded on one track.

In the case of reproduction of a record recorded according to the one-field recording method, the so-called field/frame conversion mode is most frequently employed in which, utilizing the strong vertical correlation of horizontal scanning lines in a video signal, the same track is scanned twice to reproduce a frame signal from a field signal of one kind. This field/frame conversion mode is intended principally to improve the recording density so as to enable long-time recording in the case of a movie recording and to increase the number of pictures in the case of a still recording. However, in the case of conversion from a field signal to a frame signal, the effect of interlaced scanning cannot be realized by merely repeatedly reproducing the same field signal twice. This is because mere repetition of reproduction of the same field signal twice cannot provide the relative time lag of 0.5H although this relative time lag of 0.5H is actually required between the odd field 1 and the even field 2 in Figure 1 for the purpose of attaining the effect of interlaced scanning, as will be readily seen from the relation between the vertical synchronizing signal 5 and the horizontal synchronizing signal 8 and the video signal 9 in the individual lines.

With a view to obtaining the effect of interlaced scanning, it is a common practice to attain conversion from a field signal to a frame signal in a manner illustrated in Figure 3 of the drawings where the same field signal is repeatedly reproduced on line 17 and passed or not passed through a 0.5H delay line 15, under the control of an analog switch 16 which is actuated to alternately select the field signal or the 0.5H delayed field signal on line 18 at a time interval of one vertical scanning period (IV), thereby attaining the desired conversion from a field signal to a frame signal.

However, when the arrangement shown in Figure 3 is employed directly, there will occur a relative time lag of 0.5H between the vertical synchronizing signals in successive field signals.

To deal with such a trouble, a method as, for example, shown in Figure 4 is proposed for selectively changing between the contacts c and d of the analog switch 16. It will be seen in Figure 4 that, in the period allotted for direct feed of the field signal on line 17, the portion 19 between the front equalizing pulse and the back equalizing pulse is-used for feed of the 0.5H delayed field signal on-line 18.

However, due to the fact that the provision of the delay line 15 not only gives rise to a delay in transmission time but also leads to considerable attenuation of the signal, and also due to the fact that the offset voltage of the analog switch 16 differs between the two contacts c and d thereof, the converted frame signal includes a signal level difference and a pedestal level difference between the even and odd fields, resulting in appearance of flicker on the reproduced picture.

A circuit as shown in Figure 5 of the drawings has heretofore been employed so as to prevent appearance of such flicker. Referring to Figure 5, this flicker preventing circuit includes an amplifier 2₀, clamping circuits 21, 22, a gain-adjusting potentiometer VR₁ and a clamp-level adjusting potentiometer VR₂ associated with the combination of the 0.5H delay line 15 and the analog switch 16 of Figure 3. The gain of the amplifier 20 is adjusted by the gain-adjusting potentiometer VR₁ so that the converted frames signal has the same signal level in each field, and the clamping level is adjusted by the clamping-level adjusting potentiometer VR₂ so that the converted frame signal has the same pedestal level in each field. The above adjustment is usually made manually by the operator. Therefore, the circuit of Figure 5 is unfit to meet the severe adjustment requirement of -40 dB or more demanded for preventing flicker, and is also unfit for mass production. Also, because the 0.5H delay line 15, analog switch 16, amplifier 20 and clamping circuits 21, 22 tend to undergo secular variations in addition to their inherent temperature dependencies, it has been impossible to completely eliminate the appearance of flicker attributable to the temperature dependences And secular variations of those parts, even when the appearance of flicker has been eliminated temporarily by adjustment of the potentiometers VR₁ and VR₂.

A flicker preventing circuit which can automatically prevent the appearance of flicker in field signal/ frame signal conversion as described above, regardless of the temperature dependencies and secular variations of its components, is described in Japanese Patent Application No. 58-189202, and will now be described with reference to Figures 6 and 7 of the drawings, in which Figure 6 is a circuit diagram of the automatic flicker preventing circuit, and Figure 7 illustrates the operation of various parts of the circuit of Figure 6.

Referring to Figure 6, the automatic flicker preventing circuit includes a 0.5H delay line 15, a field-selecting analog switch 16, and an AGC loop 23 and a feedback-clamping loop 30. The AGC loop 23 acts to maintain constant the sync tip level (14 in Figure 2) and includes an automatic gain controller 24, the field-selecting analog switch 16, two input-selecting switches 25, 26, two peak detectors 27, 28, and a differential amplifier 29.

The analog switch 16 presents a frame signal shown in Figure 7(a) as its output, and the input-selecting switches 25 and 26 are turned on/off as shown in Figures 7(c) and 7(d) respectively under control of a switch control pulse signal 35, which is shown in Figure 7(b) and selectively passed through an inverter 36. Consequently, the frame signal is applied to the peak detectors 27 and 28 at a time interval of IV as shown in Figures 7(e) and 7(f) respectively. Thus, the peak value of, for example, the even field signal detected by one of the peak detectors, e.g. the peak detector 27, and the peak value of, for example, the odd field signal detected by the other peak detector 28, are applied to the differential amplifier 29, and the output signal 29a of the differential amplifier 29 indicative of the difference is applied to control the automatic gain controller 24 so as to attain coincidence of the peak values of the even and odd fields. When the peak values are the same and constant, the sync level and the signal level are maintained constant. The time constant selected is such that the AGC loop 23 responds to at least the unit field so that the signal level of a succeeding field signal becomes equal to that of a preceding field signal.

On the other hand, the feedback-clamping loop 3Q acts to maintain constant the pedestal level (13 in Figure 2) and includes a sampling switch 31, an integrating circuit 32 and two clamping circuits ₃3, 34, besides the field selecting switch 16, Figure 7(g) shows the sampling timing of the sampling switch 31. The sampling switch 31 samples the pedestal level in each horizontal scanning period, and the integrating circuit 32 holds the sampled value and compares it with a reference value Vref₁. The resultant difference signal 32a is applied from the integrating circuit 32 to the clamping circuits 33 and 34 each of which generates an output signal providing the pedestal level, so as to attain coincidence of the pedestal levels in the individual horizontal scanning periods. The time constant of this feedback-clamping loop 30 is selected to be lass than several H at the most so that the clamping level can be stabilized within the period of 1_H to 2H after change-over between the fields. Thus, flicker can be eliminated as early as possible even in the presence of variations in the characteristics of the two clamping circuits 33 and 34. Two capacitors 37 and 38 shown in Figure 6 are provided for the purpose of DC cut-off.

In the flicker preventing circuit described above, the difference between the peak values (the sync tip levels) of an even field and an odd field is detected, and an automatic gain controller is controlled on the basis of the detected difference signal thereby maintaining constant the signal level in each of the fields. Also, according to the above circuit, the pedestal level is sampled at a time interval of one horizontal scanning period (lH) to find the difference between the detected pedestal level and a reference value, and the clamping level is controlled on the basis of the detected difference signal thereby maintaining constant the pedestal level in each of the horizontal scanning periods. 'Therefore, temperature dependencies and secular variations that may be present in the components of the field signal - frame signal conversion circuit would not exert any substantial influence on the operation of the flicker preventing circuit, and the appearnce of flicker is minimized. Further, the flicker preventing circuit is suitable for mass-production since the signal level and the pedestal level can be automatically adjusted.

Although the above described flicker preventing circuit is advantageous in various aspects, there are still two points which can be improved.

In the first place, with the feedback-clamping loop in the form shown in Figure 6, the pedestal level cannot be sampled in the vertical scanning period when a sampling pulse signal produced in synchronism with HD pulses derived from a synchronizing signal generator (SSG) is used for turning on/off the sampling switch 31. Accordingly, instead of making sampling of the pedestal level in the vertical scanning period, the voltage holding time of the integrating circuit 32 must be extended to about 4H so as to deal with the above situation. However, this leads to a problem of occurrence of a sag in the vertical scanning period and leads also to a problem of delayed response of the feedback-clamping loop. Further, there is the disadvantage that a synchronizing signal generator (SSG) and a sampling cancelling circuit are additionally required.

Secondly, the holding time of at least IV required for each of the peak detectors 27 and 28 has limited the response speed of the AGC loop, since these peak detectors 27 and 28 receive their input signals at a time interval of 1V only. Unless the AGC loop can respond sufficiently quickly, the AGC loop may not properly function in response to, for example, on/off of the power source or on/off of the input signal, On the other hand, the peak detectors 27 and 28 are provided independently of each other for detecting the peak values of the direct and delayed field signals respectively. Accordingly, when the temperature dependence of one of the peak detectors differs from that of the other, it leads to appearance of flicker although the flicker may not be very appreciable.

According to one aspect of the present invention there is provided a circuit for preventing flicker occurring on conversion of a field signal to a frame signal, including delay means operative to delay a field signal supplied thereto by one half of a horizontal scanning period; a switching means operative to pass alternately the field signal directly or a delayed field signal from the delay means, the switching means being operated at a frequency of one vertical scanning period, and the output of the switching means being a frame signal; a feedback clamping loop comprising a sample and hold means sampling the pedestal level of the frame signal appearing at the output of the switching means, a clamping voltage generating means operative to compare the output signal from the sample and hold means with a reference value and generate a voltage signal proportional to the difference therebetween, and two clamping means connected to the direct and delayed field signal supply lines to the switching means respectively and controlled by the output signal from the clamping voltage generating means to maintain constant the pedestal level of the direct and delayed field signals, characterised by a synchronizing signal separating means operative to separate a synchronizing signal from the frame signal appearing at the output of the switching means, and a sampling pulse generating means operative in response to the application of a separated synchronizing signal to generate a sampling pulse signal synchronous with the change points from the sync tip level to the pedestal level and having a:pulse width equal to or smaller than that of the serrating pulses in the frame signal, the sampling pulse signal being applied to the sample and hold means in the feedback clamping loop.

According to another aspect of the present invention there is provided a circuit for preventing flicker occurring on conversion of a field signal to a frame signal, including delay means operative to delay a field signal supplied thereto by one half of a horizontal scanning period; a switching means operative to pass alternately the field signal directly or a delayed field signal from the delay means, the switching means being operated at a frequency of one vertical scanning period, and the output of the switching means being a frame signal; a feedback clamping loop comprising a sample and hold means sampling the pedestal level of the frame signal appearing at the output of the switching means, a clamping voltage generating means operative to compare the output signal from the sample and hold means with a reference value and generate a voltage signal proportional to the difference therebetween, and two clamping means connected to the direct and delayed field signal supply lines to the switching means respectively and controlled by the output signal from - the clamping voltage generating means to maintain constant the pedestal level of the direct and delayed field signals, characterised by an automatic gain control loop comprising an automatic gain controller operative to amplify the frame signal appearing at the output of the switching means, a peak detecting means operative to-detect the peak value of the amplified frame signal in each horizontal blanking period, and a gain-control voltage generating means operative to compare the output signal of the peak detecting means with a reference value and generate a Voltage signal proportional to the difference therebetween, the voltage signal being applied to the automatic gain controller to maintain constant the sync tip level of the amplified frame signal.

According to a further aspect of the present invention there is provided a circuit for preventing flicker occurring on conversion of a field signal to a frame signal, including delay means operative to delay a field signal supplied thereto by one half of a horizontal scanning period; a switching means operative to pass alternately the field signal directly or a delayed field signal from the delay means, the switching means being operated at a frequency of one vertical scanning period, and the output of the switching means being a frame signal; a feedback clamping loop comprising a sample and hold means sampling the pedestal level of the frame signal appearing at the output of the switching means, a clamping voltage generating means operative to compare the output signal from the sample -and hold means with a reference value and generate a voltage signal proportional to the difference therebetween, and two clamping means connected to the direct and delayed field signal supply lines to the switching means respectively and controlled by the output signal from the clamping voltage generating means to maintain constant the pedestal level of the direct and delayed field signals, characterised by an automatic gain control loop comprising an automatic gain controller connected in either the direct field signal line or delayed field signal line to the switching means, a first peak detecting means connected to the direct field signal line at the input to the switching means and operative to detect the peak value of the direct field signal in each horizontal blanking period, a second peak detecting means connected to the delayed-field signal line at the input to the switching means and operative to detect the peak value of the delayed field signal in each horizontal blanking period, and a differential amplifier operative to generate an output signal indicative of the difference between the peak values detected by the first and second peak detecting means, which output signal is applied to the automatic gain controller to maintain the sync tip level of the controlled signal constant.

This invention will now be described by way of example with reference to the drawings, in which:- <ul id="ul0001" list-style="none"><li>Figure 1 illustrates a frame signal;</li><li>Figure 2 shows an enlarged detail view of a portion A of the signal shown in Figure 1;</li><li>Figure 3 is a circuit diagram illustrating a basic principle of conversion of a field signal to a frame signal;</li><li>Figure 4 illustrates the operation of the circuit shown in Figure 3;</li><li>Figure 5 is a circuit diagram of a known flicker preventing circuit;</li><li>Figure 6 is a circuit diagram of a prior proposal for an automatic flicker preventing circuit ;</li><li>Figure 7 illustrates the operation of various parts of the circuit shown in Figure 6;</li><li>Figure 8 is a circuit diagram of an embodiment of this invention;</li><li>-Figure 9 illustrates the operation of various parts of the circuit shown in Figure 8;</li><li>Figure 10 is a circuit diagram of another embodiment of this invention;</li><li>Figure 11 is a circuit diagram of another embodiment of this invention;</li><li>Figure 12 illustrates the operation of various parts of the circuit shown in Figure 11;</li><li>Figure 13 is a circuit diagram of another ,embodiment of this invention;</li><li>Figure 14 illustrates the operation of the circuit shown in Figure 13; and</li><li>Figure 15 is a circuit diagram of part of a further embodiment of this invention,</li><li>Figures 1 to 7 of the drawings have been described above and will not therefore be described again.</li></ul>

The same reference numerals have been used for corresponding parts throughout the drawings.

Referring to Figure 8, the embodiment of the present invention here shown comprises a 0.5H delay line 15, a change-over switch 16, an automatic gain controller 24, clamping circuits 33 and 34, DC cut-off capacitors 37 and 38, impedance-converting emitter follower circuits 39 to 43, an AGC loop 44, and a feedback-clamping loop 45. Reference numerals 17 and 18 designate a direct field signal and a 0.5H delayed field signal respectively.

The feedback-clamping loop 45 includes a synchronizing signal,separating means 50 operative to separate a synchronizing signal 50a from a frame signal 46 appearing from the switch 16, a sampling pulse generating means 52 operative to produce a sampling pulse signal 52a on the basis of the separated synchronizing signal 50a, a sample and hold means 53 operative to sample the pedestal level of the frame signal 46 in response to the sampling pulse signal 52a, a clamping voltage generating means 54 operative to compare the output signal 53a of the sample and hold means 53 With a reference value Vref₁ And generate a voltage signal 54a proportional to the difference therebetween, and two clamping circuits 33 and 34 connected to the delayed and direct field signal lines 18 and 17, respectively.

The waveform of the separated synchronizing signal 50a is shown in Figure 9(a), and that of the sampling pulse signal 52a is shown in Figure 9(b). It will be seen in Figure 9(b) that the sampling pulse signal 52a is synchronous with the rising edges of the pulses of the synchronizing signal 50a, that is, synchronous with the change points from the sync tip level to the pedestal level of the signal 50a, and the pulse width of the signal 52a is equal to or smaller than that of the serrating pulses 6 appearing in the vertical synchronizing period 5 (Figure 1). Therefore, the sample and hold means 53 can detect the pedestal level during the entire period including the vertical blanking period 3 (Figure 1) of the frame signal 46.

The clamping voltage generating means 54 compares the sampled pedestal level with the reference value Vref₁ and applies its output.signal 54a indicative of the difference therebetween to the clamping means 33 and 34 so that the direct and delayed field signals 17 and 18 have the same And constant pedestal level, Therefore, the feedback-clamping loop 45 can clamp the pedestal level during the entire period including the vertical blanking period. Also, since the sampling interval is not longer than 1H, the required voltage holding time of the sample and hold means 53 is as short as only about lH, so that the feedback-clamping loop 45 can respond quickly.

In the embodiment shown in Figure 8, the sampling pulse signal 52a for sampling the pedestal level is produced on the basis of the synchronizing signal 50a separated from the frame signal 46. By producing the sampling pulse signal synchronous with the rising edges of the synchronizing signal, that is, the change points from the sync tip level to the pedestal level, the pedestal level can be sampled even in the vertical synchronizing period. Therefore, the feedback-clamping on the basis of the sampled pedestal level eliminates an undesirable sag appearing in the vertical synchronizing period. Further, due to the fact that the voltage holding time of the sample and hold means 53 is short or only about 1H, the clamping operation is done with a good response performance regardless of on/off of the power source or position of the switch 16. Furthermore, no special unit such as a synchronizing signal generator (SSG) for producing horizontal synchronizing pulses (HD pulses) is necessary.

The structure and function of the AGC loop 44 employed in the embodiment shown in Figure 8 will now be described. This AGC loop 44 includes the automatic gain controller 24 operative to amplify the frame signal 46 applied-from the switch 16, a sample and hold means 48 operative to sample the peak, that is, the sync tip level of the amplified frame signal 47, a gain-control voltage generating means 49 operative to compare the output signal 48a of the sample and hold means 48 with a reference value Vref₂ and generate a voltage signal 49a proportional to the difference therebetween, the synchronizing signal separating means 50 operating to separate-the synchronizing signal 50a from the frame signal 46, and a sampling pulse generating means 51 operative to produce a sampling pulse signal 51a on the basis of the separated synchconizing signal 50a. This sampling pulse signal 51a has a waveform as shown in Figure 9(c). It will be seen in Figure 9(c) that the sampling pulse signal 51a is synchronous with the falling edges, that is, the change points from the pedestal level to the sync tip level of the synchronizing signal 50a, and its pulse width is equal to or smaller than that of the serrations of the sync level or equalizing pulses in the equalizing periods 4 and 7 (Figure 1). Therefore, the sample and hold means 48 can detect the sync tip level during the entire period including the vertical blanking period 3(Figure 1) of the amplified frame signal 47. Thus, the sample and hold means 48 operates as a peak detector. The gain-control voltage generating means 49 compares the output signal 48a of the sample and hold means 48 with the reference value Vref₂, and applies a voltage signal 49a indicative of the difference therebetween to the automatic gain controller 24, so that the sync tip level of the amplified frame signal 47 can be maintained constant. Therefore, the required voltage holding time of the sample and hold means 48 is short or only about 1H, so that the AGC loop 44 can respond very quickly. Thus, the AGC loop 44 makes its AGC operation immediately in response to on/off of the power source or operation of the switch 16.

The AGC loop 23 in the known flicker preventing circuit shown in Figure 6 includes two peak detectors 27 and 28, and a difference between the temperature dependencies of these two peak detectors 27 and 28 can result in the appearance of flicker. In contrast, the AGC loop 44 in ,n the circuit shown in Figure 8 includes only one peak detector, Thus, no flicker attributable to the temperature dependence of the single peak detector appears.

The embodiment of the invention shown-in Figure 10 is a modification of the embodiment shown in Figure 8 in that its AGC loop 55 only is slightly different from the AGC loop 44 shown in Figure .8. Referring to Figure 10, the AGC loop 55 includes a peak detector 56 combined with the automatic gain controller 24 and the gain-control voltage generating means 49. The sampling pulse generating means 51 shown in Figure 8 is eliminated. The peak detector 56 detects the peak value, that is, the sync tip level of the amplified frame signal 47. Thus, when the voltage holding time is selected to be about 1H, the AGC loop 55 can respond very quickly as in the case of the embodiment shown in Figure 8. Further, since only one peak detector 56 is provided for the peak detection, no flicker atributable to the temperature dependence of the single peak detector 56 appears.

In each of the AGC loops 44 and 55 shown in Figures 8 and 10 respectively, the frame signal 46 obtained by conversion of the direct and delayed field signals 17 and 18 by the switch 16 is amplified by the automatic gain controller 24, and the peak value (the sync tip level) of the amplified frame signal 47 is detected by the peak detecting circuit 48 or 56 to be compared with the reference value Vref₂. The automatic gain controller 24 is so controlled that the peak value of the amplified frame signal 47 can be maintaned constant. Therefore, only one peak detecting circuit suffices, and there is always an input applied thereto.

Since the input signal is always applied to the peak detecting circuit, the voltage holding time which is as short as about 1H, suffices, and the AGC loop can respond very quickly. Also, since only one peak detecting circuit is provided, no flicker attributable to the temperature dependence of the single peak detecting circuit appears.

The feedback-clamping loop 45 shown in each of Figures 8 and lO may be replaced by that 30 shown in Figure 6. In such a case, however, it is a general procedure that a sampling pulse signal is produced on the basis of HD pulses from a synchronizing signal generator (SSG) and is applied to the sampling switch 31. Therefore, it is normally impossible to sample the pedestal level during the vertical synchronzing period 5 (Figure 1), and it becomes necessary to extend the voltage holding time of the integrating circuit 32 to a considerably longer period of about 4H, From this aspect, the feedback-clamping loop 45 shown in each of Figures 8 and 10 is advantageous over the loop 30 shown in Figure 6 in that the capability of clamping of the pedestal level even in the vertical synchronizing period eliminates occurrence of an undesirable sag, and the quick response ensures immediate starting of the clamping operation in response to on/off of the power source or operation of the switch 16.

The flicker preventing circuit shown in Figure 11 is an improvement in the known circuit shown in Figure 6. The structure shown in Figure 11 is the same as that shown in Figure 6 except that two peak detectors 58 and 59 each having a voltage holding time of about 1H are disposed in a stage preceding the switch 16, and the clamped signal from the clamping circuits 33 and 34 is directly applied to the peak detectors 58 and 59 respectively to constitute an AGC loop 57. In Figure 11, emitter follower circuits 60 and 61 are provided for the purpose of impedance conversion.

The operation of the flicker preventing circuit shown in Figure 11 will now be described. The field signal 18 passed through the 0.5H delay line 15 is applied to one of the peak detectors, e.g. peak detector 58 (Figure 12(c)), and, at the same time, the direct field signal 17 is applied to the other peak detector 59 (Figure 12(a) ). The two peak detectors 58 and 59 detect the peak values, that is, the sync tip levels of the respective field signals at a time interval of 1H, and their output signals indicative of the detected sync tip levels (Figs. 12(d) and 12 (b) ) respectively are applied to the differential amplifier 29. The differential amplifier 29 applies its output signal 29a, proportional to the difference between the two inputs, to the automatic gain controller 24 to control the gain so that coincidence can be achieved between the sync tip levels of the direct field signal 17 and the delayed field signal 18. The voltage holding time required for each of the peak detectors 58 and 59 is as short as about 1H, since they always have inputs thereto unlike those shown in Figure 6. Therefore, the AGC loop 57 can respond very quickly. The feedback-clamping loop 30 in Figure 11 is the same as that 30 shown in Figure 6. In the loop 30, the pedestal level of the frame signal 62 sampled by the sampling switch 31 is held in the integrating circuit ₃₂ and also compared with the reference value Vref₁. The clamping potential signal 32a proportional to the difference therebetween is applied from the integrating circuit 32 to the clamping means 33 and 34 to control the latter, thereby maintaining constant the pedestal level.

The peak detectors 58 and 59 in Figure 11 may be either peak detecting means or sample and hold means. However, it is necessary to set the detection timing so that the sync tip level of each field signal can be detected in a manner as shown in Figure 12.

Figure 13 shows an embodiment which includes a modified feedback-clamping loop designated generally by the reference numeral 63. In Figure 13, the AGC loop 57 is-the same as that shown in Figure 11. The feedback-clamping loop 63 in the embodiment shown in Figure 13 is improved in its response speed compared with the loops 30 shown in Figures 6 and 11, and reduces the possibility of a sag which may occur during the vertical synchronizing period 5 (Figure 1). In other words, in the case of the loops 30 shown in Figures 6 and 11, it is a general procedure that the sampling switch 31 is actuated by a sampling pulse signal produced on the basis of HD pulses from a synchronizing signal generator (SSG). Therefore, as previously described, it is normally unable to sample the pedestal level during the vertical synchronizing period 5, and it becomes necessary to extend the voltage holding time of the integrating circuit 32 to a considerably long period of about 4H.

The feedback-clamping loop 63 in the embodiment shown in Figure 13 includes a synchronizing signal separating means 64 operative to separate the synchronizing signal 64a from the frame signal 62 obtained from the switch 16, a sampling pulse generating means 65 operative to produce a sampling pulse signal 65a on the basis of the separated synchronizing signal 64a, a sample and hold means 66 operative to sample the pedestal level of the frame signal 62 in response to the sampling pulse signal 65a, a clamping voltage generating means 67 operative to compare the output signal 66a of the sample and hold means 66 with a reference value Vref₁ and generate a voltage signal 67a proportional to the difference therebetween, and the aforementioned two clamping means 33 and 34 connected to the delayed and direct field signal lines 18 and 17, respectively.

The waveform of the separated synchronizing signal 64a is shown in Figure 14(a), and that of the sampling pulse signal 65a is shown in Figure 14(b). It will be seen in Figure 14(b) that the sampling pulse signal 65a is synchronous with the rising edges of the pulses, that is, the change points from the sync tip level to the pedestal level of the synchronizing signal 64a, and the pulse width of the signal 65a is equal to or smaller than that of the serrating pulses 6 appearing in the vertical synchronizing period 5 (Figure 1). Therefore, the sample and hold means 66 can detect the pedestal level during the entire period including the vertical blanking period 3 (Figure 1) of the frame signal 62.

The clamping voltage generating means 67 compares the sampled pedestal level with the reference valve Vref₁ and applies its output signal 67a indicative of the difference therebetween to the clamping means 33 and 34 so that the direct and delayed field signals 17 and 18 have the same and constant pedestal level. Therefore, the feedback-clamping loop 63 can clamp the pedestal level during the entire period including the vertical blanking period. Also, since the sampling interval is not longer than 1H, the required voltage holding time of the sample and hold circuit 66 is as short as only about 1H, so that the feedback-clamping loop 63 can operate with a high response speed.

Although the automatic gain controller 24 is inserted in the same signal line as the 0.5H delay line 15 in the embodiments shown in Figures 11 and 13, it may otherwise be inserted in the direct field signal line, In such a case, it is preferable that the peak detectors 58 and 59 are connected to the plus and minus input terminals respectively of the differential amplifier 29 as shown in Figure 15, unlike the connections shown in Figures 11 and 13.

In each of the embodiments shown in Figures 11, 13 and 15, the peak values of the direct field signal and delayed field signal respectively are detected before being converted into the frame signal. Therefore, the two peak detecting circuits 58 and 59 always have input signals applied thereto, and the voltage holding time is as short as about 1H, so that the AGC loop can make the AGC operation with a very high response speed. It is apparent that the frame signal after conversion can be automatically controlled to have the same signal level between the fields, because the automatic gain controller 24 is controlled by the difference signal indicative of the difference between the peak values of the-direct and delayed field signals. It is also apparent that the pedestal level of the frame signal can be automatically maintained constant, because the pedestal level of the fieldframe converted signal is sampled at the time interval of one horizontal scanning period (lH) so as to control the clamping level of the direct and delayed field signals before being converted into the frame signal. Therefore, even in the presence of temperature dependencies and/or secular variations in the components of the field signal/frame signal conversion circuit, appearance of flicker can be minimized. Also, by virtue of the fact that the signal level and pedestal level can be automatically adjusted, the manual adjustment required hitherto during the manufacturing process is unnecessary, and the flicker preventing circuit is suitable for mass-production.