Method of forming a passivated compound semiconductor substrate.

0001This invention is concerned with the passivation of compound semiconductor substrates.

0002Crystalline compound semiconductor materials have a number of advantages but such materials require special care in fabrication operations. One major limitation is that oxides which form on the surface of the compound semiconductor crystals which receive further processing, require removal prior to some types of subsequent processing operations. Since the material involves more than one element, more than one oxide can form, with some oxides being harder to remove than others. Thus, processing difficulties are encountered which may require special steps or high temperatures which frequently are incompatible with other processing operations.

0003Prior procedures for generating clean and atomically ordered surfaces of compound semiconductors that have already been air exposed, for example, Gallium Arsenide (GaAs) and Gallium Aluminum Arsenide (GaAlAs), include thermal annealing, normal and high temperature ion bombardment and annealing (IBA).

0004In addition, as reported in J. Vac. Sci. Tech. 19 (2), Aug. 1981, pages 255 and 256, already clean surfaces of GaAs, GaAlAs epitaxial layers that have been formed in ultrahigh vacuum (UHV) conditions by the molecular beam epitaxy (MBE) method have been protected by coating with As prior to removal from the UHV conditions into air.

0005For air exposed surfaces, the prior art procedures provide clean surfaces for further processing but they require a removal step which generally involves temperatures which are so high as to introduce other problems such as the diffusion of impurities from precise locations or out of the substrate or prevent patterning for device circuitry.

0006The invention seeks to provide an air exposable semiconductor substrate with a passivation layer which is easily removed using non- detrimental steps and low temperatures to provide an oxide free, clean and well ordered surface, capable of localized processing.

0007A passivated body comprising a monocrystalline substrate consisting of a single compound semiconductor and a layer of material formed on a surface of the substrate is characterised in that said layer of material consists of the most volatile element of the compound semiconductor.

0008The invention will now be described by way of example, with reference to the accompanying drawings; in which:- <ul id="ul0001" list-style="none"><li>FIG. 1 represents a semiconductor substrate passivated in accordance with the invention; and</li><li>FIG. 2 represents a prior art passivated semiconductor substrate.</li></ul>

0009In order to facilitate explanation, the description of the invention will be set forth in terms of a particular semiconductor compound and the most volatile element thereof; however, it will be apparent to one skilled in the art in the light of the principles set forth that the teaching may be readily translated to other semiconductor compound materials such as Indium Arsenide (InAs), Gallium Indium Arsenide (GaInAs) and Gallium Aluminum Arsenide (GaAlAs).

0010For the material Gallium Arsenide (GaAs), the necessary thickness of the most volatile element As layer will be governed by the harshness of the environmental conditions until the further processing takes place. Under normal temperature and corrosiveness conditions, such as • room temperature in air, an arsenic layer of 10 to 500A is satisfactory. Where the semiconductor intermediate product is GaAs, it may be formed by the exposure of at least the future processing surface of a crystalline GaAs member to light with a photon energy of greater than 1.8 eV at a power density of 0.01 to 0.5 W/cm², while the GaAs is immersed in a 1:1 HC1:H₂0 mixture or other solutions which do not etch the more volatile element for a period of 10 to 30 minutes.

0011The resulting structure is schematically illustrated in FIG. 1 wherein the upper surface is illustrative of the surface on which future processing is to occur.

0012The invention as illustrated in FIG. 1 is contrasted with the prior art as shown in FIG. 2 in that the layer 6 involves oxides of each element of the multielement semiconductor.

0013Referring to FIG. 1, a GaAs crystalline member 1, such as a wafer, is provided on the future processing surface 2 with a layer of arsenic 3. In FIG. 1, an oxide layer 5 is shown on the upper surface 4 of the layer 3. When the wafer is handled in air, a layer 5 of arsenic oxide forms. The layer 5 may be formed by exposing the layer 3 to an oxidizing environment.

0014The structure of FIG. 1 is a passivated body which permits a wafer of GaAs to be stored on the shelf in relaxed environmental constraints and at the time of use the layers 5 and 3 can be readily and predictably removed at relatively low temperatures by merely baking at temperatures of the order of 150 to 500°C.

0015The problem solved by the invention has been a limitation to the fabrication of devices in the art especially where the devices are formed in an epitaxial layer grown on the surface of a substrate wafer. In order to form epitaxial layers of GaAs, GaAlAs, etc., on GaAs substrate wafers, and in order for the layers to have good optical and electrical qualities and to have epitaxial layer substrate interfaces which have low defect densities, the GaAs substrate surface must be free of any native oxides yet must be fully crystalline in structure at the surface with minimum defects. However, annealing GaAs at the temperatures necessary to remove the oxides and especially the nonvolatile element oxides will result in an accumulation of defects and unwanted impurities at the surfaces. Therefore, there are limits to the ability to remove oxides.

0016Where the method of liquid phase epitaxial growth is employed, the substrate wafer is generally baked in hydrogen at temperatures greater than 650°C, then the GaAs substrate wafer surface is placed in contact with an undersaturated liquid phase melt which first dissolves some of the surface and then with a temperature drop there is epitaxial growth.

0017In the case of the technique of chemical vapor deposition, CVD, the GaAs substrate is generally etched in HCL acid vapor, at greater than 600°C prior to the CVD growth.

0018In the case of the molecular beam epitaxy (MBE) technique it is normally required to anneal the substrate at temperatures above 550°C to remove the oxide and to produce an atomically ordered surface prior to epitaxial growth.

0019In each technique, temperatures in excess of 550°C and as high as 640°C are required to ensure that the surface of the GaAs substrate will be free of any oxide inclusions and will be adequate for high yield semiconductor devices. This requirement is quite rigorous because in a broad array a single one micron region of oxide in a large series circuit can render the entire circuit inoperative.

0020The arsenic layer 3 is the higher volatility element and the oxide thereof is layer 5 both of which come off easily at low temperature. Further, the arsenic prevents the formation of all other less volatile oxides such as gallium oxide which does not come off easily or entirely until the temperature is raised to undesirable levels such as 550°C, which is detrimental to the product being produced.

0021By photoetching the GaAs 1 surface 2 under controlled conditions, a continuous film of arsenic 3 is formed on the GaAs which does not dissolve easily. The arsenic layer 3 at surface 4 then in turn partially oxidizes in air or can be oxidized to form an arsenic oxide layer 5.

0022By way, of example, a monocrystalline substrate wafer of n-type, GaAs having a [100] crystallographic orientation is prepared using standard chemical cleaning procedures such as an etch in 7:1:1 H₃SO₄:H₂O₂:H₂O and thereafter a rinse in deionized water.

0023The n-type GaAs wafer is then placed in a 1:1 HC1 water solution for a period of about 10 to 30 minutes. During that time, the wafer is irradiated with a 0.01 to 0.5 watt/cm² light having a photon energy in excess of 1.8 eV. The 1.8 eV level is higher than the bandgap of GaAs.

0024During that time the photoetch products including the gallium species are dissolved in the solution leaving a GaAs wafer 1 with a ° layer of arsenic 3 10 to 200A thick over the surface 2 and upon exposure to air, a further layer of arsenic oxide will form on the surface 4 of the arsenic 3.

0025The substrate wafer may then be handled and stored in air.

0026When it is subsequently desired to conduct further epitaxial growth or other processing, the wafer is annealed at 150°C to 500°C. In the annealing, at 150°C most of the surface layer 3 of arsenic will desorb, and all will be gone at 300°C. Temperatures above 300°C up to the 500°C level may be used for metallization operations such as alloying.

0027The wafer is generally n-conductivity type doped with Si, although one skilled in the art may make substitutions for different conductivity types.

0028An arsenic layer may be generated on a semi-insulating GaAs surface by photoetching while maintaining the GaAs in an anodic bias condition. On the other hand, p-type samples require a bias to produce a hole current while photoetching. Under certain conditions, an anodic bias alone will be sufficient to produce the layer of the most volatile element As.

0029The properties of the characteristics of the layer 3 have been determined through the use of standard surface science tools and the data for a number of samples is shown in Table 1. <tables id="tabl0001" num="0001"><img file="EP0108910A2_D0001.tif" /></tables>

0030The data in Table 1 is provided involving the standard in the art test techniques of "Electron Spectroscopy for Chemical Analysis" (ESCA) and "Low Energy Electron Diffraction" (LEED).

0031The data in Table 1 illustrates that for an air exposed [100] surface the GaAs surface is stoichiometric with respect to gallium and arsenic (Ga/As = 0.63), and that the surface contains a relatively large amount of oxide (O/GaAs = 0.63) and is disordered (no LEED pattern). The photoetched surface has a relatively large As concentration (Ga/As = 0.06 to 0.51), has a relatively low oxide concentration (O/GaAs = 0.03 to .33) and is disordered (no LEED pattern).

0032A 300°C anneal of a photoetched surface results in a stoichiometric surface (Ga/As = 0.63 to 0.73) and an ordered surface (LEED pattern). It should be noted that an air exposed surface of the prior art would require a 600°C anneal to achieve the same properties as a 300°C anneal of a photo-etched surface.

0033The passivated body of the invention may also be employed to provide a constant and uniform arsenic vapor pressure, an illustration of which is provided in copending patent application No. (IBM Docket No. Y0982-073), filed concurrently herewith.