A data processor with parallel-operating operation units

An information processor comprising a plurality of instruction execution units (300, 500; 600, 700), and a circuit (200; 230-232, 234, 250) which distributes the decoded information of a succeeding instruction to one of the instruction execution units on the basis of the sequentially decoded information of succeeding instructions and the decoded information of preceding instructions being under the controls of the instruction execution units. More concretely, the distribution circuit (200; 230-232, 234, 250) distributes the decoded information of the succeeding instruction conflictive with the preceding instruction to the instruction execution unit which is controlling the preceding instruction. Thus, the respective instruction execution units (300, 500; 600, 700) can execute the instructions quite independently of one another while guarenteeing a correct operated result, and enhancement in the processing capability conforming with increase in the operation units can be expected.