Oscillator circuit.

0001The invention relates to an oscillator circuit with an output oscillator which can be latched onto a predeterminable frequency by means of a phase control loop and a phase discriminator which is located in the phase control loop and which has the frequency of a reference oscillator at a first input and the output at a second input one that can be set to a predefinable division ratio, frequency divider circuit located in the feedback branch of the phase control loop is connected, the frequency of the reference oscillator being finely adjustable within the step width of the frequency division by means of a fine adjustment circuit.

0002In a known oscillator circuit of this type (DE-OS 27 50 150) the frequency of the reference oscillator is changed by means of a circuit arrangement, which is located between the reference oscillator and the first frequency divider, in certain predetermined orders of magnitude (for example 100 Hz). The change in the value of the reference frequency is here z. B. controlled by the values ​​set in an additional memory.

0003In another known oscillator circuit (magazine "Frequency" No. 22 (1968), 9, pages 255, 256) an output signal with a predeterminable frequency is generated by means of a phase control loop. In the phase-locked loop in this known oscillator circuit there is an output oscillator whose frequency can be regulated and whose control voltage is generated by a phase discriminator. The controlled variable at the output of the phase discriminator is generated by phase comparison of the frequency of the output oscillator, which is influenced by an additional mixing and division, with a frequency of a reference oscillator. The divider factor in frequency division is determined by means of a matrix at fixed, predetermined intervals, with the same frequencies occurring at the inputs of the phase discriminator due to the reaction within the phase control loop. Depending on the setting of the frequency divider and thus on the control variable obtained with the phase discriminator, different frequencies of the output oscillator can be set, which generates the output signal of the oscillator circuit. The settings of the frequency of the output signal of this known oscillator circuit are made with the integer changes in the divider ratio of the frequency divider circuit; it is not possible to change the frequency even more precisely.

0004The invention has for its object to provide an oscillator circuit which enables extremely fine adjustment of the frequency of the output signal with little circuit complexity.

0005To achieve this object, in an oscillator circuit of the type specified at the outset, the reference oscillator is connected at a pulling input to the output of a fine control circuit which is acted upon at its inputs by the first control signals which determine the division ratio of the frequency divider circuit, the fine control circuit comprising the control signals producing a fine control signal generated for the reference oscillator, with which a change in the frequency of the reference oscillator can be effected.

0006The oscillator circuit according to the invention has the advantage that an extremely fine change in the output frequency of the oscillator circuit can be made by a generally slight warping of the output frequency of the reference oscillator. The warping of the frequency of the reference oscillator takes place with a fine control signal which is obtained from a combination of the control signal intended for the fine adjustment with the control signals for the adjustment stages which can be changed via the frequency divider circuit. This combination is necessary because the change in the frequency of the output signal by the fine control signal should always take place in the range of the steps set with the frequency divider at every frequency of the output signal. For this purpose, the control signals for the frequency divider circuit must be taken into account when generating the fine control signal.

0007The invention is implemented in a particularly advantageous manner with the embodiments of the oscillator circuit according to the invention described in subclaims 2 to 10. Since the control signals for setting the frequency of the oscillator circuit are generally coded digital signals (BCD code), the above-mentioned linking of the control signals can also be carried out with a computing circuit which, after a digital-analog conversion, the fine control signal for warping the Reference oscillator provides.

0008Seen in itself, it is already known from DE-AS 24 55 236 to warp the output frequency of a quartz oscillator by driving a varactor diode, but only an oscillator arrangement that otherwise oscillates at a fixed frequency is adjusted slightly here. Problems with an oscillator circuit that can be snapped into a large frequency range and with fine adjustment do not occur here.

0009The invention is explained with reference to the figures, wherein<ul id="ul0001" list-style="none"><li>FIG. 1 shows a block diagram of the oscillator circuit according to the invention,</li><li>FIG. 2 shows a block diagram of a circuit alternative of a further exemplary embodiment of the oscillator circuit,</li><li>Figure 3 is a block diagram of another circuit alternative of the further embodiment and</li><li>Figure 4 is a circuit diagram of an embodiment of the fine control circuit of the oscillator circuit according to the invention.</li></ul>

0010In the block diagram shown in FIG. 1, a phase control loop PR has an output oscillator VCO, which generates an output signal with a frequency f_a generated, which is adjustable in size via a control input 1. The output oscillator VCO is usually a voltage controlled oscillator (Voltage Control Oscillator = VCO). The output signal of the output oscillator is fed to the input of a frequency divider circuit FT1, the

0011Divider factor n can be set via an input 2. The output of the frequency divider circuit FT1 is fed to an input 3 of a phase discriminator PD1, at the other input 4 of which a signal with a reference frequency f_refis present. The output of the phase discriminator PD1 is connected to the control input 1 of the output oscillator VCO via a low-pass filter TP1.

0012To generate the signal with the reference frequency f_ref there is a reference oscillator RO, the output frequency f_ref'by means of a downstream frequency divider circuit FT2 with a predetermined divider factor m to the predeterminable frequency f_ref is divided down; the output signal of the frequency divider circuit FT2 is fed to the other input 4 of the phase discriminator PD1. The output 5 of a fine adjustment circuit FR is connected to a pull input 6 of the reference oscillator RO. The fine control circuit FR contains a divider module DI and a digital-to-analog converter DA connected downstream of it. A coded signal a is present at a first input 7 of the fine control circuit FR and a coded signal b is present at a second input 8. The coded signals a and b are output signals of an actuating signal generator SG which transmits the actuating signals n 10 via signal lines 11 ... 15¹ f ... n 10^P f to set the desired divider ratio of the frequency divider FT2 at its input 2; the coded signal b is the control signal n 10⁰ f, which is led via the control signal line 16 to the input 7, with it the smallest possible adjustment is made via the fine control circuit FR. Setting information for an even finer frequency setting can be routed to the input 7 in the same way as the control signal line 16 via further control signal lines. The smallest possible adjustment in the exemplary embodiment shown is, for example, via the actuating signal n 10⁰ f with the factor n. 10th f_ref possible. The output signal of the output oscillator VCO is additionally conducted in the illustrated embodiment via a frequency divider circuit FT3 with a predeterminable divider factor q, so that the output signal of the oscillator circuit with the required output frequency f is present at the output of the frequency divider circuit FT3.

0013The mode of operation of the oscillator circuit according to the invention is first explained using the block diagram according to FIG. 1. The frequency f_a of the output signal of the output oscillator VCO results from the relationship:<maths id="math0001" num=""><img file="EP0093433A2_D0001.tif" /></maths>where n is the divider factor of the frequency divider FT1 and Δf_ref the distortion of the frequency f which can be effected via the pull input 6_ref'or f_ref of the reference oscillator RO represents. At the output frequency f_a in order to warp a step size of the phase control loop PR, predetermined by the control signals n 10¹ f ... n 10^P f, is therefore a certain change in f_ref necessary, which is calculated as follows:<maths id="math0002" num=""><img file="EP0093433A2_D0002.tif" /></maths>

0014With<maths id="math0003" num=""><img file="EP0093433A2_D0003.tif" /></maths>and<maths id="math0004" num=""><img file="EP0093433A2_D0004.tif" /></maths>surrendered:<maths id="math0005" num=""><img file="EP0093433A2_D0005.tif" /></maths>

0015Equation (3) can also be represented as follows:<maths id="math0006" num=""><img file="EP0093433A2_D0006.tif" /></maths>

0016so that it can be seen that the ratio Δf_ref to f_ref must behave inversely proportional to the set divider factor n in order to achieve a defined frequency change in the output frequency f_a to effect. The fine control signal Δf for causing the warping of the frequency f_ref'or f_ref of the reference oscillator RO must therefore in the illustrated embodiment from the division of the coded setting information a (control signal n 10th⁰ f) by the likewise coded setting information b (control signals n 10¹ f ... n 10^P f) are derived for the frequency divider circuit FT1. The output signal of the dividing block DI performing this division thus forms the signal c (c =<maths id="math0007" num=""><img file="EP0093433A2_D0007.tif" /></maths>); this signal c must then be converted into an analog signal to control the reference oscillator RO.

0017The warping of the frequency fref 'of the reference oscillator RO by means of the fine control signal Δf can be effected, for example, in that the reference oscillator RO is designed in the usual way as a quartz oscillator with a quartz Q which is slightly warped in its oscillating frequency by means of a varactor diode VD . With the frequency divider circuit FT2, the output frequency f_ref'of the reference oscillator RO by a predetermined divider factor m to the desired reference frequency f_ref divided down. The components of the phase-locked loop PR are dimensioned so that, for example, if the frequency f_ref = 2 kHz, also the frequency f_reqat the output of the frequency divider circuit FT1 is 2 kHz. This frequency setting is achieved by dimensioning the output oscillator VCO and by correspondingly adjusted setting information at input 2 of the frequency divider circuit FT1. The frequency of the output oscillator VCO is tracked via the phase comparison of the phase discriminator PD1.

0018The step size in the frequency setting of the output frequency f of the output oscillator VCO of the oscillator circuit according to the invention is 2 kHz in the case shown; by a further frequency division of this output frequency in the frequency divider circuit FT3, the step size can be increased to 10 Hz (f_a') can be reduced. Between these 10 Hz steps z. B. 1 Hz steps by warping the reference oscillator RO via the fine control circuit FR. A further reduction in the step size in the frequency setting is also possible, the limits here being predetermined by the quality of the reference oscillator RO.

0019The exemplary embodiment of the oscillator circuit shown in FIG. 2, based on the block diagram according to FIG. 1, has an additional arrangement of a frequency standard FN to increase the frequency accuracy of the reference oscillator RO in conjunction with a phase comparison circuit PV. The components which are identical in this exemplary embodiment with the block diagram according to FIG. 1 are provided with the same reference symbols. In the exemplary embodiment according to FIG. 2, the output 5 of the fine adjustment circuit FR is routed to an input 20 of a summation circuit SU, to the other input 21 of which the output of the phase comparison circuit PV is connected. The output of the sum circuit SU is connected to the pull input 6 of the reference oscillator RO. The output of the reference oscillator RO is led via a frequency divider circuit FT3 with the predetermined divider factor x to an input 22 of a phase discriminator PD2; another input 23 of the phase discriminator PD2 is connected to the output of a frequency divider circuit FT4 with the predetermined divider factor y. The output of the phase discriminator PD2 is connected to the input of the low pass TP2, the output of which represents the output of the phase comparison circuit.

0020The output 5 of the fine adjustment circuit FR is connected to the control input of an oscillator VC02 whose frequency can be controlled, the output signal of which is led to the input 25 of a pulse adding stage IA. Another input 26 of the pulse adder stage IA is supplied with the output signal of the frequency standard FN. The output signal of the pulse adder stage IA is fed via the frequency divider circuit FT4 to the other input 23 of the phase discriminator PD2.

0021In the embodiment according to FIG. 2 it is achieved that with the control oscillator VC02 a frequency controlled by the fine control signal Af is generated, which is applied for frequency stabilization via the pulse adder stage IA with the output frequency of the frequency standard FN and thus additionally generates a comparison by means of the phase discriminator PD2 Frequency with the output frequency of the reference oscillator RO is possible. The number of pulses to be added in the pulse adder stage IA per second results from the ratio of the frequency of the frequency standard FN of, for example, 10 MHz to the controlled output frequency of the control oscillator VC02 and thus also to the size of the fine control signal _Af. For the assumed frequency of the frequency standard of 10 MHz and a desired output frequency of 1.000009 MHz - corresponding to the maximum deflectability of the reference oscillator RO - the control oscillator VC02 has an output frequency of<maths id="math0008" num=""><img file="EP0093433A2_D0008.tif" /></maths>

0022The time constant of the low-pass filter TP2 is dimensioned so large that the added pulses after the pulse adding stage IA do not cause any disturbing phase jitter in the output signal of the summation circuit SU. This time constant can be large, since essentially only long-term changes in the frequency of the reference oscillator (temperature drift, aging, etc.) are compensated for via the additional arrangement according to FIG. The divider factors x, y of the frequency divider circuits FT3 and FT4 are to be selected according to the frequency of the frequency standard FN, so that the required frequencies are set at the inputs 22 and 23 of the phase discriminator PD2.

0023The exemplary embodiment shown in FIG. 3, which is alternative to the embodiment according to FIG. 2, contains a pulse subtracting stage IS, at one input 25 'of which the output of the reference oscillator RO is guided and at the other input 26' of which the output signal of the frequency standard FN is present. The outputs of the pulse subtraction stage IS and the control oscillator VC02 are - as in the embodiment according to FIG. 2 - routed via frequency divider circuits FT3 and FT4 to the inputs 22 and 23 of the phase discriminator PD2. The function of the oscillator circuit according to this exemplary embodiment is identical to the function of the exemplary embodiment according to FIG. 2, except for the different arrangement of the frequency standard FN and the use of a pulse subtracting stage IS instead of a pulse adding stage.

0024The circuit diagram shown in FIG. 4 shows the structure of an embodiment of the fine control circuit FR for generating the fine control signal Λf. The input of control signals n 10⁰ f for fine adjustment of the output frequency for the oscillator switching is done here via inputs 30 ... 33, for example for the frequencies with the step size 1 Hz. The control signal n 10 coded in the BCD code⁰ f is connected in parallel to the four inputs 30 ... 33 and is converted into a corresponding analog signal in the inverter circuit IV constructed from CMOS inverters IV1 ... IV4 and correspondingly rated evaluation resistors 35 ... 38. This analog signal is present at an input 39 of an operational amplifier OP. The other input 40 of the operational amplifier OP is supplied with a constant voltage UK. The control signals n 10¹ f ... n 1₀^P_f Inputs 41 ... 46 are available for the higher-level adjustment information, for example n · 10 kHz or n · 100 kHz. These control signals and other control signals relating to still further higher-level adjustment information are likewise present — not shown here — as setting information at the control input 2 of the frequency divider circuit FT1 - see FIG. 1. These control signals are converted into an analog signal here by switching on evaluation resistors 50 ... 55 with the amounts 20 R ... R - with R as a reference value - via switches S1 ... S6 in the feedback branch of the operational amplifier OP. In parallel with the resistors 50 ... 55 and the switches S1 ... S6 is a resistor 56 with the size 0.4. R switched, which serves to take into account the offset frequency of the oscillator circuit with a digital frequency input of 0. Through the wiring of the operational amplifier OP shown here, a digital-analog conversion of all control signals and a division of the control signals - as described with reference to FIG. 1 - is carried out simultaneously. Adequate accuracy in the division is guaranteed if - as shown here - only the control signals for n. 20 kHz, n. 40 kHz, n. 80 kHz and n. 100 kHz, n · 200 kHz and n · 400 kHz can be used for the division. However, other combinations are also possible to adapt to different circuit conditions.