Non-volatile dynamic ram cell

This invention provides improved non-volatile semiconductor memories which form non-inverting signals and which include a one device dynamic volatile memory circuit having a storage capacitor (C,) which includes a conductive plate (12), a charged floating gate (FG) and an inversion layer (10) in a semiconductor substrate (18) together with a non-volatile device including the floating gate (FG), a control electrode (24) and a voltage divider having first and second serially-connected capacitors (C2, C1), with the floating gate (FG) being disposed at the common point between the first and second capacitors (C2, C1). The plate (12) of the storage capacitor (C,) is connected to a reference voltage source. The control electrode (24) is capacitively coupled to the floating gate (FG) through the first capacitor (C2) which includes a charge or electron injector structure. The capacitance of the first capacitor (C2) has a value, preferably, substantially less than that of the second capacitor (C1) which is formed between the floating gate (FG) and the semiconductor substrate (18).