Data transmission installation for full duplex transmission.

The invention relates to a data transmission system for full duplex transmission over a two-wire line between a master station and a slave station having the features of the preamble of claim 1.

Such data transmission system is known from DE-PS 24 53 628th Such systems are used for signal transmission over short distances with short transmission delays. On the two-wire line (1 bit, 1 dibit, 1 tribit) is in rapid direction changes alternately transmitted from the master station to the slave station, or vice versa only the information contained in a single signal step. The transmission code is chosen so that in the slave station from this the Signalschrittakt is to be derived, so that the slave station is synchronized with the master station.

In the plant according to the DE-PS 24 53 628. At the ONU no active clock generator is provided. This has the consequence that, when an interruption of the line that is connected to the slave station terminal from the slave station does not receive a clock.

Incidentally, in the DE-PS 24 53 628 of the master station to the slave station a bipolar RZ signal (RZ = return to zero) and from the slave station is sent a unipolar RZ signal to the master station. Both transmission signals are each sampled by the clock from the NRZ signals (NRZ = non return to zero). A DC-free transmission can not be achieved in the mentioned RZ signals.

Object of the invention is to provide a circuit having the features of the preamble of claim 1, wherein the sub-station generates an independent from the clock of the master station clock whose clock period quickly synchronized with the reception to the clock period of the master station.

The above object is achieved by the features of the characterizing portion of claim 1. The active clock generation in the ONU is ensured that it is always clocked with this connected terminal from the slave station namely in the case of reception with a synchronized to the transmission cycle of the master station clock and interrupt the transmission path of a clock that although the timing of the master station tations, at the onset of reception but quickly synchronized to that.

Advantageous embodiments of the invention will become apparent from the following description and the dependent claims. In the drawings:<ul><li>Fig.l is a block diagram of a data transmission system and</li><li>2 shows time charts of the circuit diagram of Fig.l.</li></ul>

A terminal 1 is connected to a main station 2 and a terminal 3 is connected to a slave station. 4 The terminals are, for example, teletex devices. The main station 2 is connected to the slave station 4 by a two-wire line 5, which is short, is routed, for example within a building.

The main station 2 has an TakterzeugerTl, which is controlled by a crystal oscillator Q1 and a transmit clock a (see. Figure 2) passes on the one hand to an encoder Cl and on the other hand to a decoder Dl. The encoder accepts Cl from the terminal 1 b transmit data (see. Figure 2) and forwards them as a coded transmission signal c to a transformer UEL, which lies on the two-wire line 5. The transformer UEL is also connected to the decoder Dl, the reception data to the terminal 1 passes.

The slave station 4 has an encoder C2, the transmission data acquired by the terminal 3 in the same manner as the encoder converts Cl in a transmission signal i (vgl.Fig.2) and a transformer U2, which is connected to the two-wire line 5, passes , In the ONU 4, a crystal oscillator Q2 is provided which operates at a nominal frequency of 4.6 MHz, for example. The oscillator Q2 is connected to a clock generator T2, having a divider. The divider is in its division ratio between n -.. Switchable 1 and n + 1 at an input 6 and provides at its output 7 to receive clock h n is the ratio of the frequencies of the oscillator Q2 and the receive clock h This is after inversion by an inverter I as a transmit clock g encoder C2 supplied.

The slave station 4 has two comparators COMP1 and KOMP2 to which the transformer U2 is connected. In a comparator, the positive in the other rectified the negative portions of the received signal d and limited in amplitude. Each of the comparators is a differentiating circuit DIF1 DIF2 or downstream whose output pulses are linked via an AND gate eighth At the output of the AND gate 8, this results in the signal e, whose pulses occur at the zero crossing of the received signal d. The zero-crossing signal e is applied to an input of a phase comparator circuit 9, to whose other input a comparison clock is set f, which is derived via a delay stage 10 from the receive clock at the output h 7th The phase comparison circuit 9 is located at the input 6 of the divider. You control this so that its division ratio n + 1, if the signals e and f do not overlap in time or when no transmission signal is present d. His division ratio is n - 1, if the signals e and f overlap.

The output 7 is connected to a clock input of the terminal. 3 The comparator KOMP2 together with an output of 7 controlled via a further delay stage 11 scanner 12 to decoder D2 the ONU 4. The samples are taken over by a flip-flop 13 and supplied as received data to the terminal. 3 The flip-flop 13 is controlled by the receiving clock h.

The operation of the described system is as follows:

The transmit clock a has a clock period Ta and a 50% duty cycle. During the "1" signal of the transmit clock a Cl encoder and the decoder operates D1 is blocked. During the "0" signal, the encoder is inhibited and the Cl decoder Dl operates.

In Fig.2 for example, the NRZ signals "0", "1", "1", "0", "1" are shown for the transmission data b. These transmission data b to be implemented in the encoder Cl during the "1" signal of the clock a in the transmission signal C, which is DC-free. For each transmit signal unit consists of a negative and positive signal component, wherein a "0" signal to the negative portion follows the positive portion and at a "1" signal to the positive the negative portion follows (Figure 2c).

The transmission signal c arises after passing through the two-wire line 5 as a reception signal d. From this are derived the zero crossings e. These occur visible on the clock period Ta of a transmit clock. With this the reception clock h is to be synchronized, the clock period is denoted by Th. For this is the Q2 or Takterzeu from the generator^GHe compared T2 via the delay stage 10 derived comparison clock f in the phase of its falling edge to the rising edge of the zero-crossing signal e. The rising edge of the zero-crossing signal e is delayed from the rising edge of the transmit clock a one-quarter clock period Ta. To account for this, the falling, for comparison with the zero-crossing signal e solved edge of the comparison clock is f delayed by the delay stage 10 at the same time. Overlaps the signal f, the signal e, the divider to the divider ratio n - 1, where n is, for example, 384, are connected. Overlaps the signal e, the signal f is not, the division ratio is switched to n + 1st Thus, the falling edge of the comparison clock jitters f to the rising edge of the zero-crossing signal e. It is the clock of the ONU 4 latched at the output 7 to the transmission cycle of the main station 2. The transmit clock g is h to receive clock and so thus inverted to transmit clock a, so that a signal derived from the transmission data of the terminal 3 transmission signal i, in the exemplary case "l", "0", "0", "l", "l" is transmitted when the encoder and the decoder disables Cl Dl is active. Line related terms are discussed here in detail, since they are negligibly short relative to a clock period.

The delay stage 11 delays the reception clock h to 3/8 of the clock period Th, to ensure op timal scan in scanner 12th Optimum sampling means that the sampling is performed at a greater eye aperture.

As long as the ONU 4 is not receiving a reception signal d, the splitter a relatively large deviation of the clock period Th relative to the clock period Ta The phase of the comparison clock f works with a divider ratio n + 1. This represents. Passes thus in a short time period Ta of the zero-crossing signal e . Once a received signal e, ie, the time is rapidly reached at which a falling edge of the clock comparison f coincides with a rising edge of the zero-crossing signal e, which then takes the desired synchronization.