Monolithic integrated semiconductor bridge circuit.

The invention relates to a monolithically integrated rectifier bridge circuit according to the preamble of claim 1, as described in DE-OS 16 39 177th

The DC supply voltage of integrated circuits can be obtained from an AC voltage rectifier bridge containing using a diode elements. It is close to the idea mitzuintegrieren the bridge. However, this causes the described in DE-OS 16 39 177 issues, namely to suppress the effect of occurring parasitic transistors as possible, what is there achieved by lowering the current gain of the parasitic transistors. Thereby, the substrate current of a corresponding diode element negligible and the assembly is integrated monolithically in bipolar technology. According to DE-OS 16 39 177 this can be achieved by means of a constitution in which arranged in on a semiconductor body of one conductivity type, by pn junctions each other isolated areas of a layer of the opposite conductivity type for forming diode elements each have a zone of the substrate conductivity type and each a contacting zone are inserted, wherein the distance between the constructed as a long and narrow stripe regions of the substrate conductivity type and the contacting zones surrounding it is chosen as low as possible and accordingly the breakdown voltage and the width of the contacting zones is substantially larger than the diffusion length of the minority charge carriers in the isolated areas.

The known realized in bipolar arrangement has its own so-called isolation well, which leads to a certain area required, which however is no longer acceptable at high integration densities for each diode element. In addition, also requires the elongated contacting zones a required floor space.

The object of the invention is to provide a monolithically integrated rectifier circuit according to the preamble of claim 1 in such a way that it has less floor space than the known and can be omitted that the Isolierwannen forming isolation diffusion zone with her. Nevertheless this case however, the effect of the parasitic transistors should be avoided. This is achieved by the features specified in the characterizing part of the claim.

The integrated rectifier bridge circuit according to the invention can therefore be produced with such process steps as are required for CMOS circuits, since the structure of the semiconductor body corresponds to that of CMOS circuits, said pn junctions in both a p-environment and in an n environment are available.

The invention will now be explained in more detail with reference to the figures of the drawing.<ul><li>Fig. 1 shows the circuit diagram of a conventional rectifier bridge circuit,</li><li>Fig. 2 shows a schematic sectional view of the semiconductor body of a possible integrated rectifier bridge circuit,</li><li>FIGS. 3 and Fig. 4 show equivalent circuits of the arrangement according to FIG. 2,</li><li>Fig. 5 shows schematically the sectional view of the semiconductor body an integrated rectifier bridge circuit according to the invention,</li><li>Fig. Figure 6 shows the relevant circuit diagram,</li><li>Fig. 7 shows the circuit diagram of a further embodiment of the integrated bridge rectifier circuit according to the invention,</li><li>Fig. 8 shows typical voltage conditions on the bridge elements of the arrangement of FIG. 5 at the occurrence of a positive half-wave at one of the AC inputs,</li><li>Fig. 9 shows the relevant circuit diagram,</li><li>Fig. Figure 10 shows the equivalent circuit diagram of FIG. 8 in which the parasitic transistors are located, and</li><li>Fig. 11 shows the equivalent circuit diagram of an integrated bridge rectifier circuit according to the invention, in which a vertical parasitic NPN transistor forms a four-layer structure with a lateral parasitic PNP transistor.</li></ul>

Fig. 1 shows the circuit diagram of a conventional rectifier bridge circuit, wherein in the bridge arms 1, 2'die diode elements D1, D2, with its cathode on formed by the former vertex P1 and the diode elements D3, D4 in the bridge arms 3 ', 4¹with their anodes are formed by at that vertex P2. At the corner points P1, P2, the DC voltage is removed. At the '3'bzw of the bridge arms. 1 2) 4 'formed vertices P3, P4 to be rectified AC voltage is fed.

Fig. 2 shows in section the possible construction of a semiconductor body of such a bridge circuit in which the diode elements D1 ... D4 realized by the corresponding pn junctions. In the n-type semiconductor body 1, the p-type zones 2, 3, 4 are inserted in the manner of the usual planar technology, whereby the areas 3, 4 with the semiconductor body 1, the pn diode D1 'D2'bilden. Indie zone 2, two n-type regions used 5.6, the D3 'D4' form with the p-type region 2, the pn diode. By the pn junction between the zone 2 and the n-conducting semiconductor body 1 is formed the fifth_Diodenelement D5, which is also shown in the equivalent circuit of FIG. 3. This diode element does not interfere unless its breakdown voltage is sufficiently high.

However, the equivalent circuit of FIG. 3 is valid only for those cases in which the zone is 2 penetrated so deeply into the semiconductor body 1 that no parasitic vertical NPN transistors between the territories 5-2-1 or 6-2-1 arise. Such ratios are straight but not before, when the semiconductor body of conventional CMOS circuits, which is not wired primitive (CMOS inverter) from the semiconductor body 1 and Zone 2 is, according to the zones 3 ... 6 Fig. 2 to forming a rectifier bridge circuit would be completed. It would be valid in this equivalent circuit of Fig. 4 in place of the diode elements D3, D4 GE showed T3 'T4' transistors effective that the direct-voltage terminal P1 with the alternating-voltage terminals P3, P4_, Soon joined via the emitter-collector path of each transistor.

In FIG. 5, a first embodiment of the invention is shown and in Fig. 6, the corresponding circuit diagram. The rectifier bridge circuit comprises in each case in the first and second bridge arm 1 ', 2 the two pn diodes D1', D2 ', which have their cathodes on formed by the two arms of the bridge 1, 2 vertex P1. Instead of the two other diode elements D3, D4 of FIG. 1, the two insulated-gate field effect transistors T3, T4 of the enhancement type having its controlled current path in nevertheless bridge arms 3 ', 4, wherein the gate of the transistor T3 with the vertex P4 and that of the transistor_T4 is connected to the corner point P3, that is, the gates of the two transistors T3, T4 are cross-connected to the AC inputs of the rectifier bridge circuit.

In Fig. 5, the transistors T3, T4 within the p-type region 2 are formed in that into it the n-type (source) region 11 of the transistor T3 - and the n-type (source) zone 12 of the transistor T4 and the two transistors T3, T4 common (drain) region 13 is inserted. The zones 11, 13 and 12, 13 are arranged at a mutual distance from each other that can form between them, the channel in a known manner, if at the arranged above the interspace gate electrode 15 and 16, the voltage is applied. Under the gate electrode is the gate insulating film 5 for simplicity not shown in Fig..

In the arrangement according to the invention flows through the respective one of the source region 11, 12 or the common drain zone 13 of the transistors T3, T4 formed with the zone 2 pn junctions no current as a base current of a parasitic vertical npn could act transistor as long as the voltage drop at the relevant channel of the transistors T3, T4, that is, the source-drain voltage is not greater than the threshold voltage of the formed in the zone 2 pn upper gears.

_Fig. 7 shows the diagram of a second embodiment of the invention, wherein the two transistors T3, T4 insulated gate field effect transistors of the depletion type. The gate of transistor T3 lies at the end point P3, that of the transistor T4 at the end point P4.

The bridge circuit according to the invention according to FIGS. 5 and 6 can be formed by appropriate selection of the ON resistance of the transistors T3, T4 so that the vertical parasitic NPN transistors limit the DC output voltage for over-current in the bridge. In Figs. 8 and 9, the voltage conditions are shown at the bridging elements when the vertex P4 abuts a positive half-wave in comparison to the corner point P3. The arrows indicate here the direction of current flow. The voltage drop across the channel of the transistor T3 should be 0.5 volts in the example chosen. This corresponds to a channel resistance of 50 ohms a current of 10 mA. The base-emitter voltage of the parasitic transistor also SFBC is 0.5 volts, this transistor is therefore still locked. Rising voltage and current at the input, so at 14 mA is the Schwells^preached al voltage of the parasitic transistor of 0.7 volts, so that current begins to flow in parallel with the load RL, so past it.

The FIG. 10 shows the corresponding equivalent circuit diagram with the parasitic transistors SFBC.

The circuit according to the invention may on the other hand - Be topologically also designed so that the vertical parasitic NPN transistor with the lateral parasitic PNP transistor forming a four-layer structure, which ignites at a fixed current. In this way, voltage and power dissipation over the bridge would greatly reduced. An equivalent circuit for one half-wave is shown in Fig. 11, in T5, the vertical parasitic NPN transistor T6 and the lateral parasitic PNP transistor is designated.

The exemplary embodiments show an n-type semiconductor body 1 and n-type regions 12, 13, 14 and p-type regions 2, 3, 4. Of course you can also start from a p-type semiconductor body, then the other zones of corresponding opposite Lei_-- Tungsart to choose.