Device for ultrasonic scanning.

The invention relates to a device for ultrasound scanning with an ultrasound applicator, which is formed by a plurality of individual transducer elements for emitting ultrasound signals and for receiving the echo signals, a delay device being provided at least in the electrical receiving circuit, which delays the resulting echo signals for each transducer element so delayed that in the chronological order of the occurrence of signals at the individual elements at the output of the delay device, the individual signals are in phase.

A device of this type is, for example, by Ultrasonics Symposium Proceedings, IEEE Cat. 1977, pages 250 to 254. This device works with memory elements as part of the delay device, the individual memories being full-line memories which therefore store a complete ultrasound line. A line is read in and out in the so-called removable buffer principle, ie information is always just being read into one of two line memories, while information is omitted from the assigned second memory. The principle of such a removable buffer memory is also described, inter alia, in DE-PS 26 29 895. However, the use of full-line memories has the disadvantage that an unnecessarily large amount of memory is required with a larger number of converter elements.

The object of the present invention is to construct a device of the type mentioned at the outset which manages with an optimally low storage capacity of the delay memories.

The object is achieved in that the delay device comprises a multiplicity of partial line memories, of which at least three are always assigned to a single converter element, the storage capacity of each partial line memory having such a value for each individual converter element, which corresponds at least to the maximum delay time of the transducer element arrangement and wherein in the triad of partial line memories of each transducer element, such a control is provided that, starting with the first transducer element in each case, which is acted upon by all elements first with information, and for each subsequent transducer element there accumulating information is sequentially written into the memory of the assigned triplet as long as until at the last converter element, which receives the last information from all elements, at least the first partial line memory of the group of three, which belongs to this last element, is filled with information and then a read start pulse is given, on the basis of which the data in all memories up to this point stored information is read out simultaneously.

In the invention, the storage capacity of a partial line memory essentially depends only on the maximum delay time of the transducer element arrangement. Since the delay time is generally very small even with large swivel angles - it is a fraction, e.g. B. a 1/16 or even less, the total storage time of a full-line memory, so there is always a relatively small required storage time and thus also an optimally low storage capacity of the partial-line memory to be used. In the case of a large number of converter elements of the converter element arrangement, the total expenditure on storage capacity is therefore optimally low.

The invention can be advantageous in so-called phased arrays, for. B. to carry out sector scans by beam swing due to different signal delay_Japply. Use in combination with dynamic focusing or use in a linear array without beam swiveling, but with dynamic focusing, is equally possible. When a beam swiveling method is combined with dynamic focusing, in an advantageous embodiment of the invention, in addition to the maximum delay time of the transducer arrangement, there is also a focus setting time which must be taken into account when setting the minimum capacity of a partial line memory. If, in a further embodiment of the invention, only dynamic focusing is used, this focus setting time takes the place of the maximum delay time of the converter arrangement. The latter is zero, since the beam is not swiveled, so that delay times resulting from this need not be taken into account. Viewed overall, the invention thus offers the possibility of diverse use in the most varied of operating modes with an extremely low total expenditure on storage capacity. A particularly outstanding operating mode is that of digital operation. For this purpose, the resulting echo information is digitized and then digitally processed further in accordance with the invention in partial line memories on a digital basis, in particular in RAM memory technology. The transition to digital technology has the considerable advantage that the overall arrangement of all operating modes can be controlled by software. This not only enables problem-free and quickly convertible sequence control; Since no more analog ultrasound signals have to be switched anywhere in the control circuit (such as LC technology), there can be no more switching clicks that are noticeable as false echoes in the image structure. Compared to CCD storage (charge coupled device) or BBD storage (bucket brigade device or bucket chain storage) is also increased stability.

Further advantages and details of the invention emerge from the following description of an exemplary embodiment with reference to the drawing in conjunction with the subclaims.

Show it<ul id="ul0001" list-style="none"><li>1 is a diagram of the operation of the invention when applied to pure beam swiveling or in combination with dynamic focusing,</li><li>2 shows a diagram corresponding to FIG. 1 for use only on dynamic focusing,</li><li>3 shows the basic circuit diagram of the invention based on an individual converter element,</li><li>Fig. 4 shows the basic circuit diagram of the invention for the overall arrangement of converter elements.</li></ul>

1 shows a schematic indication of a transducer element arrangement W1 to Wn on the left side of the diagram. The beam swivel is selected (indicated by dashed delay line 1) so that echo signals, which are received again after transmission signals have been sent, only arrive as information at the transducer element W1_lwhile subsequent transducer elements W2, W3 etc. only receive echo information with increasing delay times. The last element Wn of the transducer element row receives echo information as the last of all elements with a maximum time delay τ_Max. The scanning direction of the ultrasound beam can be changed as desired (e.g. according to the program). Appropriate preselection of different delay times also changes the angle of the dashed delay line 1, to which the main emission direction of the ultrasound scanning beams is essentially perpendicular. The overall concept, however, is always such that the maximum delay time of the converter element always hit last (in the present case Wn or W1 when the radiation direction is reflected on the axis of symmetry of the converter element arrangement) the preselected value τ_Max does not exceed.

An essential feature is that each transducer element W1 to Wn of the transducer element arrangement is associated with a triad of partial line memories, each of which therefore dynamically stores only a very specific fraction of the total line (e.g. a sixteenth of the total line). In Fig. 1, the partial line memory of a group of three are each designated I, II, III. All subline memories of a group of three can be continuously filled with information one after the other; The entry of information into the group of three is such that, starting with the converter element that is always first hit by information (in the present case W1), the information of this element is sequentially read into the individual partial line memories I to III as long as until at least the first partial line memory I of the converter element (in the present case Wn) that was always hit last by information from the entire row W1 to Wn is filled with this information. In this case, a read start pulse is then set, on the basis of which the information which has started in all the memories is then read out simultaneously.

In the diagram in FIG. 1, the starting time STE for writing S is indicated by the arrival of the first information on the first transducer element W1 of the transducer element arrangement. For each subsequent converter element Wi, the delay time with which further information arrives late is corresponding to STE._' enrolled with a delay. With regard to the last transducer element Wn is finally done around time_Max Delayed writing of information into the first partial line memory I. However, if this first partial line memory I of the converter element Wn is filled, a read start pulse can be given for simultaneous reading out L of the information of all partial line memories of all converter elements W1 to Wn. In FIG. 1, the start time STL for the read start pulse is still somewhat delayed, since a response time Δ F_Max for the focus is involved. This additional time interval is always taken into account when dynamic beam focusing is also carried out at the same time.

FIG. 2 shows the principle of FIG. 1 without beam swiveling only for dynamic focusing. In this case, the delay time is τ_Max = 0 and only the above-mentioned focus setting time Δ F occurs_Max in action. This focus setting time changes depending on the depth<img file="EP0027618A2_D0001.tif" /> of the examination subject, from which echo signals are to be received sharply (focused). The change diagram of the response time is shown schematically as 4F (9) in FIG. 2. Due to the purely dynamic focusing, there is a different delay curve for each focus distance, e.g. B. corresponding to the curved dashed line 2.

The basic circuit diagram for carrying out a functional principle according to FIGS. 1 or 2 is shown in FIG. 3 for an individual converter element W1 to Wn. In FIG. 3, the transmission pulse generator for the transmission pulse A is designated by 3 on the side of the transmission circuit. The transmission pulse generator 3 generates the transmission pulses in time with the trigger pulses of a master generator 4, which is controlled by a programmer 5, in which the transmission program according to the relationship A_TQ (<img file="EP0027618A2_D0002.tif" />, <img file="EP0027618A2_D0003.tif" />) is stored on demand . A means the server fall and T the respective transmission delay time, with Q indicating that quantized values ​​are available. ϕ is the swivel angle of the radiation and α is the location of a controlled transducer element in the row of the transducer element arrangement. The ultrasonic echo signals generated and received again due to the transmission of a transmission pulse on a transducer element or rather transducer element group in the examination object. after conversion back into corresponding electrical signals E (t) by the respective converter element, a high-frequency amplifier 6 (80 dB amplifier) ​​is fed. The amplified echo signals are then rectified in a full-wave rectifier 7 and the rectified signal is then passed via an analog-digital converter 8 to a combination circuit comprising a data multiplexer 9 and a two's complement 10. Finally, at the output of the combination circuit 9 and 10, there is the triad of partial line memories I, II, III. In the present case, there are three RAM memories with a capacity of z. B. 256 x 8 bits.

The use of a combination circuit of a data multiplexer 9 with a two's complement 10 has the following essential task: On the one hand, when the echo signals are made visible, there is a desire for optimally high resolution. However, this generally requires high-number analog-to-digital converters, which are considerable. are expensive. The. Circuit arrangement also requires optimal assignment of received signals in the phase after the delay. The summing circuit required for this should be as simple as possible. Both problems are solved in a surprisingly simple manner by the circuit arrangement 6 to 10. The solution assumes that the resulting echo signals have both positive and negative components. related to zero line potential. An analog-to-digital converter would therefore have to convert the entire dynamic range from the highest negative amplitude to the highest positive amplitude, but this would require analog-to-digital converters of a relatively high number of bits in order to be able to achieve an acceptable value for the resolution. However, much more favorable conditions result if the resulting echo signal is rectified before implementation. After rectification, the resolution only concentrates on signal components of a single polarity; with the same good degree of resolution a bitveniger is required. This also reduces the bit number of the analog-digital converter required for the resolution by 1 bit. This becomes cheaper. However, since rectification always means loss of the sign at the same time, care must be taken to ensure that a sign signal is formed which occurs throughout the further processing up to the summing device as a companion of the signal components to be processed and which ultimately the components . Display reassembled in the correct sign. However, the 1 bit that is no longer required to be generated by the analog-to-digital converter, but can now be formed directly by the sign detector and used as a carrier of the sign information, offers itself as the carrier of the sign information in an optimally simple and surprising manner. In the circuit diagram of FIG. 3, the amplifier 6 is therefore simultaneously designed as a sign detector for positive and negative components of the echo signals produced. Depending on the sign that is detected, a signal is then generated which, via a sign signal line 12, controls the combination of the multiplexer 9 with the two's complement 10 in the sense of a switch for the signal of the analog-digital converter 8. In the present exemplary embodiment, the amplifier 6 works in such a way that it generates a sign bit only when negative components of the echo signal E (t) are present and leads it via the line 12 to the multiplexer 9 and two's complement formers 10. The switching of both components 9 and 10 takes place depending on the sign signal in such a way that with signalless line 12, ie with the presence of positive signal components, the output information of the analog-digital converter 8 together with the sign bit via the data multiplexer 9 directly is forwarded to the partial line memory 11. If, on the other hand, negative components are registered, the output information of the analog-digital converter 8 is switched to the input of the two's complement 10 via the signal occurring in the signal line 12. The latter then forms the two's complement 2-K for the output information of the analog-digital converter and then forwards the two's complement information together with the sign bit to the group of three 11 of the partial line memories. Here there is then a delay in those modes of operation as have already been explained above with reference to FIGS. 1 and 2. The respective function is again controlled by program memories 12 and / or 13 which, in conjunction with address counters and enable elements, control each group of three 11 from partial line memories separately. In the block diagram of Fig. 3rd Block 14 defines a linear address counter for write S and block 15 defines the generator for the write enable pulses. Accordingly, block 16 represents an address counter for read L and block 17 represents an address adder, while block 18 is an address multiplexer for finding the addresses for write S and read L. In the embodiment of FIG. 3rd the programmer 12 provides specifically the information for setting the delay times according to the relationship T._RQ (<img file="EP0027618A2_D0004.tif" />, <img file="EP0027618A2_D0005.tif" />, <img file="EP0027618A2_D0006.tif" /> = m). T is again the delay time and R stands for the reception case, while Q again gives the information "quantized". ϕ is the swivel angle and<img file="EP0027618A2_D0007.tif" /> the location of the controlled transducer element on the transducer element row. The parameter<img file="EP0027618A2_D0008.tif" /> defines the depth of penetration and m the last of a predetermined number 0 to m of focusing areas that can be adjusted step by step over the entire examination depth range. The programmer 13, on the other hand, provides control programs for dynamic focusing, if these are required. The program of dynamic focusing is according to the relationship<maths id="math0001" num=""><img file="EP0027618A2_D0009.tif" /></maths>{T_RQ (ϕ, æ,) - T_RQ (<img file="EP0027618A2_D0010.tif" />, <img file="EP0027618A2_D0011.tif" />, <img file="EP0027618A2_D0012.tif" /> = m)]}. Both programmers 12, 13 can be used both in combination and individually, with the other not being activated.

The basic circuit for the further processing of the signals originating from each individual converter element W1 b Wn in the sense of the phase-correct assembly is shown in FIG. Each converter element is then followed by a block B1 to Bn, each of which is constructed in accordance with the basic circuit diagram of FIG. 3. The outputs of all blocks B1 to Bn then go to a digital adder 19 for adding the signals. Due to the selection of the combination of a multiplexer with a two's complement generator explained above, the digital adder 19 can be designed in a particularly simple manner as a simple summing circuit. Without the use of a two's complement, on the other hand, both sums and differences would have to be formed, as a result of which the expenditure of the adding unit would increase considerably. A pure summation is possible because, as already explained above, each negative component of the echo signals contains the information of the minus sign through the formation of two's complement. After simple addition has taken place, the sum signal then goes to a downstream chain comprising a digital compensation amplifier 20 and a digital demodulator 21. The demodulated digital signals are then finally fed via a digital filter 22 to a rounding element 23 for bit number reduction. The data-reduced signal occurring at the output of the rounding element 23, which converts, for example, 11-bit information into 8-bit information, is then transmitted in the direction of arrow 24 via z. B. image memory or the like. An image display tube for recording. The overall control of the links B1 to Bn or 19 to 23 in FIG. 4 takes place by means of a central micro-program control unit 25, which also permits changes to the program of the program transmitters B1 to Bn. The central clock is an oscillator 26.