Cursor display control system for a raster scan type display system.

The present invention relates to a display system and, more particularly, to a display system of the type in which a screen of a display system of the raster scan type is divided into a plurality of sections and the display information on the screen divided are supplied to stations by using mirror reflection.

In place of the conventional card punch system, a Key to FDD (referred to as a data system) using a floppy disc as a recording medium has been used widely. FDD is an abbreviation of a floppy disc drive. A data system of this type allowing two operators to individually perform the works has an increasing market because of its good cost/performance. The two-operator data system will be called a multiple data system. Most of the multiple data system is of the type using a single display unit. More particularly, a single screen is divided into two screen sections for displaying independently the display information. A mirror used in combination with the divided-screen reflects the display information on the divided screens toward two operators. In a multiple data system having the above display unit, the display unit may be single but the display controller can not be reduced to 1/2 in the hardware, simply. Especially, one cursor signal is necessary for the respective operators. Accordingly, the number of parts used in the cursor control circuit increases to make the circuit complicated and cost thereof high.

Accordingly, an object of the invention is to provide a cursor display system capable of displaying cursors at different positions on the display surface of stations.

To achieve the above object, there is provided a * display system which divides display screen and provides display information to respective sides using mirror reflection comprising; <ul id="ul0001" list-style="none"><li>an oscillator for producing a refresh clock signal;</li><li>a programmable CRT controller for interfacing the display unit of the raster scan type and a central processing element and for producing a refresh memory address, a raster address and a timing signal in order that a display information can be programmably displayed on the screen as to a number of display characters for one line, a number of raster and cursor position;</li><li>a refresh memory for storing the coded data to be displayed by the refresh memory address outputted from the programmable CRT controller;</li><li>a character generator for converting the coded data supplied from the refresh memory into display pattern data; and</li><li>a display unit for displaying the dot data in the raster scan manner characterized in that there are further provided,</li><li>a raster address converting circuit means which receives the raster address information from the controller and converts the raster address information by control information as a part of the refresh memory address;</li><li>multiplexer means for selecting and producing the raster address information from the controller and the output information from the raster address converting circuit by the control information as a part of the refresh memory address;</li><li>bidirectional shift register means which receives the pattern information from the character generator, determines the shift direction by the control information as a part of the refresh memory address, and produces serial dot data through a logic circuit to the display unit;</li><li>cursor address information storing means for storing the cursor address information supplied from a central processing element through a system bus;</li><li>comparing means which compares the cursor address information outputted from the cursor address information storage means with the refresh memory address outputted from the programmable CRT controller and produces a cursor display signal when both the information are coincide with each other.</li></ul>

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: <ul id="ul0002" list-style="none"><li>Fig. 1 is a block diagram of a multiple data system to which the invention is applied;</li><li>Fig. 2 diagramatically illustrates how a single display unit provides two screens;</li><li>Fig. 3 illustrates displays of two characters "A" and "F" which are commonly displayed on the screens of the stations;</li><li>Fig. 4 is a block diagram of an embodiment of a -cursor display system for a raster scan type display system according to the invention;</li><li>Fig. 5 is a construction of a programmable interface shown in Fig. 4;</li><li>Fig. 6 is a logic construction of a bidirectional shift register shown in Fig. 4; and</li><li>Fig. 7 is formats of characters displayed on a display screen of the display system to which the invention is applied.</li></ul>

Referring now to Fig. 1, there is shown a multiple data system to which the invention is applied. In the figure, a main memory unit (MMU) 11 connecting to a system bus 10 including an address line, a data line and a control line is comprised of a read only memory and a random access memory and stores programs and data through the system line 10. A central processing unit (CPU) 12 connecting to the system bus 10 performs arithmetic operation and the control of the entire system under control of the program stored in the MMU 11. Floppy disc controllers (FDD) 13 and 14 are connected to the system bus 10 and also to floppy disc units (FDU) 15 and 16. The FDUs 15 and 16 store the programs and data which are overflowed from the MMU 11. The keyboards 17 and 18 are connected through keyboard controllers (KBC) 19 and 20 to the system bus 10. The data keyed in by the KBS 17 and 18 are temporarily stored in the MMU 11 through the system bus 20 and then is displayed on the CRT 22 through the CRT controller 21 (CRTC). The CRTC 21 holds the display data of the CRT 22, performs the data conversion, and generates the synchronizing signal. The CRT 22 is so designed as to provide two picture screens corresponding to the stations. The FDD 15 and the KB 17 are assigned to the station 1 or the FDD 16 and the KB 18 are assigned to the station 2.

Fig. 2 illustrates the principle to provide two pictures by using a single picture screen. Pictures on the CRT 22 are reflected by a mirror 23 toward the operators at the stations #1 24 and #2 25. In this way, one picture screen is divided into two sections and the different information are supplied to the respective operators. Accordingly, when characters "F" and "A" as the display data are applied to the stations, the formats of the characters displayed on the CRT screen are as shown in Fig. 3 and the upper part above a central broken line is for the station #2 25 and the lower part below the broken line is for the station #1 24.

Fig. 4 is a hardware block diagram of an embodiment of a cursor control system according to the invention. In the figure, an oscillator 41 produces a clock signal to provide dots which cooperatively form a symbol or characters on the CRT screen. A dot counter 42 is connected to the oscillator 41 to count the clock signal produced from the oscillator 41 and to produce the count data for each character display. The counter data outputted is supplied to a CRT controller 44 and a bidirectional shift register 43. The CRT controller 44 is connected to the system bus 10 and the dot counter 42. The CRT controller 44 is a controller for interfacing between the CPU 12 and the CRT 22 of the raster scan type. HD 46505 (Programmable CRT Controller) of large scale integration (LSI) is applicable for the controller 44. The controller 44 is capable of controlling of: the period of the horizontal scanning, the period of the vertical scanning for each line, the number of display characters for each line, the number of display lines of one picture, the number of rasters for each line, the display position in the horizontal direction on the CRT 22, the display position in the vertical direction on the CRT, the pulse width of a horizontal synchronizing signal, the cursor display position on the CRT 22, and the direction of an address to make an access to the refresh memory. Accordingly, the CRT controller 44 can programmably form a picture on the CRT 22 using the above items as parameters. The CRT controller 44 has four registers--for signals to control the cursor. Those registers are: a cursor start raster register, a cursor end raster register, a cursor (H) register to store the high portion of the refresh memory address, and a cursor (L) register to store the low portion of the refresh memory address. If the capacity of the refresh memory is small, for example, 256 words/display, a parameter is set only in the cursor (L) resistor. In the cursor (H) register, all "ZERO" should be set. In this case, however, the number of bits are 8 bits.

The controller 44 produces a horizontal synchronizing signal through a line 48 and a vertical synchronizing signal through a line 49 for transmission for the CRT 22. The same supplies a display timing signal through a line 51 to a multiplexer 47 and an AND circuit 47, through a line 51. The cursor display signal is supplied to an OR circuit 58, through a line 59. The refresh memory address is supplied through a bus line 45 to the multiplexer 47 and a comparator 63. The raster address is supplied to a multiplexer 55 and a raster address converting circuit 57 through a bus line 46. The multiplexer 47 receives an address from the system bus 10 and a refresh memory address signal for reading which is outputted from the CRT controller 44, and selectively produces either of those.

Of those address information inputted to the multiplexer 47, an address supplied through the system bus 10 is a write address used when display data is written into the refresh memory (RM1) 52. The address inputted from the CRT controller 44 is a read out address for reading out the display data from the refresh memory 52. The refresh memory (RAM) 52 is connected to the multiplexer 47 and is connected to the system bus 10 through a gate 53. The refresh memory 52 is comprised of a random access memory and stores the display information of one picture, for example, 1024 characters. Address information inputted through the multiplexer 47 reads out coded data from the refresh memory 52 and applies it to a character generator 54. The gate 53 is a control gate for applying the display data coming through the system bus 10 to the refresh memory 52, in response to the write signal from the CPU 12. The character generator 54, as a read only memory, is connected to the refresh memory 52 and a multiplexer 55. The character generator 54 converts the coded data into corresponding character information in response to the address information which is the combination of the display data and the raster address inputted from the CRTC 44 through the multiplexer 55. The multiplexer 55 connecting to the CRT controller 44 is supplied with raster address converting information applied through a bus line 46 and a raster address through the bus line 56. The multiplexer 55 is supplied with the most significant bit information outputted from the multiplexer 47, through a line 60. The same information is applied to the bidirectional shift register 43. When the most significant bit information of the address is logical "0", the multiplexer 55 selects and produces the raster address through the bus line 46. When it is logical "1", the multiplexer 55 selects and produces the raster address converting information. In the bidirectional shift register 43, when the most significant bit of the address is logical "0", the display information is shifted to the right. When it is logical "1", the display information is shifted to the left. The raster address converting circuit 57 is comprised of an inverter and is connected to the CRT controller 44. The raster address converting circuit 57 inverts the raster address information supplied from the CRT controller 44 and the converted one is supplied to the multiplexer 55.

The bidirectional shift register 43 is connected to the oscillator circuit 41, the dot counter 42, and the character generator 54. Having the output signal from the dot counter the shift register 43 fetches the character pattern information from the character generator 54 and responds to the signal outputted from the oscillator circuit 41 to shift its contents to the right or to the left. The selection of the right shift or the left shift depends on the control signal (the most significant bit of the address information of the refresh memory 52) outputted from the multiplexer 47. When the most significant bit (MSB) is logical "0", it is shifted to the right, for example, and when the MSB is logical "I", it is shifted to the left. The inverse shift direction in this case is of course allowed, if necessary.

To the bidirectional shift register 43 is connected an OR circuit 58. The OR circuit 58 is supplied with a cursor display signal from the CRT controller 44.

The OR circuit 58 is connected to the AND circuit 67. The AND circuit 67 is supplied with a display timing signal from the CRT controller 44 through the line 51.

Accordingly, at the timing of the signal display timing inputted, it produces the display character pattern information shifted out to the right from the bidirectional shift register 43 or that shifted out to the left from the same.

In this way, the display character pattern information outputted from the OR circuit 58 is supplied to the CRT 22 where it is visualized.

The programmable interface element (PIE) 61 is connected to one input terminal of the comparator 63 through line 62 and the comparator 63 is supplied at the other input refresh memory address from the CRT controller 44 through the line 45.

The programmable interface element (PIE) 61 has an input/output interface function between the system bus 10 and the related periphery equipments (not shown). The data may be programmably inputted and outputted to and from the PIE 61 having buffers of 3 by therein. Those 3-byte buffers may be used corresponding to a cursor start raster address register, a cursor end raster address register, and a cursor register (H) or (L). It has three ports 71 to 73, as shown in Fig. 5. Those ports 71 to 73 have the functions changeable programmably. The port 71 has a single 8-bit data output latch/buffer and a single 8-bit data input latch. The port 72 has a single 8-bit data input, an output latch/buffer, and a single 8-bit input buffer. The port 73 has a single 8-bit data output latch/buffer, and a single 8-bit data input buffer (the input has no latch). The port 73 may be divided into ports 72₁ and 72₂ each of 4 bits by a mode control. Each 4-bit port is a 4-bit latch and is used for the output of the control signal or the input of the status information, in combination with the port 71 or the port 72. Further, included are a data buffer 74, a read/write control logic 75, and port control sections 76 and 77. Receiving the control word from an internal data bus (not shown) under control of a command from the read/write control logic 75, the port control sections 76 and 77 produces commands to the ports designated.

In the embodiment of the invention, the programmable interface is constructed by 8255A sold by Intel Co. in U.S.A. and the operation and timing in each mode is described in "Intel 8080 Microcomputer System User's Manual" published by the same company on Sept., 1975.

The comparator 63 compares the refresh memory address from the CRT controller 44 with the contents of the cursor address set in the buffer in the programmable interface element 61 and applies an output as a corresponding cursor signal to an OR gate 58. The AND gate 67 is conditioned by the output from the OR gate 58 and the display timing through the line 51 from the CRT controller 44 and applies an output signal as a video signal to the CRT 22.

The output signal from the comparator 63 is coupled with the OR gate 58 through a control line 66. The output of the OR gate 58 is connected to one input terminal of an AND gate 67 of which other input terminal is connected to the CRT controller 44 through a control line 51. The output of the AND gate 67 is connected to the CRT 22.

The CRT controller 44 includes a cursor start raster address register, a cursor end raster address register (not shown) and a cursor register (not shown), with relation to the invention. The former is for programming the end raster address of the cursor display and the start address of the cursor display, and the latter is for programming a current address to display the cursor. The latter register allows the read/write operation from the CPU 12. The cursor address programmed is compared with the internal address generated from an address generator (not shown) and a coincident signal is applied to the cursor control section (not shown). The cursor control section provides a cursor display signal which is a video signal for displaying a cursor on the CRT display screen. This signal is inhibited during a period of time that the display timing signal is logical "0". Normally, the signal is mixed with the character video signal and the mixed one is supplied to the CRT display unit.

Fig. 6 is logic diagram of the bidirectional shift register 43 shown in Fig. 4. The embodiment employs an 8-bit parallel access right left shift register (SN74198 sold by Texas Instrument Co. in U.S.A. or the equirment). The shift register has all the functions required for the shift register, and has a parallel input, a parallel output, a right shift input, a left shift input, an operation mode control input and a direct clear input. By an operation mode control input (Sl or SO), the following modes may be selected: <ul id="ul0003" list-style="none"><li>(1) Parallel load</li><li>(2) Shift right</li><li>(3) Shift left</li><li>(4) Clock inhibition (no operation is made)</li></ul>

In the parallel load, the 8-bit data is applied to the inputs A to H and is stored in the respective floppy discs by clocking. In the shift right mode, the data is shifted to the right at the leading edge of the input clock pulse. At this time, the serial data is applied to the shift right terminal. In the shift left mode, the serial data applied to the shift left terminal is shifted to the left by the input clock pulse. For inhibiting the clocking of the flip-flop, logical "0" of signals SO and Sl is applied, as in the following table.