Arrangement for controlling voltage generators in multi-voltage generator chips such as DRAMs

Cross-reference to related registrations

The This application is filed on 27 March 1998 Provisional Application Ser. 60 / 079,717 used and removed her and has the same inventor and successor to.

invention field

The This invention relates to an arrangement for controlling the Operation of various phases of chips such as DRAM chips (Dynamic Random Access Memory) used multi-voltage generator system.

State of the art

Modern have chips such as DRAM chips (Dynamic Randon Access Memory) many different voltages to the one on the chip by Most have to be produced by generators in terms of their Order of start times, etc. during different phases of operation must be controlled.

In the issued on 7 June 1994 US Pat. 5,319,601 (Kawata et al.) discloses a power supply start-up circuit for a DRAM is disclosed wherein a rise time of an intermediate potential is made short after the power and the power consumption is kept low. The power supply circuit includes both a Power-detection circuit, which detects when an external power supply potential, a predetermined reached potential and produces first and second detection signals, and an internal power supply circuit, an internal power supply potential generated. The power supply circuit further comprises a first intermediate potential generating circuit, a first intermediate potential from the external power supply potential generates and supplies an intermediate potential supply node it. If the first detection signal is generated, and the first intermediate potential reaches a predetermined potential, stops the first intermediate potential generating circuit both the feed the first intermediate potential to the intermediate potential supply node as the intermediate potential generating function. From a second Intermediate potential generation circuit is a second intermediate potential generated from the internal power supply potential and if the second recognition signal is generated, the second intermediate potential fed to feeder node. The first intermediate potential generating circuit has a larger drive capacity than that of the second intermediate generating circuit, resulting in a shortening of Rise time of the intermediate potential after the power and enables reduction of total electricity consumption.

Now on <figref idrefs="S27">1</figref> Referring there is a block diagram of a Generator control arrangement <figref>10</figref> of the prior art shown for controlling generators that tensions in example a DRAM chip (Dynamic RAM) generate. The order<figref>10</figref> includes a turn-on <figref>20</figref>, A generator system (GENERATORS) <figref>22</figref>. the reference voltage generators (REF. VOLT.) <figref>23</figref> and a Plurality of (not shown) voltage generators, initialization circuits <figref>24</figref>. Pull-up circuits <figref>26</figref> and first and second OR gate arrangements <figref>28</figref> or. <figref>30</figref> includes. It is understood that the Pull-up circuits <figref>26</figref> and the first and the second OR gate arrangement <figref>28</figref> and <figref>30</figref> in dependence of the number of parallel by the pull-up circuits <figref>26</figref> and OR gate arrangements <figref>28</figref> and <figref>30</figref> received and processed signals, one or more of such circuits or Gates include.

signals Contact points and locations for the associated Chip in the pull-up circuits <figref>26</figref> receive. In the pull-up circuits <figref>26</figref> an output signal is standard on a logic high level (logic "1") kne gen when an input connection point not connected is, and it is a logical "0" is output when the input signal is active from the junction or connection is pulled down. The output signals from the Pull-up circuits<figref>26</figref> will in the first OR gate arrangement <figref>28</figref> with test mode register signals logically combined in the accompanying initialization circuits <figref>24</figref> initialized have been. The outputs from the first OR gates<figref>28</figref> are to first inputs the startup circuit <figref>20</figref> and the generator system <figref>22</figref> coupled. The test mode register signals are also associated initialization circuits <figref>24</figref> initialized and then to the generator system <figref>22</figref> coupled. signals from (Not shown) backups on the associated chip are in the accompanying initialization circuits <figref>24</figref> initialized and in the reference generators <figref>23</figref> of the generator system <figref>22</figref> coupled. The safety signals are also the second OR gate arrangement <figref>30</figref> logical with the input test mode register signals combined and then to the generator system <figref>22</figref> coupled. The startup circuit <figref>20</figref> receives the outputs of the first OR gate arrangement <figref>28</figref> and various signals of the initialization circuits <figref>24</figref> and generates output control signals as well as the initialization circuits <figref>24</figref> and the generators of the generator system <figref>22</figref>, The generator system<figref>22</figref> includes a plurality of voltage generators, including the Bezugsgenera&lt;?page 3?&gt;tors <figref>23</figref> and receives an external voltage (VEXT), system signals (SYS. SIGS.) and the Signals from each of first and second OR gate arrangement <figref>28</figref> and <figref>30</figref>. the initialization circuits <figref>24</figref> and the startup circuit <figref>20</figref> and generates output signals at the initialization circuits <figref>24</figref> and the various remote from the circuits on the associated chip required (not shown) voltages.

to Control the operation of these generators are many logic control circuits involved the generator functions, which conventionally by the entire generator system <figref>22</figref> within the (not shown) individual genes ratorblöcke arranged distributed (not shown) local logic circuits are performed. The conventional generator system <figref>22</figref> is the result of a growth process, why whenever new voltage levels and the associated generator blocks were added or whenever control functionality needed to be changed, additional Logic circuits locally were added.

It is desirable provide an arrangement wherein control of voltage generators by on a chip the need for distributed array of logic circuits is avoided in the entire generator system and a flexibility to reflect all changes allows is that for future amendments the generator system or chips may be needed.

Summary of the Invention

The present invention is directed to an arrangement for controlling the various operating modes of the DRAM (Dynamic Access randon Memory) and other modules having a plurality of generator units for Generating various voltages required by the module used voltage generator system.

Out considered one aspect, the present invention is directed on a chip comprising a generator system including a plurality of voltage generating circuits and a centralized generator control arrangement. The central generator control arrangement comprises a to each of the plurality of voltage generating circuits and to predetermined devices on the chip coupled control. The control reacts to signals from the predetermined devices on the chip for generating a predetermined sequence of output control signals to the individual generating circuits for each of at least two separate Operating phases of the generator system. Any predetermined sequence of Output control signals controls the logic operation sequence of the plurality of Generating circuits and the predetermined devices on the Chip in defined time periods to generate the required stable Voltage outputs from the plurality of generating circuits to predetermined circuits on the chip.

Out considered another aspect is directed the present Invention to a DRAM chip (Dynamic Randon Access Memory) with a Generator system having a plurality of voltage generating circuits and for generating voltages to predetermined other generating circuits and to other devices on the chip, and a centralized generator control arrangement. The central generator control arrangement includes one of each of Plurality of voltage generating circuits and to predetermined of the other devices on the chip coupled control. The Controller is responsive to occurrences in the plurality of voltage generating circuits and signals from the predetermined ones of the other devices on the Chip for generating a predetermined sequence of Ausgangssteueuerungssignalen to the individual generating circuits for each of at least two separate Operating phases of the generator system. The predetermined sequence of Output control signals controls the logic operation sequence of the plurality of Generating circuits and the predetermined devices on the Chip in defined time periods to generate the required stable Voltage outputs from the plurality of generating circuits to predetermined circuits on the chip.

The Invention will be apparent from the following detailed description in Conjunction with the accompanying drawings and claims easier to understand.

Brief Description of Drawing

<figref idrefs="S27">1</figref> is a block diagram of a generator control arrangement of the prior the technique for controlling voltages in multi-generator chips as For example, dynamic RAM chips;

<figref idrefs="S28">2</figref> is a block diagram of an exemplary centralized generator control arrangement for Controlling various voltage generators More Generator Chips such as a dynamic RAM chip in accordance with the present invention;

<figref idrefs="S29">3</figref> is a block diagram of an exemplary voltage generator system according to the present Invention having a plurality of voltage generators on a More generator chip such as &lt;?page 4?&gt;For example, a dynamic RAM, the by the central generator control arrangement of <figref idrefs="S28">2</figref> controlled will;

<figref idrefs="S30">4a</figref> and <figref idrefs="S31">4b</figref> show a start-up sequence table illustrating an exemplary Starting sequence for controlling the generator assembly of <figref idrefs="S29">3</figref> by the exemplary centralized generator control arrangement of <figref idrefs="S28">2</figref>; and

<figref idrefs="S32">5</figref> shows an exemplary arrangement for a State machine in the exemplary centralized generator control arrangement the <figref idrefs="S28">2</figref>,

Detailed description

Now on <figref idrefs="S28">2</figref> Referring there is a block diagram of a exemplary (within a rectangle shown with a dashed line) central generator control arrangement <figref>40</figref> to control various (in <figref idrefs="S29">3</figref> shown) voltage generating circuits an integrated circuit chip having multiple voltage generator circuits such as a Dynamic RAM chip according to the present Invention. The central generator control arrangement<figref>40</figref> includes a (shown within a rectangle with a dashed line) control <figref>50</figref>, An oscillator <figref>42</figref> for providing of clock signals for the control <figref>50</figref> and a voltage detector circuit <figref>44</figref>. the S ignale from the controller<figref>50</figref> receives and control signals generated for controlling <figref>50</figref> back transfers. The control <figref>50</figref> comprises a state machine <figref>52</figref> and an AND gate <figref>54</figref>, The state machine<figref>52</figref> is a well-known device that comprises a processor which a (not shown) memory used, the Pogrammanweisungen for operating the processor stores in a predetermined manner.

Now on <figref idrefs="S32">5</figref> Referring can the state machine <figref>52</figref> as Alternative input logic circuits <figref>70</figref>, Output logic circuits <figref>72</figref> and State memory circuits <figref>74</figref> include. The input logic circuits<figref>70</figref> and Output logic circuits <figref>72</figref> generally receive all logical input signals to control (eg., signals of pads / testing, Test mode register, fuses and voltage detection circuits <figref>44</figref>) and provide necessary logic functions via the use of various Gate ready to produce accurate output control signals. The state memory circuits <figref>74</figref> can flip-flops (not shown) comprise the signals from the input logic circuits <figref>70</figref> and Other signals such as reset signals and clock signals received and sufficient outputs to the input and output logic circuits <figref>70</figref> and <figref>72</figref> produce.

Now to <figref idrefs="S28">2</figref> returning receives the state machine <figref>52</figref> the clock signals from the oscillator <figref>42</figref>. Control signals from the voltage detector circuit <figref>44</figref> and Signals from various fuses, relays and inspection services and test mode registers and generated based on the encountered in its memory Program instructions outputs. From the AND gate<figref>54</figref> are clock enable signals and predetermined output signals from the state machine <figref>52</figref> receive and output signals, the other with predetermined output signals the state machine <figref>52</figref> are combined to static Enable and configuration output signals "C" of the cent ral generator control arrangement <figref>40</figref> form, the transferred to different to be controlled voltage generating circuits will. Hereinafter, an exemplary operation of the controller<figref>50</figref> in Connection with a description of <figref idrefs="S30">4A</figref> and <figref idrefs="S31">4B</figref> described.

From the voltage detector circuit <figref>44</figref> is an external supply voltage (in <figref idrefs="S29">3</figref> VEXT shown) and certain of by a predetermined Plurality of (in <figref idrefs="S29">3</figref> shown) generating circuits measured voltages generated and corresponding signals to control <figref>50</figref> Posted, once these voltages have reached their specific threshold. It is understood that to perform these functions, any suitable well known voltage detection circuits are used can.

Now on <figref idrefs="S29">3</figref> Referring there is a block diagram of a exemplary (within a rectangle shown with a dashed line) central voltage generator system <figref>100</figref> according to the present Invention. The system<figref>100</figref> includes a plurality of voltage generating circuits <figref>111</figref>-<figref>124</figref> (GEN. 1 to GEN. 14) on a multi-generator chip such as a dynamic RAM chip by the central generator control arrangement <figref>40</figref> the <figref idrefs="S28">2</figref> being controlled. In the exemplary voltage generator system <figref>100</figref> receives each the voltage generating circuits <figref>111</figref>-<figref>124</figref> a separate Control signal "C" from the controller <figref>50</figref> the <figref idrefs="S28">2</figref> and a predetermined external voltage (VEXT). It is understood that to simplify the drawing, the control signal "C" and the predetermined external voltage (VEXT) as to each of the voltage generating circuits <figref>111</figref>-<figref>124</figref> over a individual input conductors are shown applied. In reality these inputs each of the voltage generating circuits <figref>111</figref>-<figref>124</figref> over a separate conductor provided. In addition to the control signal "C" and the predetermined external voltage (VEXT) it is shown that an output (V3) of the voltage generating circuit <figref>113</figref> at each of the voltage generating circuits <figref>115</figref>-<figref>124</figref> is&lt;?page 5?&gt;puts will and an output (V6) from the voltage generation circuit <figref>116</figref> as entry for the voltage generating circuit <figref>123</figref> provided.

In the exemplary voltage generator system <figref>100</figref> responds the voltage generating circuit <figref>111</figref> (GEN. 1) on the dedicated control signal "C" from the controller <figref>50</figref> and the predetermined external voltage (VEXT), for generating both a first output voltage (V1A) that everyone on both first inputs the voltage generating circuits <figref>112</figref> (GEN. 2) and <figref>113</figref> (GEN. 3) is coupled, and a second output voltage (V1B) the second connected to an input of the voltage generating circuit <figref>112</figref> is coupled. The voltage generating circuit <figref>112</figref> responding to the first and second voltages V1A and V1B from voltage generating circuit <figref>111</figref>. the certain for Control signal "C" and the predetermined external voltage (VEXT) for generating an output voltage (V2) the second connected to an input of the voltage generating circuit <figref>113</figref> and inputs each of the voltage generating circuits <figref>114</figref> (GEN. 4) and <figref>115</figref> (GENE. 5) is coupled. The voltage generating circuit<figref>113</figref> responds on it certain control signals "C", the predetermined external voltage (VEXT) and the voltage generating circuits <figref>111</figref> and <figref>112</figref> received Voltages V1A and V12 for generating an output voltage (V3) as inputs to voltage generating circuits <figref>115</figref>-<figref>124</figref> and as an output signal from the voltage generator system <figref>100</figref> provided will.

The Voltage generating circuit <figref>114</figref> responds to the dedicated Control signal "C", the predetermined external voltage (VEXT) and from the voltage generating circuit <figref>112</figref> received Voltage V2 to generate an output voltage (V4), which as an output the voltage generator system <figref>100</figref> provided. The voltage generating circuit<figref>115</figref> responds on it specific control signal "C", the agreed vorbe external voltage (VEXT), which from the voltage generating circuits <figref>112</figref> and <figref>113</figref> received Voltages V2 and V3 for generating an output voltage (V5), the input signal to the voltage generation circuit <figref>116</figref> (GENE. 6) is provided. The voltage generating circuit<figref>116</figref> responds on it certain control signal "C", the predetermined external voltage (VEXT), which from the voltage generating circuits <figref>113</figref> and <figref>115</figref> received Voltages V3 and V5 for generating an output voltage (V6) as an input signal to the voltage generating circuits <figref>117</figref> (GENE. 7) and <figref>123</figref> (GEN. 13) is provided. The voltage generating circuit<figref>117</figref> responds on it certain control signal "C", the predetermined external voltage (VEXT), which from the voltage generating circuits <figref>113</figref> and <figref>116</figref> received Voltages V3 and V6, respectively for generating an output voltage (V7), as an input signal to the voltage generating circuits <figref>118</figref>. <figref>121</figref>. <figref>122</figref>. <figref>123</figref> and <figref>124</figref> provided is.

The Voltage generating circuit <figref>118</figref> (GEN. 8) to respond the for certain control signal "C", the predetermined external voltage (VEXT), which from the voltage generating circuits <figref>113</figref> and <figref>117</figref> received Voltages V3 and V7 for generating an output voltage (V8) as an input signal to the voltage generating circuits <figref>119</figref> (GENE. 9) and <figref>120</figref> (GEN. 10) is provided. The voltage generating circuit<figref>119</figref> responds on it certain control signal "C", the predetermined external voltage (VEXT), which from the voltage generating circuits <figref>113</figref> and <figref>118</figref> received Voltages V3 and V8 for generating an output voltage (V9) as output by the voltage generator system <figref>100</figref> provided is. The voltage generating circuit<figref>120</figref> responds to the for certain control signal "C", the predetermined external voltage (VEXT), which from the voltage generating circuits <figref>113</figref> and <figref>118</figref> received Voltages V3 and V8 for generating an output voltage (V10) as output from the voltage generator system <figref>100</figref> provided is. The voltage generating circuits<figref>121</figref> (GEN. 11), <figref>122</figref> (GEN. 12) and <figref>124</figref> (GEN. 14) each responsive to the dedicated Control signal "C", the predetermined external voltage (VEXT), which from the voltage generating circuits <figref>113</figref> and <figref>117</figref> received voltages V3 or V7 for generating output voltage V11, V12, V13 or V14 that from as outputs voltage generator system <figref>100</figref> provided will. The voltage generating circuit<figref>123</figref> (GEN. 13) responds to the dedicated Control signal "C", the predetermined external voltage (VEXT), which from the voltage generating circuits <figref>113</figref>. <figref>116</figref> and <figref>117</figref> received voltages V3, V6 and V7 to generate the output voltage V13, as output signals the voltage generator system <figref>100</figref> provided.

the Spanungsgeneratorsystem <figref>100</figref> can generator systems modern DRAM chips and synchronous DRAM chips are assimilated, having more than 10 voltages on the chip by many Voltage generating circuits are produced. These tensions comprise a plurality of reference voltages (z. B. for input / output and receiver for bias current generation in analog circuits) as well as several voltages different (Not shown) function blocks of the DRAM with high or low operating current (for. example, for sense amplifiers or Word line driver) supply. Basically there are three different Operating phases for the various Erzeugungsschaltun&lt;?page 6?&gt;gene in the voltage generator systems <figref>22</figref> the <figref idrefs="S27">1</figref> and <figref>100</figref> the <figref idrefs="S29">3</figref> instead of, as (a) a normal operation phase, (b) a test and burn-in phase, and (C) a switch-on can be displayed.

While a drop to "normal" phase in one of the generator systems <figref>22</figref> the <figref idrefs="S27">1</figref> or <figref>100</figref> the <figref idrefs="S29">3</figref> must they Generating circuits (z. B. generating circuits <figref>111</figref>-<figref>124</figref> the <figref idrefs="S29">3</figref>) guarantee that all voltages provided on the chip are stable, and that all necessary (not shown) of several Power grids currents taken performed on the chip will. Furthermore, it must be ensured to whoever that generation circuits even too much electricity use (eg. as bias in differential amplifiers and Current through resistor divider). Power grids, the peak currents (eg. B. for read operations) supply must be, therefore usually of one or more of several types of generating circuits such as a stand-by generating circuit, an active generating circuit and a peak current generating circuit fed. The stand-generating circuit is always on and can supply only little current, but consumes also own little power. Their purpose is to Entertainment the voltage level during the Times and phases when the chip is not active. An active generating circuit is only activated when the chip performs a function that requires power from a corresponding mains. The active generation circuit can a large current supply, but also consumes a larger current. To activate an active generating circuit are also of the generator system <figref>22</figref> the <figref idrefs="S27">1</figref> or the control <figref>50</figref> the <figref idrefs="S28">2</figref> signals from other chip functions (eg. as the sense amplifier enable signals that the sense amplifier activate) (not shown in the figures) evaluated to the active To enable generating circuit. At times, a peak current generating circuit to used to supply high peaks of current from a power grid is removed. A peak current generating circuit may for example only a transistor switch between a respective power network and either an external voltage supply (VEXT) or a current source for this Electricity mains. Peak current generating circuits are briefly turned on at the exact instant when the peak current of is taken from the mains. The peak current generating circuits usually have even no regulation function, but the final settlement of the voltage is it mentioned by a top active generating circuit performed. To turn the peak current generating circuits at the right moment, signals from other chip functions with the generator system connected (z. B. the sense amplifier enable signals).

furthermore there is an interaction between the voltage generating circuits for different Power grids. For example, if a first voltage generating circuits (Z. B. generating circuit <figref>123</figref>) Responsive to a voltage for word line boost the DRAM chip provides to restore a full voltage level is active, then this voltage generation circuit sends a signal to a second of the predetermined voltage generating circuits (Z. B. generating circuit <figref>116</figref>). This signal will prevent that the second of the predetermined voltage generating circuits is turned off because the first one of the voltage generating circuits itself Current from the second one of the voltage generating circuits consumed. Since a DRAM chip often for used memory devices with different configurations can be that different drive capabilities of certain voltage generating circuits require, need configures the voltage generating circuits for these situations be. This is done by contact points or by fuses, where the information of the contact points and / or fuses to conventional generator system <figref>22</figref> the <figref idrefs="S27">1</figref> or the control <figref>50</figref> the <figref idrefs="S28">2</figref> transfer will.

to Control these generating circuits during the different Operating phases in conventional Voltage generator system <figref>22</figref> the <figref idrefs="S27">1</figref> are many Logic control circuits to the generating circuit functions involved, through the entire generator system <figref>22</figref> distributed and disposed within the individual (not shown) generating circuit blocks (Not shown) local logic circuits are performed. As a result, includes the conventional Voltage generator system <figref>22</figref> a complex control scheme. According to the present Invention are logic control circuits no longer of any generating circuits <figref>111</figref>-<figref>124</figref> distributed. Instead of which receives the state machine <figref>52</figref> the control <figref>50</figref> all input signals and is for providing individual control signals for each of the generating circuits <figref>111</figref>-<figref>124</figref> programmed to the applicable generation circuits <figref>111</figref>-<figref>124</figref> to predetermined times during each of the possible Operating phases on or off. It is understood that the program for the state machine <figref>52</figref> for each phase of operation is so far arbitrary that a designer a desired Operating result for any must define operational phase. Once such an operating phase is determined, it can easily in a corresponding program instruction sequence for the state machine <figref>52</figref> are converted, the appropriate the Function of the generator system <figref>100</figref> in response to through the state machine <figref>50</figref> received predetermined input&lt;?page 7?&gt;signals causes.

In a test and burn-in phase must of the generation circuits over many their normal operation beyond additional functions are performed. For example, can be a function that certain or all generating circuits for audit purposes can be locked. A second function may be that certain voltages in comparison be set to normal operation to a different value. A third function may be that certain time constants in the generating circuits, which determine their dynamic behavior, to determine the best value for optimum amended chip functions can be. A fourth function may be that to stress the chip (Burn-in test) most internal voltages to a higher value than in normal operation must be set, which by setting VEXT to a higher value and allowing an internal reference voltage follows the increase of the external voltage, accomplished can be.

A Switch is used as a transition state defined as where the external voltage VEXT has already been applied to the chip is but the internal voltages have not provides Herge. For the Switch there are two main requirements. These requirements are that they must be short (z. B. 100 microseconds), and that they must take place in a well defined way. To Switch must be kept short more additional Functions from the generator system <figref>100</figref> be performed. As with any power supply in a short time from zero volts to their respective levels need to be recharged, the driving ability is more Generating circuit blocks unsatisfactory. There are several potential solutions to overcome this problem. First, while a first phase of the switch-grids by transistor switch shorted to VEXT until they have almost reached their target value. Then, these switches are opened again and the regulation of this Voltage is taken from the respective generating circuit block. As second is the driving ability some generating circuits (z. B. pump circuits) of the frequency driving of these pump circuits oscillators depends. During the Switch are high-frequency oscillators with the pump circuits together to enable fast pumping operation and then, after the switch slower oscillators to drive these pump circuits used and the fast oscillators are turned off to save power. In general, a control at the output of<figref>50</figref> -supplied static enable signal for enabling a generating circuit block (Z. B. in the switch, or to turn off the same during a used Prüfmodusphase) and this signal is not time-critical. To change the behavior of a or more predetermined generating circuit blocks specific manner, such as by changing its voltage level (Trim) Change its driving ability changing its internal time constants or specific functions for test modes are configuration signals at the output of the controller <figref>50</figref> used. These signals are also not time critical and change not while the normal operation of the chip. It is understood that within the generator Systems <figref>100</figref> dynamic enable signals and message signals be generated. Dynamic enable signals to activate a used generating circuit when the control of its output voltage start must, or must begin to generate electricity (z. B. peak generating circuits). These signals are time critical and not every generating circuit requires such input signal (z. B. a standby generating circuit). Message signals are used for communicating between generating circuit blocks Signals inform the example of a generating circuit can that their input pump voltage level is not yet established and that the pump voltage supplying pumping generating circuit is still running. Thereby causing the generating circuit shutdown their delayed although a dynamic enable signal been for already shut is. These signals are also time critical and not every generating circuit requires such input signal.

Now Referring to <figref idrefs="S30">4A</figref> and <figref idrefs="S31">4B</figref> is there is a start-up sequence table illustrating an exemplary Sequence for controlling the generator system <figref>100</figref> the <figref idrefs="S29">3</figref> for Einschaltbetriebsphase by the exemplary centralized generator control arrangement <figref>40</figref> the <figref idrefs="S28">2</figref> shown. in the section <figref>200</figref> of the table is the external voltage (VEXT) applied to the chip to begin the sequence. By applying of VEXT to the chip causes the state machine <figref>52</figref> in the control <figref>50</figref> predetermined (in <figref idrefs="S28">2</figref> not shown) flip-flops in the controller <figref>50</figref> resets and a signal "V6on" in the low State offset so that circuits that the signal "V6on" of the control <figref>50</figref> receive, remain inactive. At this time, the generating circuit<figref>111</figref> activated to begin generating the voltages V1A and V1B, the generating circuit <figref>112</figref> is activated with the generation the voltage V2 to start, the generating circuit <figref>113</figref> becomes activated to start generating the voltage V3, the generating circuit <figref>114</figref> is activated with the generation the voltage V4 to start, the generating circuit <figref>115</figref> becomes to generate V5 and for causing an initial &lt;?page 8?&gt;Pull downs a (not shown), the node is activated, the generating circuit <figref>117</figref> becomes to generate V7 and providing an initial activation of a (Not shown) gain switch is activated, the generating circuit <figref>116</figref> is activated and in the standby mode offset to a signal V6acc (V6 active) and V6sbm (V6 stand-by mode) to produce, the generation circuit <figref>118</figref> is activated, to start the generation of the voltage V8, the signal V6osb (V6 started to standby / V6 on standby), the generating circuit <figref>119</figref> starts with the generating the voltage V9, and the generating circuit <figref>120</figref> starts with the generation of the voltage V10. In the controller<figref>50</figref> becomes a Backup storage signal "bFINIT" (bFuse Initialize Initialization b-fuse) is placed in a low state while a Signal "bFSET" (bFuse Set-Set b-assurance) is placed in a high state. The signals "bFINIT" and "bFSET" are exemplary signals for Fuses on the chip. The information of these fuses not applied to the chip, but in the exemplary switch- could this fuse information into predetermined (not shown) flip-flop For example, in the control <figref>50</figref> are stored. This are two fuse signals which a certain timing with respect to its High or low walking require the storage of backup information to organize in the predetermined flip-flops or control. Since backups over an entire chip are arranged distributed, it is important to know that the voltage V6 is already well established all over the chip is before the backup information is stored, otherwise could a logic "0" are stored, if it is actually a logical "1", because the circuits and these circuits supplying voltage are not yet stable.

in the section <figref>201</figref> the table, the control waits <figref>50</figref> a predetermined number of X clock cycles (eg., X = 10) to which Time it is known that the voltage V6 from the generating circuit <figref>116</figref> (the section <figref>200</figref> activated and in the standby mode has been added) should have reached a predetermined level. In section <figref>202</figref> of the table is by the voltage detector <figref>44</figref> recognized that V13 (control of generating circuit <figref>123</figref>) On a required level (low or high), and the voltage detector <figref>44</figref> recognizes, that the voltage V6 a predetermined high threshold has been reached, the voltage detector <figref>44</figref> transmits a signal for controlling V6DET <figref>50</figref>. which indicates that the voltage V6 across the entire chip away is well constructed. In section<figref>203</figref> the table when the Control knows that the voltage V6 is at its proper level, it waits for more X clock cycles before with section <figref>204</figref> starts. In section<figref>204</figref> the Table, the signal "V6on" in control <figref>50</figref> high and the driving ability the voltage V3 is decreased, the voltage V5 is not longer in the pull-down state and the activation of the voltage V7 of the gain switch is turned off. At the beginning of the switch is assumed that the generating circuit <figref>117</figref> a large V7 drive capability requires that by their gain switch section <figref>200</figref> is activated and then the section <figref>204</figref> reduced , when the large driving ability no longer is required.

in the section <figref>205</figref> Table generates the control <figref>50</figref> on Signal "V14sbct" (V12 stand-by circuit - maintained mode) and the generating circuit <figref>124</figref> begins with the generation the voltage V14. In section<figref>206</figref> generates the table the control <figref>50</figref> Signals "V13acct" (V13 active circuit - activation circuit) and "V13sbct" (V13 stand-by circuit - maintained mode) whereby the generation circuit <figref>123</figref> activated and in the Standby mode is set. In section<figref>207</figref> the Table generates the control signals and the backup storage Signal bFINIT goes high. In section<figref>208</figref>-<figref>211</figref> the Table traverses controlling a waiting order for Y clock cycles (section <figref>208</figref>) By bFSET relies on low (Section <figref>209</figref>), And Z clock cycles waiting (section <figref>210</figref>) before bFSET on high sets (Section <figref>211</figref>). It is understood that the signals bFINIT bFSET and to other circuits on go the chip and not to any of the generating circuits <figref>111</figref>-<figref>124</figref>, there has not shown that generating circuits any acts in the column labeled "Generator circuits" perform. The signals through the bFINIT and bFSET triggered flip-flops are generally by intermediate circuits controlled and these circuits require a special timing the signals bFINIT and bFSET.

at the current, in <figref idrefs="S29">3</figref> shown genset <figref>100</figref> becomes assumed that the generating circuit <figref>123</figref> a pump generator with an associated is power network that receives the VEXT voltage (which by default only a predetermined maximum value may have) and this input voltage pumped to a negative Output V13 (z. B. -0.5 Volt) provide. Similarly , It is assumed that the generating circuit <figref>122</figref> on Pump generator that receives the VEXT voltage and this input voltage inflated to V15 (z. B. 3.5 volts) to provide a positive output signal. In section <figref>212</figref> Table reaches the voltage V13 from the generating circuit <figref>123</figref> its predetermined level and it is generated (V13 Limit Limit) a detection signal V13LMT, causes the that the control <figref>50</figref> from "V13acct" (from section <figref>206</figref>) goes low and the activation signal "V13ac" in the generating circuit <figref>123</figref> switched off is. in the&lt;?page 9?&gt;section <figref>213</figref> Table generates the control <figref>50</figref> on Control signal "V12poct" (V12 Power-On Circuit turn-on), Walking on high, and the generating circuit <figref>122</figref> assigned (Not shown) power network is started. In section<figref>214</figref> the Table has been found that the voltage V12 a predetermined Level (85%) has reached the value of the voltage V6, and a signal V12DET (V12 detection) by the voltage detector <figref>44</figref> goes to a predetermined high value. This generates the control <figref>50</figref> the Signal V12poct (from section <figref>213</figref>) That goes low and causes the power network of the generating circuit <figref>122</figref> off is. In section<figref>215</figref> of the table is of the control a "V12acct" and "V12sbct" is generated on the Goes high, which in turn, causes the generating circuit <figref>122</figref> activated and is placed in the standby state. The reason for sections<figref>212</figref>-<figref>215</figref> the Table is that pump generating circuits <figref>122</figref> and <figref>213</figref> not are turned on and immediately from 0 volts to their true can go output voltage much higher is or lower than the VEXT applied voltage. this requires thus lengthening of turning these types of generating circuits. For example must the generating circuit <figref>123</figref> assigned (not shown) electricity network are pulled up to a certain level, for example, 85% of the voltage V6 from the generating circuit <figref>116</figref> amounts, and only then the pump generating circuit <figref>123</figref> to function properly begin. This is done by turning on a (not shown) Apparatus with the designation "V13 power" circuit which itself a pump and the power network of the generating circuit <figref>123</figref> on a high state draws. Once the network a predetermined Level has been reached, the network is turned off and the pump generating circuit <figref>113</figref> starts the company.

in the section <figref>216</figref> Table control generates a control signal "V8frct" (V8 feedback regulator circuit - feedback regulator circuit) which goes high and causes a feedback regulator circuit the generating circuit <figref>118</figref> the operation begins and the Generating the voltage V8 causes. In sections<figref>217</figref>-<figref>220</figref> awaiting the Control 50 × clock cycles long (section <figref>217</figref>) Then generates a control signal "V11acct", which causes the generating circuit <figref>121</figref> the generation of the voltage V11 starts (section <figref>118</figref>), the control <figref>50</figref> waiting back X clock cycles before a control signal "Vdet" (Voltage Detector - voltage detector) generated, the voltage detecting the <figref>44</figref> off because it is no longer needed, and to save bias current that would be used therein. In sections <figref>221</figref> and <figref>222</figref> the table of the control <figref>50</figref> a control signal "PWRON" (Power On-stream A) is activated, indicating that all voltages from generating circuits <figref>111</figref>-<figref>124</figref> stable are (<figref>121</figref>) And the switch-on phase is complete (Section <figref>122</figref>) since the generating circuits have been started and the correct switch-on achieved.

It understood that by a designer similar sequence tables for any required on a chip operating phases are initiated can and then into corresponding program instructions for use by the state machine <figref>52</figref> the control <figref>50</figref> being transformed can, to the generating circuits <figref>111</figref>-<figref>124</figref> for each of the different required operating phases to control.

advantages the current central generator control arrangement <figref>40</figref> consist that the logic control functions and the voltage generating functions are clearly separated. The overall system can therefore be easily checked because all functions are checked individually can and Changes with great flexibility be performed can, by signal aspects of its function without any side effects on other changed functions may be or replaced. In particular, the logic behavior of the system by the specification the state machine <figref>52</figref> determined and changes in logic behavior be easily performed and do not affect the voltage generation circuits. furthermore needed the sequence control for the switch-on operating phase no additional Delay circuits, since all delays the state machine <figref>52</figref> be carried out, since the state machine <figref>52</figref> naturally a "sequencer" is. In addition, the required Initialization of Prüfmodussignalen and backup signals no additional Circuits, as this naturally fits into the state machine <figref>52</figref> is carried out, there needs to be specified that these signals during Power up are not evaluated.

It is to recognize and understand that the above-described specific embodiments the present invention merely illustrative of the general principles of Invention. can from skilled various modifications are carried out, the listed principles correspond. For example, it is understood that similar Sequence tables causes each of the required on-chip operating phases and then into corresponding program instructions for use by the state machine <figref>52</figref> the control <figref>50</figref> to Controlling the generating circuits <figref>111</figref>-<figref>124</figref> for each of the can be converted different operating phases. furthermore is the sequence of the table <figref idrefs="S30">4A</figref> and <figref idrefs="S31">4B</figref> just one exemplary sequence, which for the switch-on can be used and can be obtained by any other &lt;?page 10?&gt;any desired Sequence to be replaced.