Threshold detecting device

The present invention relates to a threshold detection device, in particular for determining whether the so-called booster or supply voltage of a memory device has reached a predetermined threshold value, which allows the execution of various functions.

It is known that to perform functions requiring a high supply voltage, non-volatile memories having a low supply voltage Vcc have a voltage amplifier section for generating a higher output voltage. For example, in the case of flash memories with a supply voltage of only 3 volts, a voltage booster is required to generate the cell read voltage. Since the power amplifier takes some time to turn on to provide the required output voltage, circuitry is needed to determine the output level of the voltage amplifier and to indicate when it reaches the minimum acceptable threshold, ie, by generating an enable signal that allows the high voltage functions to be performed.

Again, since the device undergoes a transient state at power-up prior to reaching the steady-state supply voltage which must be guaranteed in currently used memories to prevent malfunction, a detection circuit is again required to monitor the supply voltage and generate an enable signal the supply voltage reaches a predetermined threshold.

The booster and supply voltage monitoring circuits of known devices are implemented in various ways. A commonly used solution, for example, a differential circuit, wherein an input with a reference or A reference voltage is supplied and wherein another input is supplied with the monitored voltage, and wherein the circuit generates a logic signal whose state depends on the result of the comparison between the two input voltages.

A monitoring device of this kind is z. Disclosed in EP-A-0 260 474, to which the preamble of claim 1 relates.

Although such circuits are widely used, the static consumption of such circuits, ie after evaluation and during steady state operation of the memory or device in which they are integrated, is by far not negligible. In addition, since the supply voltage has not reached the steady state, the reference voltage and the result of the voltage comparison are not reliable, thereby precluding the application of the circuits in the transient state.

It is an object of the present invention to provide a detecting circuit which is intended to overcome the aforesaid drawbacks and which therefore provides a drastic reduction in consumption, as well as having triggering characteristics irrespective of the transient state.

According to the present invention there is provided a threshold detection device as claimed in claim 1.

A number of preferred, non-limiting embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which:

Fig. 1 shows a block diagram of a first embodiment of the present booster voltage monitoring device;

Fig. 2 shows a voltage characteristic with respect to the circuit of Fig. 1;

Fig. 3 is a simplified electrical diagram of the embodiment of Fig. 1;

Fig. 4 is a simplified electrical diagram of a variation of the circuit of Fig. 3;

Fig. 5 shows a block diagram of another embodiment of the present device for monitoring the supply voltage;

Fig. 6 shows a simplified electrical diagram of the device of Fig. 5.

Fig. 1 shows a device 1 for detecting when a booster voltage Vb reaches a given threshold. The device 1 is integrated in a known memory 100 comprising: a voltage amplification stage 101 which provides the booster voltage Vb; a logic part 102 which generates signals DET and R for turning on and off the device 1 and which is supplied by the device 1 with an output signal OUT whose logic value indicates whether or not the booster voltage Vb has exceeded a given threshold; and a memory array 103 having memory cells 104.

The device 1 has a level adjustment stage 2 with two inputs 3, 4, which are supplied with a monitoring enable signal DET and the monitored voltage Vb, and two outputs 5, 6, the corresponding signals EN1, EN2 supply. The signal EN1 is applied to the input 7 of a source or Source stage 8 supplied, the output 9 provides a reference voltage V1; and the signal EN2 is supplied to the input 12 of a Begrenzerstufe 13, which is also supplied at the terminal 14 with the voltage V1. The voltage V1 is also supplied to an input 15 of a latch type threshold detection stage 16 whose second input 17 is supplied with the monitored voltage Vb and whose output 18 provides a logic signal LA. The output 18 of the detection stage 16 is connected to an input 20 of a latch circuit 21 whose output 22 provides an OUT signal to the logic portion 102 and / or other circuits of the memory 100; and stages 16 and 21 have respective reset inputs 24, 25, which are supplied with a reset signal R, respectively.

In particular, the adaptation stage 2 provides an adjustment of the levels of the input logic signals provided by the stages 101 and 102 of the memory device 100 to the levels of the detection means 1 and provides opposite output signals EN1 and EN2 which are switchable between zero and the voltage Vb, so that the high Signal EN1 or EN2 is coupled to the voltage Vb or connected in flip-flop and this follows.

The reference voltage stage 8 provides for the generation of a voltage V1 whose value changes along with a change in the booster voltage Vb, instead of being constant. In particular, the voltage V1, when enabled by the signal EN1, is initially coupled to Vb or connected in a flip-flop and follows the exact course of Vb; when Vb reaches a first threshold value Vth1, the voltage V1 continues to increase but not as fast as Vb, giving a voltage difference ΔV different from zero between the terminals 15 and 17 of the detecting stage 16; and when Vb reaches the desired steady-state value, the voltage V1 is set to zero.

The limiter stage 13 is operated only when the monitored voltage Vb exceeds the given steady-state value, and provides two functions: on the one hand, the switching of the detection stage 16 in the above case (ie, Vb exceeds the given steady-state value), if a discrepancy exists between the reference voltage 8 and the detection stage 16, or if the source or Source Stage 8 is not functioning normally for other reasons; and on the other hand preventing the source stage 8 from being damaged by too high a voltage.

The detection stage 16 provides for the monitoring of the voltage difference AV at the inputs 15 and 17, as well as the generation of the output signal LA whose logic value indicates whether the monitored voltage Vb has exceeded the given threshold or not.

The latch stage 21 is provided exclusively as an interface for the signal LA with the remainder of the memory device 100.

The device according to FIG. 1 works as follows. Before being turned on (first logic state, eg, 0 of the signal DET), the device 1 is initially reset to a pre-enable state by the signal R, the signals LA and OUT in a given logic state (e.g. 0) indicate that the booster voltage Vb has not yet reached the operating level; the functions that require the booster voltage Vb are disabled; and the signals EN1 and EN2 (low and high) lock the steps 8 and 13.

When the signal DET switches to high, the level adjustment stage 2 releases the stages 8 and 13, by the signals EN1 and EN2 to high or be switched low; As mentioned, the signal EN1 therefore assumes the value of the monitored voltage Vb and follows the exact course thereof, so that the reference source stage 8, in addition to being enabled by the switching of the signal EN1, starts Vb in exactly the same way as to monitor the detection stage 16; as mentioned, the voltage V1 is coupled to Vb or connected in a flip-flop and follows the exact course of it; and this continues as long as the voltage Vb remains below the first threshold Vth1. In practice, in the above initialization phase, the reference voltage is disabled and the detection stage 16 itself provides the coupling of V1, with Vb.

When Vb exceeds the first threshold value Vth1, the reference source 8 is turned on and cooperates with the detecting stage 16, so that the voltage V1, as mentioned, rises more slowly than Vb, as shown in Fig. 2, the voltage Vb, the voltage V1 and the output LA of the detection stage 16 shows. It can be seen that the curves of Vb and V1 begin to diverge when Vb exceeds the threshold Vth1 (time t1).

As a result, in the second phase, there is a potential difference ΔV different from zero between the inputs 15 and 17 of the detecting stage 16, and increases as Vb rises; and when the potential difference AV exceeds a second given threshold value Vth2 (time t2 in FIG. 2), the detecting stage 16 turns on and the signals LA and OUT are turned high.

As mentioned, the limiter stage 12 is not operated when the device 1 is functioning properly, whereas in the case when the voltage V1 exceeds the given threshold, it is turned on to switch the detection stage 16 and set the voltage V1 to zero.

As will be explained in greater detail later with reference to FIG. 3, the source stage 8 and the detection stage 16 advantageously cooperate as follows. When the voltage Vb exceeds the first threshold value Vth1, the source stage 8 generates a current related to the value of Vb and supplied to the detecting stage 16, which in turn generates the potential difference ΔV between the terminals 17, 15; and if the potential difference (which therefore depends on the current generated by the reference source 8 and ultimately depends on the value of Vb) exceeds the threshold value Vth2, the detecting stage 16 switches.

As shown in Fig. 3, has a level matching stage 2, an N-channel transistor 30 whose gate terminal is connected to the input 3 of the stage 2, wherein the source terminal is grounded, and wherein the drain terminal with connected to the output 6. The input 3 is also connected to the input of an inverter 34 whose output is connected to the gate of an N-channel transistor 31, whose source is grounded, and whose drain is connected to the output 5. The stage 2 also has two P-channel transistors 32, 33, the source terminals are connected to the input 4, whose drain terminals are connected to outputs 6 and 5, and their gate terminals with the outputs 5 and 6 are connected. The transistors 30, 32 form a first branch 2a and the transistors 31, 33 form a second branch 2b of the adaptation stage 2.

The limiter stage 13 comprises a native P-channel transistor 35 (ie, not implanted for changing the threshold during fabrication, thus having a high turn-on threshold) and a normal P-channel transistor 36 (having a high threshold) modified threshold). More specifically, in transistor 35, the gate terminal is connected to input 12 of stage 13 (which is directly connected to output 6 of stage 2), the drain terminal is grounded, and the source terminal is connected to the drain terminal of the transistor 36 connected. The transistor 36 - which is diode connected, ie with shorted drain and gate terminals - has a source terminal which forms the output 14 of the stage 13 and is connected directly to the terminal 9 of the reference source stage 8.

The reference source stage 8 has a memory cell 38 similar to the memory cells 104 and an N-channel transistor 39. The memory cell 38 has a control gate connected to the input 7 of the stage 8, the source is grounded, and the drain is connected to the source of the transistor 39; and the transistor 39 has a gate connected to the input 7 and a drain connecting the output 9 to the voltage V1.

The detection stage 16 has P-channel transistors 40, 41, 42 and N-channel transistors 44, 45, 46. More specifically, the source of all three P-channel transistors 40, 41, 42 are connected to the input 17 of the stage 16; the source terminal of all three N-channel transistors 44, 45, 46 is grounded; the drain terminal of the transistor 40 is connected to the input 15 (which is directly connected to the output 9 of the stage 8), and the gate terminal of the transistor 40 is connected to the output 18 of the stage 16; and transistors 41 and 42 are connected in parallel with the drains connected to the output 18 and the gate terminals connected to the input 15. The transistor 41 is of the resistance type, whereas the transistor 42 is a high threshold, high W / L ratio (W / L>> 1) type to allow it to have a high current as soon as its threshold is reached. The drain terminal of the transistor 44 is connected to the input 15 and the gate terminal of the transistor is connected to the output 18. The drain terminal of the transistor 45 is connected to the output 18, and the gate terminal of the transistor 45 is connected to the input 15; and the drain terminal of the transistor 46 (reset transistor) is connected to the output 18, and the gate thereof is connected to the reset input 24.

The latch circuit 21 is essentially a flip-flop and includes an N-channel input transistor 48, two P-channel transistors 49, 50, two N-channel transistors 52, 53 and an N-channel reset Transistor 54 on. In particular, the source terminal of the input transistor 48 is grounded, the gate terminal thereof is connected to the input 20 of the latch stage 21 (which is directly connected to the output 18 of the stage 16), and the drain terminal thereof is a Node 56 connected; the source terminals of the transistors 49 and 50 are connected to a supply line 57 on the supply voltage Vcc; the source of transistors 52 and 54 is grounded; the drain of transistor 49 is connected to node 56 and the gate thereof is connected to the output 22 of latch 21; the gate terminal of the (native) transistor 50 is connected to the node 56, and the drain terminal thereof is connected to the output 22; the drain of transistor 52 is connected to node 56 and the gate thereof is connected to output 22; the drain terminal of the transistor 53 is connected to the output 22, and the gate terminal thereof is connected to the node 56; the drain terminal of the transistor 54 is connected to the output 22, the source terminal thereof is grounded, and the gate thereof is connected to the input 25 of the stage 21, which is supplied with the reset signal R.

The circuit of FIG. 3 works as follows. Initially (when the memory is turned on), the reset signal R is high and turns on the reset transistors 46, 54 to ground the outputs 18, 22; the OUT signal is therefore low, indicating that the booster voltage Vb has not yet reached the steady state; the DET signal is low, so that the inverter 34, the transistor 30 of the stage 2 is turned off and the transistor 31 is turned on or holds through; the transistor 31 keeps the signal EN1 at the output 5 low (grounded) and keeps the transistor 32 on and turned on; the signal EN2 is high and is at the same value as the voltage Vb; and both the reference source stage 8 and the limiter stage 13 are disabled. In this phase, none of the branches 2a, 2b of the matching stage 2 consumes current since only one transistor in each branch is turned on. The same applies to the detection stage 16, in which the low LA signal turns on and off the transistors 40, 45, 46 and 44, 41, 42 kept off, as well as the latch stage 21, in which the transistors 49 , 53, 54 are switched on or through and the transistors 50, 52 are turned off.

Also, the state of the device 1 does not change when the reset signal R turns low and the transistors 46, 54 turn off.

When the DET signal turns high, the transistor 30 is turned on and the transistor 31 is turned off so that the signal EN2 at output 6 turns low and turns on the transistor 33, which connects the output 5 to the booster circuit Vb. In this phase, therefore, signal EN1 is high and follows the course of Vb generated by the release of voltage boosting stage 101 in FIG. 1 is increased; and the transistor 32 is turned off, by the high voltage at its gate terminal, so that in turn flows in any of the branches 2a, 2b of the matching stage 2 current.

Source stage 8 remains off as long as the voltage at input 7 is below the turn-on threshold of cell 38, e.g. B. 2.1 volts, which therefore represents the first threshold Vth1. Below this value, therefore, the transistor 40, which is turned on, keeps the voltage V1 at the input 15 equal to the voltage Vb at the input 17, so that the voltage V1 follows the course of Vb. In this phase, the Begrenzerstufe 13 is also turned off, so that their switching a voltage V1 of about 2.6 to 2.7 volts is required, ie equal to the sum of the threshold voltage of the transistor 35 (which is a native transistor with a high threshold of is about 1.7 volts) and the threshold voltage of transistor 36 (about 0.9 to 1 volt).

When the voltage Vb exceeds 2.1 volts, the reference source 8 is turned on and begins to draw a gradually increasing current with respect to the gate-source voltage drop of the cell 38, and the reference source 8 generates a voltage drop between the source and drain terminals of the transistor 40 and a divergence between Vb and V1. When the booster voltage Vb rises, the voltage drop AV between the terminals 17 and 15 of the detecting stage 16 also increases, and this is also detected by the transistors 41, 42, and the transistor 41 is turned on. Since the transistor 41 is of the resistance type, when it is turned on, it does not initially conduct enough current to the switching stage 16 which is switched when the voltage drop AV is approximately equal to 1.7 volts, ie In particular, components 38, 39 and 40 are designed such that when voltage Vb reaches the desired level (approximately 4 volts in the example shown) memory cell 38 (which receives voltage Vb across the signal EN at its control gate terminal) conducts sufficient current to produce a voltage drop AV of 1.7 volts in transistor 40 which turns on transistor 42. In view of its high W / L ratio, transistor 42, once turned on, starts high current and rapidly turns output 18 high so that transistor 40 is turned off, transistor 44 is turned on, voltage V1 is fast is turned low, the transistor 45 is turned off, and the signal LA is turned high, indicating that the desired threshold voltage has been reached.

After switching the signal LA, the transistor 48 of the latch stage 21 is turned on, the node 56 switches to low; the transistor 50 is turned on and the transistor 53 is turned off; the output 22 switches high equal to the supply voltage Vcc; the transistor 49 is turned off and the transistor 52 is turned on and the circuit is brought to a stable state, indicating that the desired threshold of Vb has been reached, and the circuit can only be reset by turning off the memory 100 and back on is turned on, in which case the above sequence is repeated.

The device 1 only consumes current during the evaluation, in particular via the detection stage 16 in the interval between the switching on of the reference source 8 and the switching of the detection stage 16, due to the current path formed by the transistor 40 and the source stage 8. After the detection stage 16 toggles, there is no longer a current path between the high voltage line (input 17) and ground since the transistors 40, 45 and 46 are off. Similarly, no power is consumed by the latch 21 because the transistors 49 and 53 are turned off and turn off any possible path between the supply line 57 and ground.

The device 1 automatically adapts to any process spread that might result from a small variation in component performance, particularly with regard to the conductivity of the cell 38 and the matching between the cell 38 and the transistor 40, which, as mentioned, are important in ensuring the correct operation of the device.

Since the cell 38 is of the N-channel type and the transistor 40 is of the native P-channel type, a mismatch may occur which affects the precision of the device 1. In particular, two situations can arise: a high conductivity of the cell 38, which results in an early switching of the device 1; or a low conductivity that slows down the cell and may cause an excessive increase in voltage V1 before the device switches. The first situation is not critical because the cell 38 is formed simultaneously with the cells 104 of the memory 100 and the same method is used and the cell 38 is well adapted to the characteristics of the cells 104. Even if the conductivity of cells 104 (and cell 38) is slightly above the design level or As a result, the cell 38 generates the switching current for the device 1 before the voltage Vb reaches the given steady-state value, as a result of which the early generation of the OUT signal in no way affects the operation of the device 1, since the memory cells also have a high conductivity and therefore are also correctly readable at a slightly lower than the predetermined or nominal booster voltage Vb.

On the other hand, the second situation, which could eventually affect the operation of the device 1, prevented by the Begrenzerstufe 13. In the case of poor conductivity of the cell 38 and the cells 104, so that at the (given steady-state booster voltage) current below the nominal value or current. Design levels that is insufficient for switching the detection stage 16, the voltage V1 and therefore the voltage between the drain and source terminals of the cells 38 may increase excessively, resulting in a "soft" writing of the cell 38 when repeated can change the properties of cell 38 and therefore change the reliability of cell 38 as a reference. The same problem also occurs in the case of a mismatch of the cell 38 and the transistor 40 in the event that the cell 38 behaves as intended at a given steady state booster voltage, but the transistor 40 generates a voltage drop AV which is insufficient for switching ,

In the above cases, however, the better matching of the transistor 40 and the transistors 35, 36 is taken advantage of in view of the fact that all three are of the same type and therefore manufactured together. In particular, once the voltage V1 tends to exceed the threshold (2.7 volts) of the limiter stage 13, it will turn on and generate additional current which is added to that of the reference source 8 and will certainly switch the detection stage 16. The limiting stage 13 thus ensures the correct switching of the device 1 when the booster voltage Vb reaches the given threshold, and at the same time that a further increase of the voltage V1 and a "soft" writing of the cell 38 is prevented.

The use of a memory cell 38 as a threshold element to turn on the source stage 8 is advantageous not only because it allows the device 1 to automatically adapt to the characteristics of the memory array 103. By having a higher turn-on threshold compared to normal MOS transistors, the memory cell 38 also provides for the source stage 8 to be turned on later, thereby delaying the instant current begins to flow through the transistor 40, causing the transistor 40 to flow Consumption of the detection stage 16 is reduced during the evaluation.

The transistor 39 of the source 8, which forms a cascode configuration, also provides protection to the cell 38 and, in particular, prevents too high a voltage (above 1 volt for reading the cell) at the drain of the cell 38, even if the booster voltage Vb is almost zero has reached the steady state value.

The device 1 also offers the advantage that it is not subject to oscillation since the latch circuits are also used to form the detection stage 16; that it is independent of the value of the supply voltage Vcc; and that it operates reliably, maintaining the same trigger level, for any transient state (slow or fast) of the supply voltage.

FIG. 4 shows a variation in which the detection device 1 ', unlike the device 1 in FIG. 3, can be switched on pulsed and can itself be repeatedly switched on after the release of the memory device 100.

In particular, the device 1 'comprises a level matching stage 2, a reference source stage 8, a limiter stage 13, a threshold detection stage 16 and a latch circuit stage 21, similar to those in Figure 3, and the corresponding components are therefore the same Numbering system without further description referred.

In the device 1 ', the signal R is also supplied to one input of a NOR gate (NAND gate) 60 whose other input is supplied with a signal PD. The output of the NOR gate 60 is connected to the input of an inverter 61 whose output is connected to the gate terminal of an N-channel transistor 62, the source terminal is grounded, and its drain terminal to the input 3 of the Level matching stage 2 is connected; a switch 63 is provided between an input 64 (which provides the enable signal CE) of the device 1 'and a node 3; and the switch 63 has a pair of complementary control terminals, one connected to the output of the NOR gate 60 and the other connected to the output of the inverter 61.

In the device V, the DET signal at the input 3 of the level matching stage 2 is generated internally on the basis of the signals PD and CE, instead of being externally generated (eg by the logic part 102). More specifically, the output of the inverter 61 turns high when the memory 100 is enabled and the reset signal R goes high, and the transistor 62 is turned on and turns the input 3 low. At the same time, the signal R is present at the gate terminals of the transistors 46, 54, so that the device V is reset in the same way as the device 1 in FIG. 3.

When the reset signal R goes low and when the normally high signal PD goes low, the output of the NOR gate 60 goes high, the output of the inverter 61 goes low, the transistor 62 is turned off, and the switch 63 is therefore enabled and provides the logic state at input 64 to input 3. The state of signal DET is therefore determined by that of signal CE. When CE is high, DET turns high to turn on with respect to FIG. 3 to release the described evaluation phase.

Unlike the embodiment of FIG. 3, the device 1 'is capable of being reset and performing another evaluation phase under the control of the logic part 102.

For this purpose, the logic part 102 first resets the detection stage 16 and the latch stage 21 by switching the signal R high, which in this case represents a reset in the true sense of the word. When the signal R goes low back in the same manner as described above, the low switching of the signal PD provides for closing the switch 63 and coupling DET to CE. In particular, when CE is high, the evaluation phase is released again.

Fig. 5 shows a block diagram of another embodiment of the present invention and more particularly means 70 for monitoring the supply voltage Vcc. As the devices 1 and V in Figs. 1, 3 and 4, the device 70 forms part of a known memory 110, which has a supply stage 111, which generates the supply voltage Vcc, and a logic part 112, which is supplied by the stage 111 with the supply voltage Vcc and by the device 70 is supplied with an output signal O whose logic value indicates whether the supply voltage Vcc has reached a given threshold. The logic part 112 generates a regulation signal REG and a logic signal VD which, when high, is connected to the supply voltage Vcc. The memory 110 also includes a memory array 113 having memory cells 114, and the logic portion 112 and array 113 may include the same components 102 and 103 as the memory 100.

The device 70 comprises a reference source stage 71, a limiter stage 72 and a threshold detection stage 73, similar to stages 8, 13 and 16 in FIG. 1. In particular, the reference source 71 has an input 75 connected to the input 74 of the apparatus 70 connected via a switch 76; a lock input 77 which carries a signal DIS; and an exit 78. The input 74 of the device 70 is in turn connected to the output of the logic part 112, via which it is supplied with the signal VD; and like stage 8, source stage 71 produces at output 78 a voltage V2 that varies in accordance with the value of supply voltage Vcc. The limiting stage 72 has an input 80, which is also supplied with the signal DIS, and a terminal 81 which is connected to the output 78 of the reference source 71. The detection stage 73 has an input 82 which is connected to the output 78 of the reference source 71; a reset input 83 which carries a signal R1; an input 84 which is supplied with the supply voltage Vcc; and an output 85 which carries the signal 0.

The device 70 also has a blocking stage 86 and an asymmetrical delay stage 87. The inhibit stage 86 provides for disabling the device 70 when the supply voltage Vcc reaches the threshold or in the presence of a regulator function (enabling the voltage booster circuits in the presence of a low supply voltage Vcc) and has a first input 88 connected to the input 74 of the device 70 connected is; a second input 89 which is connected to the output 85 of the detection stage 73 and carries the signal 0; a third input 90 which is connected to the logic part 112, via which it is supplied with the signal REG; and an output 91 connected to the input 92 of the asymmetric delay stage 87.

The asymmetrical delay stage 87 has an output 93 which is connected to an inverted control input of the switch 76, whose direct input is also connected to the output 93 via an inverter 94; and an output 93 is also connected to the inputs 77 and 80 of the stages 71 and 72 via a switch 95 having an inverted input connected to the input 74 of the device 70 and a direct input connected to the input 74 via an inverter 96, owns.

Initially, assume that the signal REG of device 70 in Figure 5 has a first logic value (eg, high) indicating that there are no voltage regulation functions. Initially, after the memory 110 is turned on, the signal VD is low, so that the output of the inverter 96 is high and the switch 95 is on; the signal VD supplied to the input 88 resets the inhibit stage 86; the signal (high) on the tag 92 is supplied by the delay stage 87 to the input of the switch 95 after a short delay; the switched on or Closed switches 95 provide the inhibit signal DIS to inputs 77 and 80 to disable stages 71 and 72. Also, through the signal R1 at the input 83, the inverter 96 holds the detection stage 73 in a pre-enable state, the signal 0 in a given logic state (e.g. 1) indicates that the supply voltage Vcc has not yet reached the predetermined threshold value; and the low output of the delay stage 87 keeps the switch 76 closed and allows the signal VD to be supplied to the input 75 of the reference source 71, which is already inhibited by the signal DIS.

When signal VD goes high, the output of inverter 96 goes low; the switch 95 is opened; the stages 71, 72 no longer receive the inhibit signal DIS at the inputs 77, 80 and are turned on; and the high logic level at the input 88 switches the inhibit stage 86 to "standby" or "wait", depending on the switching of the 0 or REG signal. As long as the signals 0 and REG remain high, the latching stage 86 does not switch and does not switch on the delay stage 87, so that the switch 76 remains switched on or closed.

In the meantime, the reference source stage 71, which is no longer locked by the signal DIS, begins to monitor the supply voltage Vcc from the signal VD. In particular, and as described with reference to FIG. 1, the reference source 71 cooperates with the detection stage 73 to provide a voltage V2, which is initially coupled to the supply voltage Vcc and follows the exact course thereof, and which later subsequently (when the voltage VD or V2 reaches a first threshold) increases more slowly. In other words, as before, the reference source 71 is initially disabled, and the threshold detection stage 73 provides for coupling V2 to Vcc; The reference source 71 is then turned on to produce a potential difference that increases along with Vcc; if the potential difference exceeds a second given threshold, the detection stage 73 will switch over and the signal 0 at the output 85 will go low to indicate that the supply voltage has reached a given threshold.

The switching of the output signal 0 is detected by the blocking stage 86 which switches and releases the asymmetric delay stage 87; stage 87, whose output switches with respect to the input with a delay dependent on the switching edge, goes high with a delay greater than that at which it switches low so that after a given delay the switch 76 is opened to turn off the voltage VD (equal to the supply voltage Vcc) to the reference source 71, and the device 70 is automatically turned off.

The same turn-off operation is also enabled by up-switching the signal REG, which indicates regulation of the supply voltage, e.g. B. Enable a voltage gain to provide the utility booster voltage Vb. This condition is obviously typical of devices operating at such a low supply voltage that Vcc can never reach the given threshold, with the logic portion 112 switching the signal REG low after a predetermined delay determined by the stage 87 to the device 70 to lock.

The limiting stage 72 provides exactly the same function as the stage 13 of the device 1 in FIG. 1, ie the switching of the detection stage 73 when the voltage V2 exceeds a given value in order to compensate for a mismatch of the reference source 71 and the detection stage 73 to protect the source 71.

An embodiment of the device 70 is shown in Fig. 6, in which the components of the steps 71, 72, 73 which are identical to those of the steps 8, 13, 16 are designated by the same numbering system without further description.

More specifically, the reference source stage 71 has, in addition to the memory cell 38 and the transistor 39, an N-channel blocking transistor 120 whose source is grounded, whose gate is connected to the input 77 of the stage 71, and whose drain is connected to the source Input 75 of the stage 71 (the gate terminals of the components 38, 39) is connected. In addition to the transistors 40-42 and 44-46, the detection stage 73 has an output buffer - in this case in the form of an inverter 121 - whose input is connected to the terminal 18 and whose output is connected to the terminal 85.

In Fig. 6, the inverter 96 is duplicated and has a first inverter 96a controlling the switch 95 and a second inverter 96b connected to the input 83 of the detecting stage 73; and the switch 95 in FIG. 5 is replaced by a switch 122 and a transistor 123. In particular, the switch 122 is connected between the output 93 of the delay stage 87 and the inputs 77, 80 of the stages 71, 72 and has a direct input connected to the input 74 of the device 70 and an inverted input connected to the input terminal Output of the inverter 96a is connected. P-channel transistor 123 has a gate connected to input 74 of device 70, a drain connected to inputs 77, 80 of stages 71, 72, and a source, which is connected to the supply line 57 with the voltage Vcc.

The blocking stage 86 essentially has a flip-flop and has first and second NAND gates 125, 126. In particular, a first input of the first NAND gate 125 forms the input 88 of the stage 86, a second input of the first NAND gate 125 is connected to the output of the NAND gate 126, and an output of the first NAND gate 125 forms the output 91; a first input of the second NAND gate 126 is connected to the output 91 and a second and third input of the second NAND gate 126 forms the inputs 89, 90 and the signals 0 and REG are there, the input 89 via a capacitor 127 is also grounded.

The delay stage 87 is formed by a cascade connection of a given number of inverters (in this case three, namely 130, 131, 132), which are arranged between the input 92 and the output 93 of the stage 87 and whose outputs are grounded via capacitors 134.

In short, the device 70 of Fig. 6 operates as follows. Initially, when the signal VD is low, the output of the gate 96b is high, so that the transistor 46 on or the node 18 is low, the detection stage 73 is reset, and the output 0 is high; at the same time, the output of the inverter 96a is also high and turns off the switch 122 (along with the signal VD); the transistor 123 is turned on and keeps the inputs 77, 80 at the voltage Vcc; the transistor 35 is therefore off and the limiter 72 is off; the transistor 120 is turned on and keeps the gate terminals of the components 38, 39 grounded to the source or Block source stage 71; since the input 88 is low, the outputs of the NAND gate 125 and the inverter 131 are high and the output 93 of the inverter 132 is low; the switch 76 is therefore on and supplies the low signal VD to the source stage 71 to confirm its off state; together with signals 0 and REG at inputs 89, 90, the high output of NAND gate 125 keeps the output of NAND gate 126 low.

When VD toggles high, the input of gate 125 connected to the output of gate 126 remains low, preventing latch stage 86 from switching; the switch 76 remains switched on and supplies the signal VD to the source or Source stage 71, which rises together with the supply voltage Vcc; R1 turns low to enable the detection stage 73, turn off the transistor 123, and turn on the switch 122; the switch 122 connects the output 93 (low) of the delay stage 87 to the inputs 77, 80 of the stages 71, 72; the transistor 35 is turned on to release the limiter 72, and the transistor 120 is turned off or locked to enable the source stage 71; the device 70 then operates in the same way as the device 1, it being noted that the voltage VD follows the exact course of the supply voltage Vcc. Therefore, the device 70 initially remains in the previously described state as long as the supply voltage Vcc remains below its first threshold; the reference or Source 71 is then turned on and begins to draw current so that voltage V2 rises less than Vcc; when the voltage V2 reaches a second threshold corresponding to the desired steady state value of the supply voltage Vcc, the detecting stage 73 switches over, the terminal 18 turns high, and the signal 0 goes low.

At this time, NAND gate 126 receives a low signal at input 89 and turns high, thereby toggling NAND gate 125, which receives two high signals at the input; the gate 125 in turn switches to provide a low output and to cascade the inverters 130, 131, 132 with a given delay; the signal at output 93 of stage 87 turns high, turns off switch 76, which therefore turns off the signal VD at the input of source stage 71, and turns transistor 35 off again, turning transistor 120 on to stages 71, 72 lock.

The device 70 is also disabled as described above in the event that the REG signal goes low. In the regulator mode, in which the supply voltage Vcc is low and can not reach the given threshold, the low logic level of the signal REG, after a given time, provides for the device 70 to disable and disable consumption.

With the device 70 having the same reference source, level limiting and threshold detection stages described in detail with reference to Figure 3, the device 70 also provides the same advantages in terms of low consumption and adaptability.

Of course, changes may be made to the device described and illustrated herein without departing from the scope of the present invention. In particular, the individual stages may be formed differently than described herein. For example, the latch stage 21 in FIG. 3 may be replaced by a simple buffer as in FIG. 4 or by a level matching circuit similar to stage 2. Instead of using transistors 46, 54, the detection stage 16 or 73 and the latch stage 21 may be reset by not balancing (non-balancing) their structure and by sizing the components to reset as needed (lower output node 22 in Figs. 3, 4 and lower node 18 in Fig. 6) before the given threshold is reached. In this case, advantageously, a capacitive element, for. B. in the form of N + diffusion, between node 18 and ground (Figure 6) or between node 22 and ground (Figures 3 and 4).