Integrated circuit memory.

Field of the Invention

This invention relates generally to integrated memory circuits, and more particularly to integrated memory circuits having word lines that are controlled by a write enable.

Background of the Invention

An integrated memory circuit, such as static random access memory (SRAM), is generally implemented as an array of memory cells in a plurality of rows and columns. A field can be divided into blocks of memory cells. The memory cells can be addressed by block, row and column decoders for reading data from the memory cells or for writing data into the memory cells. Each memory cell has a unique address at an intersection of a row and a column. The bit line pairs are commonly used for both reading data from and writing data to the memory cell. Typically, a value is read from memory when a write enable signal is logically high (or inactive) and is written to memory when a write enable signal is logically low (or active). During a read cycle, a word line selects the addressed row of memory cells and a pair of complementary bit lines transfer the data bit between the addressed row and a sense amplifier. The value exists as a relatively small differential voltage on the pair of complementary bit lines. A sense amplifier detects and amplifies the differential voltage and transmits it to the data output stage of the integrated memory circuit via global read data lines.

During a write cycle, a relatively large difference signal is provided on the bit lines to overwrite the contents of a selected memory cell. At the end of a write cycle, the differential voltage remaining on the bit line pair must be reduced to a relatively low level so that the value is not erroneously written to a memory cell during the subsequent read cycle. The differential voltage on the bit line pair must also be quickly reduced so that the read cycle is not extended unnecessarily. This process is called write recovery or bit line equalization. Bit line equalization brings the voltages on the bit line pair so close together that a value is not overwritten and the correct value is quickly sensed during the read cycle. The write recovery of the bit line pairs is performed in a timing specification known as TWHAX (high write signal to an invalid address). TWHAX is essentially the time interval between the start of a read cycle and the change of address to select a different location in the memory field. During this time a write recovery or bit line equalization occurs to prevent data from being overwritten during the following read cycle. The write recovery period must be long enough to allow bit line balancing to occur, but not so long as to unnecessarily delay the read cycle. A minimum time of zero is usually given as the TWHAX timing specification.

If an address changes before the write enable signal goes logic high, TWHAX is considered negative and bit line equalization may not be complete before the word line changes, causing such a data reliability problem. This problem is more serious if the address selects a new word line within the same block as that of the previous word line because less time is needed for address changes if they are within a block. For security band purposes, the TWHAX specification must not only be met, but exceeded. It is desirable that the memory ignore address changes that occur a couple of nannoseconds before the write cycle changes to the read cycle, since the user may have difficulty ensuring that the address does not change before the write enable signal changes. These difficulties can arise due to the custom timing circuitry as well as board layout problems.

US Patent No. 4,878,198 discloses a memory in which the bit lines are balanced at the end of a write cycle.

Summary of the invention

According to the present invention, there is provided an integrated memory circuit as claimed in claim 1.

These and other features and advantages will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings.

Brief description of the drawings

1 illustrates in block form an integrated memory circuit in accordance with the present invention.

FIG. 2 illustrates, in a partial block diagram form and a partially schematic form, a portion of the row predecoder of FIG. 1 in accordance with the present invention.

3 shows a timing diagram of various signals of the memory of FIG. 1 in accordance with the present invention.

FIG. 4 illustrates, in partial block diagram and partially schematic form, a portion of the write control circuit of the memory of FIG. 1 in accordance with the present invention.

Figure 5 illustrates in schematic form the one-sided delay circuit of the memory of Figure 1 in accordance with the present invention.

Description of a preferred embodiment

1 illustrates in block form a memory 20 in accordance with the present invention. Memory 20 includes memory block 22, row select circuitry 38, address buffer 40, row predecoder 42, block logic 42, column predecoder 43, write control circuit 44, single sided delay circuit 45, data I / O circuitry 46 , global write data lines 47 and global read data lines 50. The memory block 22 includes a bit line equalization block 24, a memory array 26, a column logic / decoder 28, a memory cell 30, a word line 32 and a bit line pair 34. The memory block 22 is a representative memory block of the memory 20 and there may be other memory blocks in the memory 20 be present. The memory array 26 contains 128 bit line pairs and 512 word lines. The memory cells are arranged at crossing points of the word lines and the bit line pairs. A representative memory cell 30 is illustrated in FIG. 1, which is connected to the word line 32 and the bit line pair 34. Bit line pair 34 includes pit lines 36 and 37. Global write data lines 47 include global write data line 48 and global write data line 49. The global read data lines 50 include a global read data line 51 and a global read data line 52.

Write control circuit 44 receives an external write enable signal at ECL (Emitter Coupled Logic) level labeled '/ W' and an external chip select signal at ECL level labeled '/ CS'. In response, write control circuit 44 provides a core write signal labeled "/ WIC", an internal chip select signal labeled "/ CSI", and internal differential write signals labeled "WI" and "/ WI", respectively. Unilateral delay circuit 45 receives internal write signals WI and / WI and provides a unilateral delay control signal labeled 'WED' at logical CMOS (Complementary Metal Oxide Semiconductor) levels.

For ECL applications, VDD is the system ground, with VSS being equal to a negative power supply voltage that is generally equal to -5.2 volts. A logically high ECL voltage is substantially equal to VDD minus a base emitter diode voltage drop (VBE) and a logically low ECL voltage is equal to VDD - 2VBE. The CMOS logic levels can oscillate over the full range of the power supply voltage.

Address buffer 40 receives an address signal labeled 'ADDRESS' and provides a buffered differential row address labeled 'ROW ADDRESS', a buffered differential block address labeled 'BLOCKADRESSE' and a buffered differential column address which is labeled 'COLUMN ADDRESS'. Block logic 41 receives block address signals BLOCK ADDRESS, core write signal / WIC, and internal chip enable signal / CSI and in response provides a bit line equalization signal labeled 'EQ' to bit line equalization block 24 and a block select signal labeled 'BS' column selection 38. In other embodiments, different numbers of blocks, different sizes of blocks, and different word widths can be used. Block logic 41 will provide block select signals and bit line equalization signals to the other memory blocks as well.

The row predecoder 42 receives the differential row address signals ROW ADDRESS and the one-sided delay control signal WED. In response, the row predecoder provides the row selector 38 with a plurality of predecoded row address signals, labeled 'PRE-DECODED ROW ADDRESS'. Column predecoder 43 receives the COLUMN ADDRESS differential column address signals and, in response, provides the column logic / decoder 28 with a plurality of predecoded column address signals, designated 'PRE-DECODED COLUMN ADDRESS'. The specific address signals provided by row predecoder 42 and the column predecoder 43 are not particularly significant and may be different in other embodiments. In addition, the amount of decoding performed by the row and column predecoders may be different in other embodiments.

In one embodiment, memory block 22 is one of 64 memory blocks and the 64 blocks are grouped into four quadrants of 16 blocks each. The other memory blocks are not shown for clarity and simplicity. In memory block 22, row selection 38 receives block selection signal BS and a pre-decoded row address and selects one of the 512 word lines in response. The memory cells in the memory array 26 are arranged at intersections of the 512 word lines and the 128 bit line pairs. Each memory cell is coupled to a word line and a bit line pair. Each bit line pair serves as an input to the memory cells during the write cycle of memory 20 and as an output during the read cycle. A representative memory cell 30 is shown coupled to word line 32 and bit line pair 34. Bit line equalization block 24 receives equalization signal EQ from block logic 41 and is coupled to each of the 128 bit line pairs of memory array 26. Block logic 41 provides block selection signals BS for selecting one of the memory blocks.

Column logic decoder 28 is coupled to each companion pair, including representative companion pair 34, and is coupled to global read data line pair 50 and global write data line pair 47. During a write cycle, the data I / O circuit 46 receives unilateral data labeled 'DATA' and provides differential data signals labeled 'WGDL' and '/ WGDL' to global write data lines 48 and 49, respectively , During a read cycle, data I / O circuit 46 receives differential data signals, labeled 'RGDL' and '/ RGDL', on global read data lines 51 and 52, respectively, and provides unilateral data signals DATA. In a preferred embodiment, memory 20 is configured with a word length of X1. However, memory 20 could also be configured to have a word length of X2, X4 or X8. The other global read data lines and global write data lines to support other word widths are not shown for ease of illustration.

For a word width of X1, memory 20 receives 22 address signals A0-A21. Address buffer 40 provides column address signals A0 - A3, block address signals A 4 - A7, row address signals A10 - A16, quadrant address signals A17 and A18 for selecting one of the four quadrants and X1 option address signals A19 - A21. Fewer address signals are required to configure memory 20 for other word widths.

To read data from memory 20, write control circuit 44 receives external chip select signal / CS as a logic low ECL (active) and external write enable signal labeled / W as a logic high ECL (inactive). Note that a bar or swipe over the signal name indicates that the signal is active at a logic low. In response to receiving the internal write control signals WI and / WI, the one-sided delay circuit 45 provides the one-sided delay control signal WED at a logic low during the write cycle. The internal write signals WI and / WI and the internal chip selection signal / CSI are buffered from the write enable signal / W and the chip selection signal / CS. The block selection signal BS is decoded from the block address signals BLOCKADRESSE and selects the memory block 22 of the memory 20. Only one block of memory can be selected at a time. Row predecoder 42 receives a row address decoded from the buffered row address differential signal row address and provides a pre-decoded row address labeled 'PRE-DECODED ROW ADDRESS' to row selector 38 to select one of the 512 word lines from which the word line 32 is an example. There are 128 memory cells that are coupled to each word line. Each memory cell coupled to the selected word line provides its output as a differential voltage on a corresponding bit line pair. Predecoded column address signals PRE-DECODED COLUMN ADDRESS are provided to column logic / decoder 28. For a word width of X1, the column logic decoder 28 selects a bit line pair from the 128 bit line pairs, for example the bit line pair 34. When the bit line pair 34 is selected, the column logic decoder 28 senses and amplifies the relatively small differential voltage supplied by the memory cell 30 to the bit line pair 34 and couples the selected bit line to the global read data line pair 50. The global read data line pair so is representative of the eight global read data line pairs in memory 20. The data I / O circuit 46 receives a differential signal from the global read data line pair 50 corresponding to the difference signal from the bit line pair 34 and provides a one-sided data signal DATA. The differential voltage during a read cycle is approximately 300 millivolts.

The flow of data is essentially reversed during a write cycle. To write data to memory 20, chip select signal / cs is logic low (active) and write enable signal / W changes state from logic high to logic low. Data I / O circuit 46 receives a data bit to be written to memory 20 and provides the data bit as a difference signal to a corresponding global write data line pair 47. Global write data line pair 47 is representative of the eight global write data line pairs in memory 20. Block logic 41 selects the block of memory to receive the data bit. Column predecoder 43 provides the predecoded column address to column logic decoder 28, which couples a global write data line pair to a bit line pair. The row predecoder provides a predecoded row address to row selector 38, which selects one of the 512 word lines. As in the read cycle, the memory cells located on an enabled word line deliver data to the bit line pairs. However, a voltage difference driven on the bit line pairs by the column logic decoder 28 is greater than the drive voltage of the memory cell and overwrites a stored bit in the memory cell. The differential voltage that is driven on the bit line pairs during the write cycle is approximately 3.0 volts. At the end of a write cycle, the differential voltage on the bit line pair must be reduced to a level small enough so that the value is not erroneously written to a memory cell during the subsequent read cycle. Equalization of the bit line pairs is achieved by the bit line equalization block 24.

The write cycle ends in response to the write enable signal / W becoming logic high. The differential voltage on the selected bit line pair must be equalized before the address changes the word line. This period is specified by the TWHAX specification. The TWHAX period is illustrated in the timing diagram of FIG. 3. Sometimes, for various reasons, TWHAX is of insufficient duration to allow bit line balancing before the word line changes. If the word line changes before bit line equalization occurs, the value that was written during the write cycle can be written to the selected memory cell during the next read cycle, causing a data reliability problem.

The one-sided delay circuit 45 supplies the one-sided delay control signal WED to the row predecoder 42 to prevent the predecoded row address from changing before the accompaniment compensation occurs. The old pre-decoded row address is latched and the new pre-decoded row address is prevented from leaving the row decoder 42 until the unilateral delay control signal WED goes logic low. In the preferred embodiment, the address is latched in row predecoder 42. In other embodiments, the row address can be latched anywhere between the address buffer 40 and the row selector 38. When determining where to lock the address, the number of address signals in the memory, the current load on each signal path, and the layout of the integrated memory circuit must be considered. In addition, in other embodiments, the column address can be locked instead of the row address.

The one-sided delay control signal WED is active at a logic high level. When the write enable signal / W changes from logic high to logic low, the control signal WED changes from logic low to logic high. When the write enable signal / W changes from logic high to logic low, the one-sided delay circuit 45 delays the transition of the one-sided delay control signal WED from a logic low level to a logic high level. Hence the name one-sided delay. The circuitry that provides the one-sided delay control signal WED is illustrated in FIG. 4 and will be discussed later. Controlling word line selection with the write enable signal prevents a new address from being scanned before bit line equalization has occurred, thereby preventing a TWHAX error.

FIG. 2 illustrates in a partial block diagram form and a partially schematic form a row predecoder section 42a of the row predecoder 42 from FIG. 1 in accordance with the present invention. The row predecoder 42 includes a plurality of row predecoder circuits represented by the row predecoder 42a of FIG. 2. In one embodiment, seven differential address signals are provided by address buffer 40 to row predecoder 42. Twenty-four row pre-decoder circuit sections 42a in the row pre-decoder 42 receive these seven differential address signals and provide 24 pre-decoded row address signals.

Row predecoder 42a includes a three-input NAND gate 56, a pass gate 57, and a latch section 58. NAND gate 56 includes P-channel transistors 60, 61 and 62, N-channel transistors 64, 65, 66, 67, 68 and 69 and an NPN transistor 63. P-channel transistor 60 has a source connected to a positive power supply terminal labeled 'VDD', a gate for receiving an input signal labeled 'RO', and a drain. P-channel transistor 61 has a source connected to VDD, a gate for receiving an input signal labeled 'R1', and a drain connected to the drain of transistor 60. P-channel transistor 62 has a source connected to VDD, a gate for receiving an input signal labeled 'R2', and a drain connected to the drain of transistor 61. NPN transistor 63 has a collector connected to VDD, a base connected to the drain of transistor 62, and an emitter connected to an account labeled 'N101'. N-channel transistor 64 has a drain connected to the drains of transistors 60, 61 and 62, a gate connected to the gate of transistor 60, and a source. N-channel transistor 65 has a drain connected to the source of transistor 64, a gate connected to the gate of transistor 61, and a source. N-channel transistor 66 has a drain connected to the source of transistor 65, a gate connected to the gate of transistor 62 and a source connected to a negative power supply voltage terminal labeled 'VSS'. is connected to. N-channel transistor 67 has a drain connected to the emitter of transistor 63 at node N101, a gate connected to the gate of transistor 64, and a source. N-channel transistor 68 has a drain connected to the source of transistor 67, a gate connected to the gate of transistor 65, and a source. N-channel transistor 69 has a drain connected to the source of transistor 68, a gate connected to the gate of transistor 66, and a source connected to VSS.

Pass gate 57 includes a P-channel transistor 70, an N-channel transistor 71 and an inverter 72. P-channel transistor 70 has a first drain / source terminal connected to the emitter of transistor 63 at node Nlol, a second drain / Source terminal connected to a node labeled 'N102' and a gate for receiving the unilateral control signal WED. N-channel transistor 71 has a first drain / source connection, which is connected to the first drain / souce connection of transistor 70 at node N101, a second drain / source connection, which is connected to the second drain / source connection of Transistor 70 is connected to node N102, and a gate on. Inverter 72 has an input terminal connected to the gate of transistor 70 and an output terminal connected to the gate of transistor 71.

Latch section 58 includes inverters 73 and 77, an NPN transistor 74 and N-channel transistors 75 and 76. Inverter 73 has an input terminal connected to the second drain / source terminal of transistor 70 at node N102 and an output terminal on. NPN transistor 74 has a collector connected to VDD, a base connected to the output terminal of inverter 73, and an emitter for providing an output signal labeled 'RP0'. N-channel transistor 75 has a drain connected to the base of transistor 74, a gate connected to the input terminal of inverter 73 at node N102, and a source connected to the emitter of transistor 74 , N-channel transistor 76 has a drain connected to the emitter of transistor 74, a gate connected to the input terminal of inverter 73 at node N102, and a source connected to VSS. Inverter 77 has an input terminal connected to the emitter of transistor 74 and an output terminal connected to the input terminal of inverter 73 at node N102.

The row predecoder section 42a receives the three input signals R0, R1 and R2 and supplies the output signal RP0 to the row selection 38. The row predecoder 42a is representative of the majority of the row predecoders in the memory 20. The number of row predecoders in the memory 20 is determined by the number of row address signals and the number of rows in each memory block 22. The input signals R0, R1 and R2 represent three of the buffered address signals provided by the address buffer 40 and the output signal RP0 represents one of the pre-decoded row address signals provided by the row pre-decoder 42.

NAND gate 56 is a conventional BICMOS NAND gate and receives three CMOS logic level input signals R0, R1 and R2 corresponding to three of the buffered row address signals ROW ADDRESS, and in response provides a signal at node Niol as a logical NAND of the input signals R0, R1 and R2. If at least one of the input signals R0, R1 and R2 is input to the NAND gate 56 logic low, the signal at node N101 is logic high. Only if all input signals R0, R1 and R2 are logic high will the signal at node N101 be logic low. The input signals R0, R1 and R2 are at CMOS logic level, however a NAND gate using different logic levels (such as ECL) can be used.

In the event that one of the input signals R0, R1 and R2 is logic low and the other signals are logic high voltages, at least one of the P-channel transistors 60-62 is conductive, at least one of the series-connected channel transistors 64-66 is not conductive and at least one of the transistors 67-69 connected in series is non-conductive. Therefore, the base of transistor 63 is pulled to approximately VDD and the logic high voltage at node Niol is equal to the voltage at the base of transistor 63 minus a base emitter diode voltage drop (VBE) across transistor 63. When all input signals R0 , R1 and R2 are logically high voltages, all P-channel transistors 60-62 are non-conductive and all N-channel transistors 64-66 are conductive, pulling the base of transistor 63 to VSS. Transistor 63 is non-conductive, so the voltage at node N101 is pulled low by approximately VSS through transistors 67-69.

When pass gate 57 receives unilateral delay control signal WED as a logic low signal (indicating a read cycle), P-channel transistor 70 is conductive. The inverter 72 receives the one-sided delay control signal WED as a logic low voltage and supplies a logic high voltage to the N-channel transistor 71, which makes the transistor 71 conductive. When transistors 70 and 71 are on (or conductive), there is a conduction path between nodes N101 and N102, making the voltage at node N102 approximately equal to the voltage at node N101. The latch section 58 receives a signal through the pass gate 57 at the node N102 when the one-sided delay control signal WED is a logic low, and provides the output signal RP0.

When pass gate 57 receives unilateral delay control signal WED as a logic high voltage (indicating a write cycle), P-channel transistor 70 and N-channel transistor 71 are turned off (or non-conductive), which prevents the voltage level at node N102 from going through Voltage at the node Niol to be affected. Therefore, pass gate 57 effectively decouples row predecoder 42a from row selection 38. The latch section 58 holds the output signal RP0 at a logic level that corresponds to the logic level before the one-sided delay control signal WED became a logic high signal. The latch section 58 maintains the logic level of the output signal RPO until the unilateral delay control signal WED becomes a logic low signal, thereby forming a conduction path between the nodes N101 and N102.

The N-channel transistor 71 in the embodiment illustrated in FIG. 2 is shown as a low-threshold N-channel transistor to reduce the switching delay of the pass gate 57. The low-threshold N-channel transistor 71 has a threshold voltage (VT) of approximately 0.5 volts. In other embodiments, a normal N-channel transistor may be used for the low-threshold N-channel transistor.

If the voltage at node N102 is logic high, the output of inverter 73 is logic low and transistor 74 is off (or non-conductive). Transistor 75 is conductive and helps prevent transistor 74 from base-emitter reverse bias. Transistor 76 is conductive, reducing the voltage at the emitter of transistor 74 to VSS so that output RP0 is logic low, equal to approximately Vss. Inverter 77 receives a logic low voltage and amplifies the logic high state at node N102. The inverter 77 therefore 'locks' the logic level of the output signal RP0. Inverter 77 is sized to provide a weak latch so that the logic level held by latch section 58 can be overwritten when pass gate 57 becomes conductive, allowing a new address signal to pass through.

If the voltage at node N102 is logic low, the output of inverter 73 is logic high and transistor 74 is conductive. Both transistors 75 and 76 are non-conductive, which allows the output signal RP0 to be pulled to a logic high level. The voltage received by inverter 77 is logic high, so the logic low output is provided to node N102 to provide a weak latch for the logic low voltage on node N102 that can be overwritten if pass gate 57 becomes conductive and allows a new signal to pass.

FIG. 3 shows a timing diagram of some of the various signals of memory 20 of FIG. 1. It should be noted that the time intervals and logic levels illustrated in FIG. 3 are not drawn to scale and only to represent the sequence and the relationship of some of the signals during a write cycle of memory 20. At time t0, the address and the write enable signal / W change from logic high to logic low, which indicates the start of a write cycle. It should be noted that in other embodiments, the write enable signal / W may go logic low some time after time t0. In response to the address change, the pre-decoded row address changes after a relatively short propagation delay. In addition, the word line (WL) changes in response to and after the pre-decoded row address has changed. The one-sided delay control signal WED changes from logic low to logic high at time t1, after a predetermined delay, in response to the change in write enable signal / W from logic high to logic low. At time t1, the one-sided delay control signal WED causes the pre-decoded row address to be locked. The length of the predetermined delay is long enough to ensure that there is a valid pre-decoded row address before the pre-decoded row address is locked.

The time interval between the address change at time t2 and the time when the write enable signal / W becomes logic high is known as the THWAX specification. Typically, the write enable signal / W becomes inactive at the same time as or before the address change, in which case THWAX is zero. In the case illustrated by Fig. 3, THWAX is negative, that is, the write enable signal / W becomes inactive after the address changes. If this occurs, bit line equalization cannot be accomplished before the word line changes, causing a value to be written into the memory cell selected by the new word line, thereby destroying the value. In the preferred embodiment, the row address is latched in row predecoder 42. This prevents the word line (WL) from changing until time t3 when the one-sided deceleration control signal WED changes to a logic low. This ensures that bit line (BL) equalization always occurs before the word line changes.

FIG. 4 illustrates a portion of the write control circuit 44 of the memory 20 of FIG. 1 in accordance with the present invention in a partially schematic representation and in a partial block representation. The write control circuit 44 includes an ECL logic gate 90. Additional circuitry is provided in the write control circuit 44 to provide the internal core write signal \ X \ TO \ (WIC) and the internal chip select signal / CSI, but they are not shown in FIG. 4. The ECL logic gate 90 is a conventional ECL logic gate and includes resistors 91 and 92, NPN transistors 931 94 and 96-101 and N-channel transistors 95 and 102-106. Resistor 91 has a first terminal that is connected to a positive power supply voltage terminal that is labeled 'VDD' and a second connector that is connected to a node labeled 'N103'. Resistor 92 has a first terminal connected to VDD and a second terminal connected to a node labeled 'N104'. NPN transistor 93 has a collector connected to the second terminal of resistor 91 at node N103, a base and an emitter. NPN transistor 94 has a collector connected to the second terminal of resistor 92 at node N104, a base, and an emitter connected to the emitter of transistor 93. N-channel transistor 95 has a drain connected to the emitters of transistors 93 and 94, a gate for receiving a bias voltage labeled 'NBIAS', and a source connected to a negative power supply voltage terminal labeled 'VSS 'is referred to, is connected to. NPN transistor 96 has a collector connected to VDD, a base for receiving external write enable signal / W, and an emitter. NPN transistor 97 has a collector connected to VDD, a base for receiving the external chip select signal / CS and an emitter connected to the base of transistor 93. N-channel transistor 102 has a drain connected to the emitter of transistor 96, a gate for receiving NBIAS, and a source connected to VSS. NPN transistor 98 has a collector connected to the second terminal of resistor 91 at node N103, a base connected to the emitter of transistor 96, and an emitter connected to the emitters of transistors 93 and 94 is on. N-channel transistor 103 has a drain connected to the emitter of transistor 97, a gate for receiving bias NBIAS, and a source connected to VSS. NPN transistor 99 has a collector connected to VDD, a base for receiving a reference voltage labeled 'VREF', and an emitter connected to the base of transistor 94. N-channel transistor 104 has a drain connected to the emitter of transistor 99, a gate for receiving bias voltage NBIAS, and a source connected to VSS. NPN transistor 100 has a collector connected to VDD, a base connected to the collector of transistor 93 at node N103, and an emitter connected to a node labeled 'N105' for delivery an internal write signal labeled 'WI'. N-channel transistor 105 has a drain connected to the emitter of transistor 100 at node N105, a gate for receiving bias NBIAS, and a source connected to VSS. NPN transistor 101 has a collector connected to VDD, a base connected to the collector of transistor 94 at node N104, and an emitter connected to a node labeled 'N106' for delivery an internal write signal labeled '/ WI'. N-channel transistor 106 has a drain connected to the emitter of transistor 101 at node N106, a gate for receiving bias voltage NBIAS, and a source connected to VSS. The operation of the ECL logic gate 90 will be described later in the discussion of FIG. 5.

5 illustrates in schematic form the one-sided delay circuit 45 of the memory of FIG. 1 in accordance with the present invention. The one-sided delay circuit 45 includes a level converter 123, a low power level converter 121, a delay stage 128 and an output stage 145. The level converter 123 includes the P-channel transistors 124 and 125 and the N-channel transistors 126 and 127. P-channel transistor 124 has a source connected to VDD, a gate for receiving internal write signal WI, and a drain. P-channel transistor 125 has a source connected to VDD, a gate for receiving the internal write signal / WI, and a drain. N-channel transistor 126 has a drain and a gate connected to the drain of transistor 124 and a source connected to VSS. N-channel transistor 127 has a drain connected to the drain of transistor 125, a gate connected to the drain of transistor 124, and a source connected to VSS.

Delay stage 128 includes inverters 129-135, P-channel transistors 136 and 137 and N-channel transistors 138 and 139. Transistors 136-139 form a NOR gate 122. Inverters 129-135 are connected to the input terminal of inverter 129 which is connected to connected to the drain of transistor 125, connected in series. The output of inverter 129 is connected to the input of inverter 130, and so on.

P-channel transistor 136 has a source connected to VDD, a gate connected to the gate of transistor 125 and used to receive the internal write signal / WI, and a drain. P-channel transistor 137 has a source connected to the drain of transistor 136, a gate connected to the output of inverter 135, and a drain. N-channel transistor 138 has a drain connected to the drain of transistor 137, a gate connected to the drain of transistor 124, and a source connected to VSS. N-channel transistor 139 has a drain connected to the drain of transistor 137, a gate connected to the gate of transistor 137, and a source connected to VSS.

The low power level converter 121 includes P-channel transistors 141, 142 and 145 and N-channel transistors 143, 144 and 146. The P-channel transistor 145 has a source connected to VDD, a gate for receiving the unilateral delay control signal WED and a drain on. P-channel transistor 141 has a source connected to the drain of transistor 145, a gate for receiving the internal write signal / WI, and a drain. P-channel transistor 142 has a source connected to VDD, a gate for receiving internal write signal WI, and a drain. N-channel transistor 143 has a drain and a gate connected to the drain of transistor 141 and a source connected to Vss. N-channel transistor 144 has a drain connected to the drain of transistor 142, a gate connected to the drain of transistor 141, and a source connected to Vss. N-channel transistor 146 has a first drain / source terminal connected to the drain of transistor 141, a gate connected to the gate of transistor 145 for receiving the unilateral delay control signal WED and a second drain / source Terminal connected to the drain of transistor 142 on.

Output stage 145 includes NPN transistors 140 and 147, P-channel transistor 148 and N-channel transistors 149 and 150. NPN transistor 140 has a collector connected to VDD, a base connected to the drain of transistor 137 and an emitter for supplying the one-sided delay control signal WED. NPN transistor 147 has a collector connected to the emitter of transistor 140, a base and an emitter connected to VSS. P-channel transistor 148 has a source connected to the base of transistor 140, a gate connected to VSS, and a drain connected to the emitter of transistor 140. N-channel transistor 149 has a drain connected to the emitter of transistor 140, a gate connected to the drain of transistor 142, and a source connected to the base of transistor 147. N-channel transistor 150 has a drain connected to the base of transistor 147, a gate connected to VDD, and a source connected to VSS.

Referring again to the ECL logic gate 90 of FIG. 4, transistors 96 and 102 form an emitter follower input circuit that drops the voltage received at the base of transistor 98 to a VBE (approximately 0.8 volts) lowers the voltage of the write enable signal / W. Transistors 97 and 103 form another emitter follower input circuit which lowers the voltage received at the base of transistor 93 to a VBE below the chip enable signal / CS. A differential amplifier is formed by resistors 91 and 92, transistors 93 and 94 and transistor 95. A reference voltage VREF is received at the base of transistor 99, which lowers the reference voltage VREF one VBE before it is supplied to the base of transistor 94. The collector of transistor 93 provides a logic NOR output of the write enable signal / W and the chip select signal / CS at node N103. The collector of transistor 94 provides a logic OR output of write enable signal / W and chip select signal / CS at node N104. The reference voltage VREF is chosen so that the voltage received by the base of transistor 94 is at the midpoint of the logic swings of the write enable signal 1W and the chip select signal / CS. Transistors 100 and 105 form an emitter follower output section which is connected to the collector of transistor 93 at node N103. Transistors 101 and 106 form an emitter follower output section which is connected to the collector of transistor 94 at node N104. The internal write signals WI and / WI are complementary internal logic signals and are supplied at intermediate, or analog, logic levels.

During a read cycle of memory 20, ECL logic gate 90 receives ECL level write enable signal / W logic high and chip select signal / CS logic low. Transistor 93 is non-conductive and transistor 98 is conductive. A current through transistor 95, which is I 95. is controlled by transistor 98 so that the voltage at node N103 is equal to a logic low voltage of VDD minus I 95 R 91. where R ?? the resistance of the resistor is 91. The voltage at node N104 is logically high, approximately equal to VDD. The internal write signal WI is a logic low voltage that is equal to the voltage at node N103 minus one VBE through transistor 100, and the internal write signal / WI is a logic high voltage that is equal to the voltage at node N104 minus is a VDE across transistor 101.

The one-sided delay circuit 45 provides the one-sided delay control signal WED at a logic high CMOS voltage level in response to the wafer enable signal / W and chip select signal / CS both being logic low ECL voltages (indicating a write cycle). When the write enable signal / W is a logic high ECL voltage and the chip select signal / CS is a logic low ECL voltage (indicating a read cycle), the one-sided delay control signal WED is supplied to a logic low CMOS voltage level. When the write enable signal / W transitions from a logic high to a logic low, the one-sided delay control signal WED goes from logic low to logic high after a built-in delay provided by delay stage 128. When the write enable signal / W transitions from a logic low to a logic high voltage, the single-sided delay control signal WED transitions from a logic high voltage to a logic low voltage without any delay provided by delay stage 128. Switching times are improved because the intermediate logic levels from the ECL logic gate 90 are used instead of the full CMOS logic levels. A logically high intermediate level is approximately -0.8 volts and a logically low intermediate level is approximately -2.4 volts when VDD is equal to zero volts and Vss is approximately -5.2 volts.

During a read cycle (the write enable signal / W is high ECL logic), the internal write signal WI is at a logic low intermediate level and the internal write signal / WI is at a logic high intermediate level. The level converter 123, the transistor 124 is conductive and the transistor 125 is non-conductive. Transistor 126 is conductive, allowing current to flow through transistors 124 and 126 between VDD and VSS. Transistor 127 is conductive, which pulls the voltage at the input of inverter 129 to a logic low voltage that is equal to approximately Vss. A logic low signal at the input of inverter 129 brings the output of inverter 135 to a logic high voltage that is approximately equal to VDD. Inverters 127 - 135 operate at full stroke at CMOS logic levels. Transistors 136 and 137 are non-conductive, transistor 138 is conductive, thereby reducing the voltage at the base of bipolar pull-up transistor 140 to Vss, causing transistor 140 to be non-conductive. The one-sided delay control signal WED is therefore supplied to the emitter of transistor 140 as a logic low signal.

At the same time, the low power level converter 121 receives the internal write signals WI and / WI at the gates of transistors 142 and 141, respectively. Transistor 142 is conductive and transistor 141 is non-conductive. Transistors 143 and 144 are non-conductive, which prevents any flow of current between power supply terminals VDD and VSS. Transistor 145 receives a logic low single-sided delay control signal WED and is conductive. Transistor 146 is therefore non-conductive. Transistors 149 and 150 are conductive, causing bipolar transistor 147 to be conductive, thereby pulling the one-sided delay control signal WED to a logic low.

In order to start a write cycle of the memory 20, the write enable signal / W and the chip select signal / CS are changed to logic low voltages. Therefore, transistors 93 and 98 are non-conductive and transistor 94 is conductive so that current 195 is controlled by transistor 94. The voltage at node N103 is a logic high voltage which is equal to approximately VDD and the voltage at node N104 is a logic low voltage which is equal to approximately VDD minus I 95 R 92. where R & sub2; & sub2; represents the resistance of resistor 92. The internal write signal WI is a logic high voltage that is equal to the voltage at node N103 minus one VBE across transistor 100, and the internal write signal / WI is a logic low voltage that is equal to the voltage at node N104 minus is a VBE across transistor 101.

Transistor 124 is non-conductive and transistor 125 is conductive. Transistors 126 and 127 are both non-conductive, so there is no direct current flowing through level converter 123. Because transistor 124 is non-conductive, transistor 138 is also non-conductive. A logic high voltage approximately equal to VDD is provided to the input of inverter 129, thereby providing a logic low voltage to the output of inverter 135. Transistor 136 is conductive and transistor 137 is delayed conductive by the time it takes for the outputs of the inverter chain having inverters 129-135 to change states. A conduction path is created between VDD and the base of transistor 140 when both transistors 136 and 137 become conductive, causing bipolar transistor 140 to be biased into a conduction state. The transistor 141 of the low power level converter 121 is conductive and the transistor 142 is non-conductive. Because the one-sided delay control signal WED is logic high, transistor 146 is conductive, causing transistors 143 and 144 to be conductive. The gate of transistor 149 is pulled to approximately VSS, making transistor 149 substantially non-conductive. Transistor 145 is non-conductive, which prevents a conduction path from being created between VDD and VSS. Therefore, direct current is not allowed to flow into the low-power level converter 121. Because transistor 149 is non-conductive, bipolar transistor 147 is also non-conductive, allowing the unilateral delay control signal WED to be pulled to approximately VDD. The series CMOS inverters 127-135 delay transistor 137 from turning on by approximately 4 nannoseconds. The length of the delay can be easily controlled by increasing or decreasing the number of inverters in the inverter chain.

When going from a write cycle to a read cycle, the one-sided delay control signal WED goes from logic high to logic low in response to the write enable signal / W going from logic low to logic high. No delay is desired when the one-sided delay control signal WED changes from logic high to logic low for the write-to-read transition. Upon entering the read cycle , transistor 136 immediately becomes non-conductive and transistor 138 immediately conductive, reducing the voltage at the base of transistor 140 to VSS. The transistor 140 becomes non-conductive and the output stage 145 brings the one-sided delay control signal WED to a logic low voltage.

Transistors 136 and 138 can change states very quickly because the intermediate logic levels of ECL logic gate 90 are used. Using the intermediate logic levels reduces the propagation delay that occurs when full CMOS levels are used. But transistors 137 and 139 change state slowly due to the series connected inverters 129-135. The base of transistor 140 cannot be charged to VDD until logic 135 is supplied to the output terminal of inverter 135. To discharge the base of transistor 140, transistor 138 turns on (becomes conductive) very quickly because the gate of transistor 138 is connected to the drain of transistor 124, and thus the delay caused by the series inverters 129-135 is avoided.

The transistors 136-139 are connected to form a CMOS NOR gate 122 with two inputs. NOR gate 122 may operate on the intermediate logic levels of signals WI and / WI. NOR gate 122 operates like a conventional NOR gate, except that the gate of transistor 138 is connected to the gates of transistors 126 and 127. If the NOR gate 122 were a conventional NOR gate, the gate of transistor 138 would be connected to the gate of transistor 136. If the internal write signal / WI is logic low, the P-channel transistor 136 will become conductive, but the logic low level is not low enough to render an N-channel transistor non-conductive. Therefore, the gate of transistor 138 is coupled to the gates of transistors 126 and 127 so that the gate of transistor 138 is supplied with a voltage that renders transistor 138 non-conductive when transistor 136 is conductive.

Level converters 123 and 121 are interchangeable in most applications, but it is a disadvantage of low power level converter 121 that it requires more area on the integrated circuit. In the preferred embodiment, the low power level converter 121 is used with a conventional level converter 123 to reduce the power consumption of the one-sided delay circuit 45, which is still somewhat space-saving. In other embodiments, two low power level converters 121 can be used, which further reduces the power consumption of the one-sided delay circuit 45.

While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention can be modified in various ways and can take many forms other than those specifically described and described above has been. For example, other types of reference and bias circuits can be used for those that have been illustrated. In addition, the row address latch can be implemented in a location other than the row predecoder. In addition, a different method of latching the pre-decoded row address signal can be used. Furthermore, delay stage 128 can be implemented using a series of ECL stages before level converters 121 and 123. Accordingly, the appended claims are intended to cover all modifications of the invention that fall within the scope of the invention as specified in the appended claims.